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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +01002/*
3 * [origin: Linux kernel drivers/watchdog/at91sam9_wdt.c]
4 *
Prasanthi Chellakumar1473f6a2018-10-09 11:46:40 -07005 * Watchdog driver for AT91SAM9x processors.
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +01006 *
7 * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +01009 */
10
11/*
12 * The Watchdog Timer Mode Register can be only written to once. If the
13 * timeout need to be set from U-Boot, be sure that the bootstrap doesn't
14 * write to this register. Inform Linux to it too
15 */
16
Simon Glassf7ae49f2020-05-10 11:40:05 -060017#include <log.h>
Reinhard Meyer7f6ed7f2011-02-04 20:17:33 +010018#include <asm/io.h>
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010019#include <asm/arch/at91_wdt.h>
Prasanthi Chellakumar1473f6a2018-10-09 11:46:40 -070020#include <common.h>
Stefan Roese6c04bd32019-04-02 10:57:19 +020021#include <div64.h>
Prasanthi Chellakumar1473f6a2018-10-09 11:46:40 -070022#include <dm.h>
23#include <errno.h>
24#include <wdt.h>
25
26DECLARE_GLOBAL_DATA_PTR;
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010027
28/*
29 * AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
30 * use this to convert a watchdog
Prasanthi Chellakumar1473f6a2018-10-09 11:46:40 -070031 * value from seconds.
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010032 */
Prasanthi Chellakumar1473f6a2018-10-09 11:46:40 -070033#define WDT_SEC2TICKS(s) (((s) << 8) - 1)
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010034
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010035/*
36 * Set the watchdog time interval in 1/256Hz (write-once)
37 * Counter is 12 bit.
38 */
Stefan Roese6c04bd32019-04-02 10:57:19 +020039static int at91_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010040{
Prasanthi Chellakumar1473f6a2018-10-09 11:46:40 -070041 struct at91_wdt_priv *priv = dev_get_priv(dev);
Stefan Roese6c04bd32019-04-02 10:57:19 +020042 u64 timeout;
43 u32 ticks;
Prasanthi Chellakumar1473f6a2018-10-09 11:46:40 -070044
Stefan Roese6c04bd32019-04-02 10:57:19 +020045 /* Calculate timeout in seconds and the resulting ticks */
46 timeout = timeout_ms;
47 do_div(timeout, 1000);
48 timeout = min_t(u64, timeout, WDT_MAX_TIMEOUT);
49 ticks = WDT_SEC2TICKS(timeout);
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010050
51 /* Check if disabled */
Prasanthi Chellakumar1473f6a2018-10-09 11:46:40 -070052 if (readl(priv->regs + AT91_WDT_MR) & AT91_WDT_MR_WDDIS) {
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010053 printf("sorry, watchdog is disabled\n");
54 return -1;
55 }
56
57 /*
58 * All counting occurs at SLOW_CLOCK / 128 = 256 Hz
59 *
60 * Since WDV is a 12-bit counter, the maximum period is
61 * 4096 / 256 = 16 seconds.
62 */
Prasanthi Chellakumar1473f6a2018-10-09 11:46:40 -070063 priv->regval = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */
Achim Ehrlichf936aa02010-03-17 14:50:29 +010064 | AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */
65 | AT91_WDT_MR_WDD(0xfff) /* restart at any time */
Stefan Roese6c04bd32019-04-02 10:57:19 +020066 | AT91_WDT_MR_WDV(ticks); /* timer value */
Prasanthi Chellakumar1473f6a2018-10-09 11:46:40 -070067 writel(priv->regval, priv->regs + AT91_WDT_MR);
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010068
69 return 0;
70}
71
Prasanthi Chellakumar1473f6a2018-10-09 11:46:40 -070072static int at91_wdt_stop(struct udevice *dev)
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010073{
Prasanthi Chellakumar1473f6a2018-10-09 11:46:40 -070074 struct at91_wdt_priv *priv = dev_get_priv(dev);
75
76 /* Disable Watchdog Timer */
77 priv->regval |= AT91_WDT_MR_WDDIS;
78 writel(priv->regval, priv->regs + AT91_WDT_MR);
79
80 return 0;
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010081}
82
Prasanthi Chellakumar1473f6a2018-10-09 11:46:40 -070083static int at91_wdt_reset(struct udevice *dev)
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010084{
Prasanthi Chellakumar1473f6a2018-10-09 11:46:40 -070085 struct at91_wdt_priv *priv = dev_get_priv(dev);
86
87 writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, priv->regs + AT91_WDT_CR);
88
89 return 0;
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010090}
Prasanthi Chellakumar1473f6a2018-10-09 11:46:40 -070091
92static const struct wdt_ops at91_wdt_ops = {
93 .start = at91_wdt_start,
94 .stop = at91_wdt_stop,
95 .reset = at91_wdt_reset,
96};
97
98static const struct udevice_id at91_wdt_ids[] = {
99 { .compatible = "atmel,at91sam9260-wdt" },
100 {}
101};
102
103static int at91_wdt_probe(struct udevice *dev)
104{
105 struct at91_wdt_priv *priv = dev_get_priv(dev);
106
107 priv->regs = dev_remap_addr(dev);
108 if (!priv->regs)
109 return -EINVAL;
110
Prasanthi Chellakumar1473f6a2018-10-09 11:46:40 -0700111 debug("%s: Probing wdt%u\n", __func__, dev->seq);
112
113 return 0;
114}
115
Walter Lozanoe3e24702020-06-25 01:10:04 -0300116U_BOOT_DRIVER(atmel_at91sam9260_wdt) = {
117 .name = "atmel_at91sam9260_wdt",
Prasanthi Chellakumar1473f6a2018-10-09 11:46:40 -0700118 .id = UCLASS_WDT,
119 .of_match = at91_wdt_ids,
120 .priv_auto_alloc_size = sizeof(struct at91_wdt_priv),
121 .ops = &at91_wdt_ops,
122 .probe = at91_wdt_probe,
123};