| Felix Brack | fdce9d3 | 2018-12-05 14:53:42 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2017 Texas Instruments, Inc. |
| 3 | * |
| 4 | * This software is licensed under the terms of the GNU General Public |
| 5 | * License version 2, as published by the Free Software Foundation, and |
| 6 | * may be copied, distributed, and modified under those terms. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | #ifndef __DT_BINDINGS_CLK_AM3_H |
| 14 | #define __DT_BINDINGS_CLK_AM3_H |
| 15 | |
| 16 | #define AM3_CLKCTRL_OFFSET 0x0 |
| 17 | #define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) |
| 18 | |
| 19 | /* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ |
| 20 | |
| 21 | /* l4_per clocks */ |
| 22 | #define AM3_L4_PER_CLKCTRL_OFFSET 0x14 |
| 23 | #define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET) |
| 24 | #define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14) |
| 25 | #define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18) |
| 26 | #define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c) |
| 27 | #define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24) |
| 28 | #define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28) |
| 29 | #define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c) |
| 30 | #define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30) |
| 31 | #define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34) |
| 32 | #define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38) |
| 33 | #define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c) |
| 34 | #define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40) |
| 35 | #define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44) |
| 36 | #define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48) |
| 37 | #define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c) |
| 38 | #define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50) |
| 39 | #define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60) |
| 40 | #define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68) |
| 41 | #define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c) |
| 42 | #define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70) |
| 43 | #define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74) |
| 44 | #define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78) |
| 45 | #define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c) |
| 46 | #define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80) |
| 47 | #define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84) |
| 48 | #define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88) |
| 49 | #define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90) |
| 50 | #define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94) |
| 51 | #define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0) |
| 52 | #define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac) |
| 53 | #define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0) |
| 54 | #define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4) |
| 55 | #define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc) |
| 56 | #define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0) |
| 57 | #define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4) |
| 58 | #define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc) |
| 59 | #define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4) |
| 60 | #define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8) |
| 61 | #define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc) |
| 62 | #define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0) |
| 63 | #define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8) |
| 64 | #define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec) |
| 65 | #define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0) |
| 66 | #define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4) |
| 67 | #define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8) |
| 68 | #define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc) |
| 69 | #define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100) |
| 70 | #define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c) |
| 71 | #define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110) |
| 72 | #define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120) |
| 73 | #define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130) |
| 74 | #define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c) |
| 75 | |
| 76 | /* l4_wkup clocks */ |
| 77 | #define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4 |
| 78 | #define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET) |
| 79 | #define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4) |
| 80 | #define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8) |
| 81 | #define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc) |
| 82 | #define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14) |
| 83 | #define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0) |
| 84 | #define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4) |
| 85 | #define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8) |
| 86 | #define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc) |
| 87 | #define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0) |
| 88 | #define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4) |
| 89 | #define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8) |
| 90 | #define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4) |
| 91 | |
| 92 | /* mpu clocks */ |
| 93 | #define AM3_MPU_CLKCTRL_OFFSET 0x4 |
| 94 | #define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET) |
| 95 | #define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4) |
| 96 | |
| 97 | /* l4_rtc clocks */ |
| 98 | #define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) |
| 99 | |
| 100 | /* gfx_l3 clocks */ |
| 101 | #define AM3_GFX_L3_CLKCTRL_OFFSET 0x4 |
| 102 | #define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET) |
| 103 | #define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4) |
| 104 | |
| 105 | /* l4_cefuse clocks */ |
| 106 | #define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20 |
| 107 | #define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET) |
| 108 | #define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20) |
| 109 | |
| 110 | /* XXX: Compatibility part end */ |
| 111 | |
| 112 | /* l4ls clocks */ |
| 113 | #define AM3_L4LS_CLKCTRL_OFFSET 0x38 |
| 114 | #define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET) |
| 115 | #define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38) |
| 116 | #define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c) |
| 117 | #define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40) |
| 118 | #define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44) |
| 119 | #define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48) |
| 120 | #define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c) |
| 121 | #define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50) |
| 122 | #define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60) |
| 123 | #define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c) |
| 124 | #define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70) |
| 125 | #define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74) |
| 126 | #define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78) |
| 127 | #define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c) |
| 128 | #define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80) |
| 129 | #define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84) |
| 130 | #define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88) |
| 131 | #define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x90) |
| 132 | #define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac) |
| 133 | #define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0) |
| 134 | #define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4) |
| 135 | #define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0) |
| 136 | #define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4) |
| 137 | #define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xcc) |
| 138 | #define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd4) |
| 139 | #define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd8) |
| 140 | #define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec) |
| 141 | #define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0) |
| 142 | #define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf4) |
| 143 | #define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x10c) |
| 144 | #define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110) |
| 145 | #define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130) |
| 146 | |
| 147 | /* l3s clocks */ |
| 148 | #define AM3_L3S_CLKCTRL_OFFSET 0x1c |
| 149 | #define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET) |
| 150 | #define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x1c) |
| 151 | #define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x30) |
| 152 | #define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34) |
| 153 | #define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68) |
| 154 | #define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0xf8) |
| 155 | |
| 156 | /* l3 clocks */ |
| 157 | #define AM3_L3_CLKCTRL_OFFSET 0x24 |
| 158 | #define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET) |
| 159 | #define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x24) |
| 160 | #define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28) |
| 161 | #define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c) |
| 162 | #define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x94) |
| 163 | #define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0) |
| 164 | #define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc) |
| 165 | #define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc) |
| 166 | #define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0) |
| 167 | #define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xfc) |
| 168 | #define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x100) |
| 169 | |
| 170 | /* l4hs clocks */ |
| 171 | #define AM3_L4HS_CLKCTRL_OFFSET 0x120 |
| 172 | #define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET) |
| 173 | #define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120) |
| 174 | |
| 175 | /* pruss_ocp clocks */ |
| 176 | #define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0xe8 |
| 177 | #define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET) |
| 178 | #define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8) |
| 179 | |
| 180 | /* cpsw_125mhz clocks */ |
| 181 | #define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14) |
| 182 | |
| 183 | /* lcdc clocks */ |
| 184 | #define AM3_LCDC_CLKCTRL_OFFSET 0x18 |
| 185 | #define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET) |
| 186 | #define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0x18) |
| 187 | |
| 188 | /* clk_24mhz clocks */ |
| 189 | #define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0x14c |
| 190 | #define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET) |
| 191 | #define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c) |
| 192 | |
| 193 | /* l4_wkup clocks */ |
| 194 | #define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4) |
| 195 | #define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0x8) |
| 196 | #define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc) |
| 197 | #define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0xb4) |
| 198 | #define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0xb8) |
| 199 | #define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc) |
| 200 | #define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0xc0) |
| 201 | #define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0xc4) |
| 202 | #define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0xc8) |
| 203 | #define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0xd4) |
| 204 | |
| 205 | /* l3_aon clocks */ |
| 206 | #define AM3_L3_AON_CLKCTRL_OFFSET 0x14 |
| 207 | #define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET) |
| 208 | #define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0x14) |
| 209 | |
| 210 | /* l4_wkup_aon clocks */ |
| 211 | #define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0 |
| 212 | #define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET) |
| 213 | #define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0) |
| 214 | |
| 215 | /* mpu clocks */ |
| 216 | #define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4) |
| 217 | |
| 218 | /* l4_rtc clocks */ |
| 219 | #define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) |
| 220 | |
| 221 | /* gfx_l3 clocks */ |
| 222 | #define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4) |
| 223 | |
| 224 | /* l4_cefuse clocks */ |
| 225 | #define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0x20) |
| 226 | |
| 227 | #endif |