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Wolfgang Denk70a20472005-09-25 15:59:01 +02001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * Copied from lubbock.h
10 *
11 * (C) Copyright 2004
12 * BEC Systems <http://bec-systems.com>
13 * Cliff Brake <cliff.brake@gmail.com>
14 * Configuation settings for the Accelent/Vibren PXA255 IDP
15 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
38#include <asm/arch/pxa-regs.h>
39
40/*
Marcel Ziswiler2a4741d2007-10-19 00:25:33 +020041 * If we are developing, we might want to start U-Boot from RAM
Wolfgang Denk70a20472005-09-25 15:59:01 +020042 * so we MUST NOT initialize critical regs like mem-timing ...
43 */
Marcel Ziswiler2a4741d2007-10-19 00:25:33 +020044#undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */
Marek Vasut65bd6a92010-10-20 21:20:07 +020045#define CONFIG_SYS_TEXT_BASE 0x0
Wolfgang Denk70a20472005-09-25 15:59:01 +020046
47/*
48 * define the following to enable debug blinks. A debug blink function
49 * must be defined in memsetup.S
50 */
51#undef DEBUG_BLINK_ENABLE
52#undef DEBUG_BLINKC_ENABLE
53
54/*
55 * High Level Configuration Options
56 * (easy to change)
57 */
Marek Vasutabc20ab2011-11-26 07:20:07 +010058#define CONFIG_CPU_PXA25X 1 /* This is an PXA250 CPU */
Wolfgang Denk70a20472005-09-25 15:59:01 +020059
60#undef CONFIG_LCD
61#ifdef CONFIG_LCD
62#define CONFIG_SHARP_LM8V31
63#endif
64
65#define CONFIG_MMC 1
Marcel Ziswiler2a4741d2007-10-19 00:25:33 +020066#define CONFIG_DOS_PARTITION 1
Helmut Raiger9660e442011-10-20 04:19:47 +000067#define CONFIG_BOARD_LATE_INIT
Wolfgang Denk70a20472005-09-25 15:59:01 +020068
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020069/* we will never enable dcache, because we have to setup MMU first */
Aneesh Ve47f2db2011-06-16 23:30:48 +000070#define CONFIG_SYS_DCACHE_OFF
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020071
Wolfgang Denk70a20472005-09-25 15:59:01 +020072/*
73 * Size of malloc() pool
74 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
Wolfgang Denk70a20472005-09-25 15:59:01 +020076
77/*
78 * PXA250 IDP memory map information
79 */
80
81#define IDP_CS5_ETH_OFFSET 0x03400000
82
83
84/*
85 * Hardware drivers
86 */
Ben Warren7194ab82009-10-04 22:37:03 -070087#define CONFIG_SMC91111
Wolfgang Denk70a20472005-09-25 15:59:01 +020088#define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
89#define CONFIG_SMC_USE_32_BIT 1
90/* #define CONFIG_SMC_USE_IOFUNCS */
91
92/* the following has to be set high -- suspect something is wrong with
93 * with the tftp timeout routines. FIXME!!!
94 */
95#define CONFIG_NET_RETRY_COUNT 100
96
97/*
98 * select serial console configuration
99 */
Jean-Christophe PLAGNIOL-VILLARD379be582009-05-16 22:48:46 +0200100#define CONFIG_PXA_SERIAL
Wolfgang Denk70a20472005-09-25 15:59:01 +0200101#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
Marek Vasutce6971c2012-09-12 12:36:25 +0200102#define CONFIG_CONS_INDEX 3
Wolfgang Denk70a20472005-09-25 15:59:01 +0200103
104/* allow to overwrite serial and ethaddr */
105#define CONFIG_ENV_OVERWRITE
106
107#define CONFIG_BAUDRATE 115200
108
Wolfgang Denk70a20472005-09-25 15:59:01 +0200109
Jon Loeliger26a34562007-07-04 22:33:17 -0500110/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500111 * BOOTP options
112 */
113#define CONFIG_BOOTP_BOOTFILESIZE
114#define CONFIG_BOOTP_BOOTPATH
115#define CONFIG_BOOTP_GATEWAY
116#define CONFIG_BOOTP_HOSTNAME
117
118
119/*
Jon Loeliger26a34562007-07-04 22:33:17 -0500120 * Command line configuration.
121 */
122#include <config_cmd_default.h>
123
Jon Loeliger26a34562007-07-04 22:33:17 -0500124#define CONFIG_CMD_FAT
125#define CONFIG_CMD_DHCP
126
Wolfgang Denk70a20472005-09-25 15:59:01 +0200127#define CONFIG_BOOTDELAY 3
128#define CONFIG_BOOTCOMMAND "bootm 40000"
129#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
Wolfgang Denk25dbe982008-07-13 23:07:35 +0200130
131#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
132#define CONFIG_SETUP_MEMORY_TAGS 1
133/* #define CONFIG_INITRD_TAG 1 */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200134
135/*
136 * Current memory map for Vibren supplied Linux images:
137 *
138 * Flash:
139 * 0 - 0x3ffff (size = 0x40000): bootloader
140 * 0x40000 - 0x13ffff (size = 0x100000): kernel
141 * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
142 *
143 * RAM:
144 * 0xa0008000 - kernel is loaded
145 * 0xa3000000 - Uboot runs (48MB into RAM)
146 *
147 */
148
149#define CONFIG_EXTRA_ENV_SETTINGS \
150 "prog_boot_mmc=" \
151 "mw.b 0xa0000000 0xff 0x40000; " \
152 "if mmcinit && " \
153 "fatload mmc 0 0xa0000000 u-boot.bin; " \
154 "then " \
155 "protect off 0x0 0x3ffff; " \
156 "erase 0x0 0x3ffff; " \
157 "cp.b 0xa0000000 0x0 0x40000; " \
158 "reset;" \
159 "fi\0" \
160 "prog_uzImage_mmc=" \
161 "mw.b 0xa0000000 0xff 0x100000; " \
162 "if mmcinit && " \
163 "fatload mmc 0 0xa0000000 uzImage; " \
164 "then " \
165 "protect off 0x40000 0xfffff; " \
166 "erase 0x40000 0xfffff; " \
167 "cp.b 0xa0000000 0x40000 0x100000; " \
168 "fi\0" \
169 "prog_jffs_mmc=" \
170 "mw.b 0xa0000000 0xff 0x1e00000; " \
171 "if mmcinit && " \
172 "fatload mmc 0 0xa0000000 root.jffs; " \
173 "then " \
174 "protect off 0x140000 0x1f3ffff; " \
175 "erase 0x140000 0x1f3ffff; " \
176 "cp.b 0xa0000000 0x140000 0x1e00000; " \
177 "fi\0" \
178 "boot_mmc=" \
179 "if mmcinit && " \
180 "fatload mmc 0 0xa1000000 uzImage && " \
181 "then " \
182 "bootm 0xa1000000; " \
183 "fi\0" \
184 "prog_boot_net=" \
185 "mw.b 0xa0000000 0xff 0x100000; " \
186 "if bootp 0xa0000000 u-boot.bin; " \
187 "then " \
188 "protect off 0x0 0x3ffff; " \
189 "erase 0x0 0x3ffff; " \
190 "cp.b 0xa0000000 0x0 0x40000; " \
191 "reset; " \
192 "fi\0" \
193 "prog_uzImage_net=" \
194 "mw.b 0xa0000000 0xff 0x100000; " \
195 "if bootp 0xa0000000 uzImage; " \
196 "then " \
197 "protect off 0x40000 0xfffff; " \
198 "erase 0x40000 0xfffff; " \
199 "cp.b 0xa0000000 0x40000 0x100000; " \
200 "fi\0" \
201 "prog_jffs_net=" \
202 "mw.b 0xa0000000 0xff 0x1e00000; " \
203 "if bootp 0xa0000000 root.jffs; " \
204 "then " \
205 "protect off 0x140000 0x1f3ffff; " \
206 "erase 0x140000 0x1f3ffff; " \
207 "cp.b 0xa0000000 0x140000 0x1e00000; " \
208 "fi\0"
209
210
211/* "erase_env=" */
212/* "protect off" */
213
214
Jon Loeliger26a34562007-07-04 22:33:17 -0500215#if defined(CONFIG_CMD_KGDB)
Wolfgang Denk70a20472005-09-25 15:59:01 +0200216#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
217#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
218#endif
219
220/*
221 * Miscellaneous configurable options
222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_HUSH_PARSER 1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200224
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_LONGHELP /* undef to save memory */
226#ifdef CONFIG_SYS_HUSH_PARSER
227#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200228#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200230#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
232#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
233#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
234#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
235#define CONFIG_SYS_DEVICE_NULLDEV 1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
238#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200241
Micha Kalfon94a33122009-02-11 19:50:11 +0200242#define CONFIG_SYS_HZ 1000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200244
245#define RTC 1 /* enable 32KHz osc */
246
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100247#ifdef CONFIG_MMC
Marek Vasut831f8492012-09-30 10:09:49 +0000248#define CONFIG_GENERIC_MMC
249#define CONFIG_PXA_MMC_GENERIC
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100250#define CONFIG_CMD_MMC
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_MMC_BASE 0xF0000000
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100252#endif
Wolfgang Denk70a20472005-09-25 15:59:01 +0200253
254/*
Wolfgang Denk70a20472005-09-25 15:59:01 +0200255 * Physical Memory Map
256 */
Marek Vasut65bd6a92010-10-20 21:20:07 +0200257#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200258#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
259#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
260#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
261#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
262#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
263#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
264#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
265#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
266
267#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
268#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
269#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
270#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
271#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
272
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_DRAM_BASE 0xa0000000
274#define CONFIG_SYS_DRAM_SIZE 0x04000000
Wolfgang Denk70a20472005-09-25 15:59:01 +0200275
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200277
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200278#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Marek Vasut00d5ec92011-11-26 12:04:11 +0100279#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200280
Wolfgang Denk70a20472005-09-25 15:59:01 +0200281/*
282 * GPIO settings
283 */
284
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_GAFR0_L_VAL 0x80001005
286#define CONFIG_SYS_GAFR0_U_VAL 0xa5128012
287#define CONFIG_SYS_GAFR1_L_VAL 0x699a9558
288#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aa6a
289#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
290#define CONFIG_SYS_GAFR2_U_VAL 0x2
291#define CONFIG_SYS_GPCR0_VAL 0x1800400
292#define CONFIG_SYS_GPCR1_VAL 0x0
293#define CONFIG_SYS_GPCR2_VAL 0x0
294#define CONFIG_SYS_GPDR0_VAL 0xc1818440
295#define CONFIG_SYS_GPDR1_VAL 0xfcffab82
296#define CONFIG_SYS_GPDR2_VAL 0x1ffff
297#define CONFIG_SYS_GPSR0_VAL 0x8000
298#define CONFIG_SYS_GPSR1_VAL 0x3f0002
299#define CONFIG_SYS_GPSR2_VAL 0x1c000
Wolfgang Denk70a20472005-09-25 15:59:01 +0200300
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_PSSR_VAL 0x20
Wolfgang Denk70a20472005-09-25 15:59:01 +0200302
Marek Vasut65bd6a92010-10-20 21:20:07 +0200303#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
304#define CONFIG_SYS_CKEN 0x0
305
Wolfgang Denk70a20472005-09-25 15:59:01 +0200306/*
307 * Memory settings
308 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_MSC0_VAL 0x29DCA4D2
310#define CONFIG_SYS_MSC1_VAL 0x43AC494C
311#define CONFIG_SYS_MSC2_VAL 0x39D449D4
312#define CONFIG_SYS_MDCNFG_VAL 0x090009C9
313#define CONFIG_SYS_MDREFR_VAL 0x0085C017
314#define CONFIG_SYS_MDMRS_VAL 0x00220022
Marek Vasut65bd6a92010-10-20 21:20:07 +0200315#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
316#define CONFIG_SYS_SXCNFG_VAL 0x00000000
Wolfgang Denk70a20472005-09-25 15:59:01 +0200317
318/*
319 * PCMCIA and CF Interfaces
320 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_MECR_VAL 0x00000003
322#define CONFIG_SYS_MCMEM0_VAL 0x00014405
323#define CONFIG_SYS_MCMEM1_VAL 0x00014405
324#define CONFIG_SYS_MCATT0_VAL 0x00014405
325#define CONFIG_SYS_MCATT1_VAL 0x00014405
326#define CONFIG_SYS_MCIO0_VAL 0x00014405
327#define CONFIG_SYS_MCIO1_VAL 0x00014405
Wolfgang Denk70a20472005-09-25 15:59:01 +0200328
329/*
330 * FLASH and environment organization
331 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200333#define CONFIG_FLASH_CFI_DRIVER 1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200334
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_MONITOR_BASE 0
336#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
Wolfgang Denk70a20472005-09-25 15:59:01 +0200337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
339#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200340
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200342
343/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
345#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200346
347/* put cfg at end of flash for now */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200348#define CONFIG_ENV_IS_IN_FLASH 1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200349 /* Addr of Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200350#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
351#define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */
352#define CONFIG_ENV_SECT_SIZE (PHYS_FLASH_SECT_SIZE / 16)
Wolfgang Denk70a20472005-09-25 15:59:01 +0200353
354#endif /* __CONFIG_H */