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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Ley Foon Tan1b259402017-04-26 02:44:46 +08002/*
Tien Fong Cheeda0d5f62019-05-07 17:42:32 +08003 * Copyright (C) 2015-2019 Altera Corporation <www.altera.com>
Ley Foon Tan1b259402017-04-26 02:44:46 +08004 */
5
6#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
7#define __CONFIG_SOCFGPA_ARRIA10_H__
8
9#include <asm/arch/base_addr_a10.h>
Tom Rini91d27a12017-06-02 11:03:50 -040010
Ley Foon Tan1b259402017-04-26 02:44:46 +080011/* Booting Linux */
12#define CONFIG_LOADADDR 0x01000000
13#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
14
15/*
16 * U-Boot general configurations
17 */
Ley Foon Tan1b259402017-04-26 02:44:46 +080018
19/* Memory configurations */
20#define PHYS_SDRAM_1_SIZE 0x40000000
21
Ley Foon Tan1b259402017-04-26 02:44:46 +080022/*
Ley Foon Tan1b259402017-04-26 02:44:46 +080023 * Serial / UART configurations
24 */
25#define CONFIG_SYS_NS16550_MEM32
26#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
27
28/*
29 * L4 OSC1 Timer 0
30 */
31/* reload value when timer count to zero */
32#define TIMER_LOAD_VAL 0xFFFFFFFF
33
34/*
35 * Flash configurations
36 */
37#define CONFIG_SYS_MAX_FLASH_BANKS 1
38
Tien Fong Cheeda0d5f62019-05-07 17:42:32 +080039/* SPL memory allocation configuration, this is for FAT implementation */
40#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000
41
Ley Foon Tan1b259402017-04-26 02:44:46 +080042/* The rest of the configuration is shared */
43#include <configs/socfpga_common.h>
44
45#endif /* __CONFIG_SOCFGPA_ARRIA10_H__ */