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wdenkba56f622004-02-06 23:19:44 +00001/*-----------------------------------------------------------------------------+
2 *
Wolfgang Denk265817c2005-09-25 00:53:22 +02003 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
wdenkba56f622004-02-06 23:19:44 +00009 *
Wolfgang Denk265817c2005-09-25 00:53:22 +020010 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
wdenkba56f622004-02-06 23:19:44 +000013 *
Wolfgang Denk265817c2005-09-25 00:53:22 +020014 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
wdenkba56f622004-02-06 23:19:44 +000017 *
Wolfgang Denk265817c2005-09-25 00:53:22 +020018 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
wdenkba56f622004-02-06 23:19:44 +000020 *-----------------------------------------------------------------------------*/
21/*-----------------------------------------------------------------------------+
22 *
Wolfgang Denk265817c2005-09-25 00:53:22 +020023 * File Name: enetemac.c
wdenkba56f622004-02-06 23:19:44 +000024 *
Wolfgang Denk265817c2005-09-25 00:53:22 +020025 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
wdenkba56f622004-02-06 23:19:44 +000026 *
Wolfgang Denk265817c2005-09-25 00:53:22 +020027 * Author: Mark Wisner
wdenkba56f622004-02-06 23:19:44 +000028 *
29 * Change Activity-
30 *
Wolfgang Denk265817c2005-09-25 00:53:22 +020031 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
48 * include/net.h
49 * - Receive buffer descriptor ring is used to send buffers
50 * to the user
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
66 * used anymore)
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
wdenkba56f622004-02-06 23:19:44 +000070 *-----------------------------------------------------------------------------*
Wolfgang Denk265817c2005-09-25 00:53:22 +020071 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
74 * (2 EMACs) also
75 * 15-Aug-05 sr@denx.de
76 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
77 now handling all 4xx cpu's.
wdenkba56f622004-02-06 23:19:44 +000078 *-----------------------------------------------------------------------------*/
79
80#include <config.h>
wdenkba56f622004-02-06 23:19:44 +000081#include <common.h>
82#include <net.h>
83#include <asm/processor.h>
Stefan Roese2d834762007-10-23 14:03:17 +020084#include <asm/io.h>
Stefan Roeseff768cb2007-10-31 18:01:24 +010085#include <asm/cache.h>
86#include <asm/mmu.h>
wdenkba56f622004-02-06 23:19:44 +000087#include <commproc.h>
Stefan Roesed6c61aa2005-08-16 18:18:00 +020088#include <ppc4xx.h>
89#include <ppc4xx_enet.h>
wdenkba56f622004-02-06 23:19:44 +000090#include <405_mal.h>
91#include <miiphy.h>
92#include <malloc.h>
93#include "vecnum.h"
94
Stefan Roesed6c61aa2005-08-16 18:18:00 +020095/*
Wolfgang Denk0c8721a2005-09-23 11:05:55 +020096 * Only compile for platform with AMCC EMAC ethernet controller and
Stefan Roesed6c61aa2005-08-16 18:18:00 +020097 * network support enabled.
98 * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
99 */
Jon Loeliger3a1ed1e2007-07-09 18:57:22 -0500100#if defined(CONFIG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200101
Jon Loeliger3a1ed1e2007-07-09 18:57:22 -0500102#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200103#error "CONFIG_MII has to be defined!"
104#endif
wdenkba56f622004-02-06 23:19:44 +0000105
Stefan Roese1e25f952005-10-20 16:34:28 +0200106#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
107#error "CONFIG_NET_MULTI has to be defined for NetConsole"
108#endif
109
Wolfgang Denk265817c2005-09-25 00:53:22 +0200110#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
Stefan Roese1338e6a2007-10-23 14:05:08 +0200111#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
wdenkba56f622004-02-06 23:19:44 +0000112
wdenkba56f622004-02-06 23:19:44 +0000113/* Ethernet Transmit and Receive Buffers */
114/* AS.HARNOIS
115 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
116 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
117 */
Wolfgang Denk265817c2005-09-25 00:53:22 +0200118#define ENET_MAX_MTU PKTSIZE
wdenkba56f622004-02-06 23:19:44 +0000119#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
120
wdenkba56f622004-02-06 23:19:44 +0000121/*-----------------------------------------------------------------------------+
122 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
123 * Interrupt Controller).
124 *-----------------------------------------------------------------------------*/
125#define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
126#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
127#define EMAC_UIC_DEF UIC_ENET
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200128#define EMAC_UIC_DEF1 UIC_ENET1
129#define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
wdenkba56f622004-02-06 23:19:44 +0000130
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200131#undef INFO_4XX_ENET
wdenkba56f622004-02-06 23:19:44 +0000132
Wolfgang Denk265817c2005-09-25 00:53:22 +0200133#define BI_PHYMODE_NONE 0
134#define BI_PHYMODE_ZMII 1
wdenk3c74e322004-02-22 23:46:08 +0000135#define BI_PHYMODE_RGMII 2
Stefan Roese887e2ec2006-09-07 11:51:23 +0200136#define BI_PHYMODE_GMII 3
137#define BI_PHYMODE_RTBI 4
138#define BI_PHYMODE_TBI 5
Stefan Roesedbbd1252007-10-05 17:10:59 +0200139#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
140 defined(CONFIG_405EX)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200141#define BI_PHYMODE_SMII 6
142#define BI_PHYMODE_MII 7
143#endif
wdenk3c74e322004-02-22 23:46:08 +0000144
Stefan Roese1941cce2007-10-05 17:35:10 +0200145#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200146 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
147 defined(CONFIG_405EX)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200148#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
149#endif
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200150
wdenkba56f622004-02-06 23:19:44 +0000151/*-----------------------------------------------------------------------------+
152 * Global variables. TX and RX descriptors and buffers.
153 *-----------------------------------------------------------------------------*/
154/* IER globals */
155static uint32_t mal_ier;
156
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200157#if !defined(CONFIG_NET_MULTI)
Stefan Roese4f92ac32005-10-10 17:43:58 +0200158struct eth_device *emac0_dev = NULL;
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200159#endif
160
Stefan Roese1e25f952005-10-20 16:34:28 +0200161/*
162 * Get count of EMAC devices (doesn't have to be the max. possible number
163 * supported by the cpu)
Stefan Roese353f2682007-10-23 10:10:08 +0200164 *
165 * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
166 * EMAC count is possible. As it is needed for the Kilauea/Haleakala
167 * 405EX/405EXr eval board, using the same binary.
Stefan Roese1e25f952005-10-20 16:34:28 +0200168 */
Stefan Roese353f2682007-10-23 10:10:08 +0200169#if defined(CONFIG_BOARD_EMAC_COUNT)
170#define LAST_EMAC_NUM board_emac_count()
171#else /* CONFIG_BOARD_EMAC_COUNT */
Stefan Roese1e25f952005-10-20 16:34:28 +0200172#if defined(CONFIG_HAS_ETH3)
173#define LAST_EMAC_NUM 4
174#elif defined(CONFIG_HAS_ETH2)
175#define LAST_EMAC_NUM 3
176#elif defined(CONFIG_HAS_ETH1)
177#define LAST_EMAC_NUM 2
178#else
179#define LAST_EMAC_NUM 1
180#endif
Stefan Roese353f2682007-10-23 10:10:08 +0200181#endif /* CONFIG_BOARD_EMAC_COUNT */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200182
Stefan Roese5fb692c2007-01-18 10:25:34 +0100183/* normal boards start with EMAC0 */
184#if !defined(CONFIG_EMAC_NR_START)
185#define CONFIG_EMAC_NR_START 0
186#endif
187
Stefan Roesedbbd1252007-10-05 17:10:59 +0200188#if defined(CONFIG_405EX) || defined(CONFIG_440EPX)
189#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev)))
190#else
191#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * 2))
192#endif
193
Stefan Roeseff768cb2007-10-31 18:01:24 +0100194#define MAL_RX_DESC_SIZE 2048
195#define MAL_TX_DESC_SIZE 2048
196#define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
197
wdenkba56f622004-02-06 23:19:44 +0000198/*-----------------------------------------------------------------------------+
199 * Prototypes and externals.
200 *-----------------------------------------------------------------------------*/
201static void enet_rcv (struct eth_device *dev, unsigned long malisr);
202
203int enetInt (struct eth_device *dev);
204static void mal_err (struct eth_device *dev, unsigned long isr,
205 unsigned long uic, unsigned long maldef,
206 unsigned long mal_errr);
207static void emac_err (struct eth_device *dev, unsigned long isr);
208
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200209extern int phy_setup_aneg (char *devname, unsigned char addr);
210extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
211 unsigned char reg, unsigned short *value);
212extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
213 unsigned char reg, unsigned short value);
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200214
Stefan Roese353f2682007-10-23 10:10:08 +0200215int board_emac_count(void);
216
wdenkba56f622004-02-06 23:19:44 +0000217/*-----------------------------------------------------------------------------+
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200218| ppc_4xx_eth_halt
wdenkba56f622004-02-06 23:19:44 +0000219| Disable MAL channel, and EMACn
wdenkba56f622004-02-06 23:19:44 +0000220+-----------------------------------------------------------------------------*/
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200221static void ppc_4xx_eth_halt (struct eth_device *dev)
wdenkba56f622004-02-06 23:19:44 +0000222{
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200223 EMAC_4XX_HW_PST hw_p = dev->priv;
wdenkba56f622004-02-06 23:19:44 +0000224 uint32_t failsafe = 10000;
Stefan Roesedbbd1252007-10-05 17:10:59 +0200225#if defined(CONFIG_440SPE) || \
226 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
227 defined(CONFIG_405EX)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200228 unsigned long mfr;
229#endif
wdenkba56f622004-02-06 23:19:44 +0000230
Stefan Roese2d834762007-10-23 14:03:17 +0200231 out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
wdenkba56f622004-02-06 23:19:44 +0000232
233 /* 1st reset MAL channel */
234 /* Note: writing a 0 to a channel has no effect */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200235#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
236 mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
237#else
wdenkba56f622004-02-06 23:19:44 +0000238 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200239#endif
wdenkba56f622004-02-06 23:19:44 +0000240 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
241
242 /* wait for reset */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200243 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
wdenkba56f622004-02-06 23:19:44 +0000244 udelay (1000); /* Delay 1 MS so as not to hammer the register */
245 failsafe--;
246 if (failsafe == 0)
247 break;
wdenkba56f622004-02-06 23:19:44 +0000248 }
249
250 /* EMAC RESET */
Stefan Roesedbbd1252007-10-05 17:10:59 +0200251#if defined(CONFIG_440SPE) || \
252 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
253 defined(CONFIG_405EX)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200254 /* provide clocks for EMAC internal loopback */
255 mfsdr (sdr_mfr, mfr);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200256 mfr |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200257 mtsdr(sdr_mfr, mfr);
258#endif
259
Stefan Roese2d834762007-10-23 14:03:17 +0200260 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
wdenkba56f622004-02-06 23:19:44 +0000261
Stefan Roesedbbd1252007-10-05 17:10:59 +0200262#if defined(CONFIG_440SPE) || \
263 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
264 defined(CONFIG_405EX)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200265 /* remove clocks for EMAC internal loopback */
266 mfsdr (sdr_mfr, mfr);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200267 mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200268 mtsdr(sdr_mfr, mfr);
269#endif
270
271
Stefan Roesea93316c2005-10-18 19:17:12 +0200272#ifndef CONFIG_NETCONSOLE
Stefan Roesec157d8e2005-08-01 16:41:48 +0200273 hw_p->print_speed = 1; /* print speed message again next time */
Stefan Roesea93316c2005-10-18 19:17:12 +0200274#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +0200275
wdenkba56f622004-02-06 23:19:44 +0000276 return;
277}
278
Stefan Roese846b0dd2005-08-08 12:42:22 +0200279#if defined (CONFIG_440GX)
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200280int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
wdenk855a4962004-03-14 18:23:55 +0000281{
282 unsigned long pfc1;
283 unsigned long zmiifer;
284 unsigned long rmiifer;
285
286 mfsdr(sdr_pfc1, pfc1);
287 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
288
289 zmiifer = 0;
290 rmiifer = 0;
291
292 switch (pfc1) {
293 case 1:
294 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
295 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
296 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
297 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
298 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
299 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
300 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
301 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
302 break;
303 case 2:
Stefan Roesef6e495f2006-11-27 17:43:25 +0100304 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
305 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
306 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
307 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
wdenk855a4962004-03-14 18:23:55 +0000308 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
309 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
310 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
311 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
312 break;
313 case 3:
314 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
315 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
316 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
317 bis->bi_phymode[1] = BI_PHYMODE_NONE;
318 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
319 bis->bi_phymode[3] = BI_PHYMODE_NONE;
320 break;
321 case 4:
322 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
323 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
324 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
325 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
326 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
327 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
328 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
329 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
330 break;
331 case 5:
332 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
333 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
334 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
335 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
336 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
337 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
338 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
339 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
340 break;
341 case 6:
342 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
343 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
344 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
wdenk855a4962004-03-14 18:23:55 +0000345 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
346 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
347 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
wdenk855a4962004-03-14 18:23:55 +0000348 break;
349 case 0:
350 default:
351 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
352 rmiifer = 0x0;
353 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
354 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
355 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
356 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
357 break;
358 }
359
360 /* Ensure we setup mdio for this devnum and ONLY this devnum */
361 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
362
Stefan Roeseff768cb2007-10-31 18:01:24 +0100363 out_be32((void *)ZMII_FER, zmiifer);
364 out_be32((void *)RGMII_FER, rmiifer);
wdenk855a4962004-03-14 18:23:55 +0000365
366 return ((int)pfc1);
wdenk855a4962004-03-14 18:23:55 +0000367}
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200368#endif /* CONFIG_440_GX */
wdenk855a4962004-03-14 18:23:55 +0000369
Stefan Roese887e2ec2006-09-07 11:51:23 +0200370#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
371int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
372{
373 unsigned long zmiifer=0x0;
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200374 unsigned long pfc1;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200375
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200376 mfsdr(sdr_pfc1, pfc1);
377 pfc1 &= SDR0_PFC1_SELECT_MASK;
378
Wolfgang Denk2f152782007-05-05 18:23:11 +0200379 switch (pfc1) {
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200380 case SDR0_PFC1_SELECT_CONFIG_2:
Stefan Roese887e2ec2006-09-07 11:51:23 +0200381 /* 1 x GMII port */
Stefan Roese2d834762007-10-23 14:03:17 +0200382 out_be32((void *)ZMII_FER, 0x00);
383 out_be32((void *)RGMII_FER, 0x00000037);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200384 bis->bi_phymode[0] = BI_PHYMODE_GMII;
385 bis->bi_phymode[1] = BI_PHYMODE_NONE;
386 break;
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200387 case SDR0_PFC1_SELECT_CONFIG_4:
Stefan Roese887e2ec2006-09-07 11:51:23 +0200388 /* 2 x RGMII ports */
Stefan Roese2d834762007-10-23 14:03:17 +0200389 out_be32((void *)ZMII_FER, 0x00);
390 out_be32((void *)RGMII_FER, 0x00000055);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200391 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
392 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
393 break;
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200394 case SDR0_PFC1_SELECT_CONFIG_6:
Stefan Roese887e2ec2006-09-07 11:51:23 +0200395 /* 2 x SMII ports */
Stefan Roese2d834762007-10-23 14:03:17 +0200396 out_be32((void *)ZMII_FER,
397 ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
398 ((ZMII_FER_SMII) << ZMII_FER_V(1)));
399 out_be32((void *)RGMII_FER, 0x00000000);
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200400 bis->bi_phymode[0] = BI_PHYMODE_SMII;
401 bis->bi_phymode[1] = BI_PHYMODE_SMII;
402 break;
403 case SDR0_PFC1_SELECT_CONFIG_1_2:
404 /* only 1 x MII supported */
Stefan Roese2d834762007-10-23 14:03:17 +0200405 out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
406 out_be32((void *)RGMII_FER, 0x00000000);
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200407 bis->bi_phymode[0] = BI_PHYMODE_MII;
408 bis->bi_phymode[1] = BI_PHYMODE_NONE;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200409 break;
410 default:
411 break;
412 }
413
414 /* Ensure we setup mdio for this devnum and ONLY this devnum */
Stefan Roese2d834762007-10-23 14:03:17 +0200415 zmiifer = in_be32((void *)ZMII_FER);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200416 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
Stefan Roese2d834762007-10-23 14:03:17 +0200417 out_be32((void *)ZMII_FER, zmiifer);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200418
419 return ((int)0x0);
420}
421#endif /* CONFIG_440EPX */
422
Stefan Roesedbbd1252007-10-05 17:10:59 +0200423#if defined(CONFIG_405EX)
424int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
425{
426 u32 gmiifer = 0;
427
428 /*
429 * Right now only 2*RGMII is supported. Please extend when needed.
430 * sr - 2007-09-19
431 */
432 switch (1) {
433 case 1:
434 /* 2 x RGMII ports */
Stefan Roese2d834762007-10-23 14:03:17 +0200435 out_be32((void *)RGMII_FER, 0x00000055);
Stefan Roesedbbd1252007-10-05 17:10:59 +0200436 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
437 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
438 break;
439 case 2:
440 /* 2 x SMII ports */
441 break;
442 default:
443 break;
444 }
445
446 /* Ensure we setup mdio for this devnum and ONLY this devnum */
Stefan Roese2d834762007-10-23 14:03:17 +0200447 gmiifer = in_be32((void *)RGMII_FER);
Stefan Roesedbbd1252007-10-05 17:10:59 +0200448 gmiifer |= (1 << (19-devnum));
Stefan Roese2d834762007-10-23 14:03:17 +0200449 out_be32((void *)RGMII_FER, gmiifer);
Stefan Roesedbbd1252007-10-05 17:10:59 +0200450
451 return ((int)0x0);
452}
453#endif /* CONFIG_405EX */
454
Stefan Roeseff768cb2007-10-31 18:01:24 +0100455static inline void *malloc_aligned(u32 size, u32 align)
456{
457 return (void *)(((u32)malloc(size + align) + align - 1) &
458 ~(align - 1));
459}
460
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200461static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
wdenkba56f622004-02-06 23:19:44 +0000462{
Stefan Roeseff768cb2007-10-31 18:01:24 +0100463 int i;
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200464 unsigned long reg = 0;
wdenkba56f622004-02-06 23:19:44 +0000465 unsigned long msr;
466 unsigned long speed;
467 unsigned long duplex;
468 unsigned long failsafe;
469 unsigned mode_reg;
470 unsigned short devnum;
471 unsigned short reg_short;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200472#if defined(CONFIG_440GX) || \
473 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200474 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
475 defined(CONFIG_405EX)
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200476 sys_info_t sysinfo;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200477#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200478 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
479 defined(CONFIG_405EX)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100480 int ethgroup = -1;
481#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +0200482#endif
Grzegorz Bernacki2db64782007-10-01 09:51:50 +0200483#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200484 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
485 defined(CONFIG_405EX)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200486 unsigned long mfr;
487#endif
Stefan Roeseff768cb2007-10-31 18:01:24 +0100488 u32 bd_cached;
489 u32 bd_uncached = 0;
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200490
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200491 EMAC_4XX_HW_PST hw_p = dev->priv;
wdenkba56f622004-02-06 23:19:44 +0000492
493 /* before doing anything, figure out if we have a MAC address */
494 /* if not, bail */
Stefan Roese4f92ac32005-10-10 17:43:58 +0200495 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
496 printf("ERROR: ethaddr not set!\n");
wdenkba56f622004-02-06 23:19:44 +0000497 return -1;
Stefan Roese4f92ac32005-10-10 17:43:58 +0200498 }
wdenkba56f622004-02-06 23:19:44 +0000499
Stefan Roese887e2ec2006-09-07 11:51:23 +0200500#if defined(CONFIG_440GX) || \
501 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200502 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
503 defined(CONFIG_405EX)
wdenkba56f622004-02-06 23:19:44 +0000504 /* Need to get the OPB frequency so we can access the PHY */
505 get_sys_info (&sysinfo);
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200506#endif
wdenkba56f622004-02-06 23:19:44 +0000507
wdenkba56f622004-02-06 23:19:44 +0000508 msr = mfmsr ();
509 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
510
511 devnum = hw_p->devnum;
512
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200513#ifdef INFO_4XX_ENET
wdenkba56f622004-02-06 23:19:44 +0000514 /* AS.HARNOIS
515 * We should have :
Wolfgang Denk265817c2005-09-25 00:53:22 +0200516 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
wdenkba56f622004-02-06 23:19:44 +0000517 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
518 * is possible that new packets (without relationship with
519 * current transfer) have got the time to arrived before
520 * netloop calls eth_halt
521 */
522 printf ("About preceeding transfer (eth%d):\n"
523 "- Sent packet number %d\n"
524 "- Received packet number %d\n"
525 "- Handled packet number %d\n",
526 hw_p->devnum,
527 hw_p->stats.pkts_tx,
528 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
529
530 hw_p->stats.pkts_tx = 0;
531 hw_p->stats.pkts_rx = 0;
532 hw_p->stats.pkts_handled = 0;
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200533 hw_p->print_speed = 1; /* print speed message again next time */
wdenkba56f622004-02-06 23:19:44 +0000534#endif
535
Wolfgang Denk265817c2005-09-25 00:53:22 +0200536 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
537 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
wdenkba56f622004-02-06 23:19:44 +0000538
539 hw_p->rx_slot = 0; /* MAL Receive Slot */
540 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
541 hw_p->rx_u_index = 0; /* Receive User Queue Index */
542
543 hw_p->tx_slot = 0; /* MAL Transmit Slot */
544 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
545 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
546
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200547#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
wdenkba56f622004-02-06 23:19:44 +0000548 /* set RMII mode */
549 /* NOTE: 440GX spec states that mode is mutually exclusive */
550 /* NOTE: Therefore, disable all other EMACS, since we handle */
551 /* NOTE: only one emac at a time */
552 reg = 0;
Stefan Roese2d834762007-10-23 14:03:17 +0200553 out_be32((void *)ZMII_FER, 0);
wdenkba56f622004-02-06 23:19:44 +0000554 udelay (100);
wdenkba56f622004-02-06 23:19:44 +0000555
Stefan Roese846b0dd2005-08-08 12:42:22 +0200556#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
Stefan Roese2d834762007-10-23 14:03:17 +0200557 out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
Stefan Roese887e2ec2006-09-07 11:51:23 +0200558#elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200559 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
Stefan Roese4a3cd9e2005-09-07 16:21:12 +0200560#elif defined(CONFIG_440GP)
561 /* set RMII mode */
Stefan Roese2d834762007-10-23 14:03:17 +0200562 out_be32((void *)ZMII_FER, ZMII_RMII | ZMII_MDI0);
wdenk0e6d7982004-03-14 00:07:33 +0000563#else
564 if ((devnum == 0) || (devnum == 1)) {
Stefan Roese2d834762007-10-23 14:03:17 +0200565 out_be32((void *)ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
Stefan Roese1c2ce222006-11-27 14:12:17 +0100566 } else { /* ((devnum == 2) || (devnum == 3)) */
Stefan Roese2d834762007-10-23 14:03:17 +0200567 out_be32((void *)ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
568 out_be32((void *)RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
569 (RGMII_FER_RGMII << RGMII_FER_V (3))));
wdenk0e6d7982004-03-14 00:07:33 +0000570 }
571#endif
Stefan Roesec57c7982005-08-11 17:56:56 +0200572
Stefan Roese2d834762007-10-23 14:03:17 +0200573 out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100574#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
Stefan Roesedbbd1252007-10-05 17:10:59 +0200575#if defined(CONFIG_405EX)
576 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
577#endif
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200578
wdenk0e6d7982004-03-14 00:07:33 +0000579 __asm__ volatile ("eieio");
580
581 /* reset emac so we have access to the phy */
Stefan Roesedbbd1252007-10-05 17:10:59 +0200582#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
583 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
584 defined(CONFIG_405EX)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200585 /* provide clocks for EMAC internal loopback */
586 mfsdr (sdr_mfr, mfr);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200587 mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200588 mtsdr(sdr_mfr, mfr);
589#endif
wdenk0e6d7982004-03-14 00:07:33 +0000590
Stefan Roese2d834762007-10-23 14:03:17 +0200591 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
wdenkba56f622004-02-06 23:19:44 +0000592
593 failsafe = 1000;
Stefan Roese2d834762007-10-23 14:03:17 +0200594 while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
wdenkba56f622004-02-06 23:19:44 +0000595 udelay (1000);
596 failsafe--;
597 }
Stefan Roese887e2ec2006-09-07 11:51:23 +0200598 if (failsafe <= 0)
599 printf("\nProblem resetting EMAC!\n");
wdenkba56f622004-02-06 23:19:44 +0000600
Stefan Roesedbbd1252007-10-05 17:10:59 +0200601#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
602 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
603 defined(CONFIG_405EX)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200604 /* remove clocks for EMAC internal loopback */
605 mfsdr (sdr_mfr, mfr);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200606 mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200607 mtsdr(sdr_mfr, mfr);
608#endif
609
Stefan Roese887e2ec2006-09-07 11:51:23 +0200610#if defined(CONFIG_440GX) || \
611 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200612 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
613 defined(CONFIG_405EX)
wdenkba56f622004-02-06 23:19:44 +0000614 /* Whack the M1 register */
615 mode_reg = 0x0;
616 mode_reg &= ~0x00000038;
617 if (sysinfo.freqOPB <= 50000000);
618 else if (sysinfo.freqOPB <= 66666667)
619 mode_reg |= EMAC_M1_OBCI_66;
620 else if (sysinfo.freqOPB <= 83333333)
621 mode_reg |= EMAC_M1_OBCI_83;
622 else if (sysinfo.freqOPB <= 100000000)
623 mode_reg |= EMAC_M1_OBCI_100;
624 else
625 mode_reg |= EMAC_M1_OBCI_GT100;
626
Stefan Roese2d834762007-10-23 14:03:17 +0200627 out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100628#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
wdenkba56f622004-02-06 23:19:44 +0000629
630 /* wait for PHY to complete auto negotiation */
631 reg_short = 0;
632#ifndef CONFIG_CS8952_PHY
633 switch (devnum) {
634 case 0:
635 reg = CONFIG_PHY_ADDR;
636 break;
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200637#if defined (CONFIG_PHY1_ADDR)
wdenkba56f622004-02-06 23:19:44 +0000638 case 1:
639 reg = CONFIG_PHY1_ADDR;
640 break;
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200641#endif
Stefan Roese846b0dd2005-08-08 12:42:22 +0200642#if defined (CONFIG_440GX)
wdenkba56f622004-02-06 23:19:44 +0000643 case 2:
644 reg = CONFIG_PHY2_ADDR;
645 break;
646 case 3:
647 reg = CONFIG_PHY3_ADDR;
648 break;
649#endif
650 default:
651 reg = CONFIG_PHY_ADDR;
652 break;
653 }
654
wdenk3c74e322004-02-22 23:46:08 +0000655 bis->bi_phynum[devnum] = reg;
656
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200657#if defined(CONFIG_PHY_RESET)
wdenka06752e2004-09-29 22:43:59 +0000658 /*
659 * Reset the phy, only if its the first time through
660 * otherwise, just check the speeds & feeds
661 */
662 if (hw_p->first_init == 0) {
Stefan Roeseec0c2ec2006-11-27 14:46:06 +0100663#if defined(CONFIG_M88E1111_PHY)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200664 miiphy_write (dev->name, reg, 0x14, 0x0ce3);
665 miiphy_write (dev->name, reg, 0x18, 0x4101);
666 miiphy_write (dev->name, reg, 0x09, 0x0e00);
667 miiphy_write (dev->name, reg, 0x04, 0x01e1);
668#endif
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200669 miiphy_reset (dev->name, reg);
wdenkba56f622004-02-06 23:19:44 +0000670
Stefan Roese887e2ec2006-09-07 11:51:23 +0200671#if defined(CONFIG_440GX) || \
672 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200673 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
674 defined(CONFIG_405EX)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200675
wdenk0e6d7982004-03-14 00:07:33 +0000676#if defined(CONFIG_CIS8201_PHY)
wdenkfc1cfcd2004-04-25 15:41:35 +0000677 /*
Stefan Roese17f50f222005-08-04 17:09:16 +0200678 * Cicada 8201 PHY needs to have an extended register whacked
679 * for RGMII mode.
wdenkfc1cfcd2004-04-25 15:41:35 +0000680 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200681 if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
Stefan Roeseb79316f2005-08-15 12:31:23 +0200682#if defined(CONFIG_CIS8201_SHORT_ETCH)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200683 miiphy_write (dev->name, reg, 23, 0x1300);
Stefan Roeseb79316f2005-08-15 12:31:23 +0200684#else
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200685 miiphy_write (dev->name, reg, 23, 0x1000);
Stefan Roeseb79316f2005-08-15 12:31:23 +0200686#endif
Stefan Roese17f50f222005-08-04 17:09:16 +0200687 /*
688 * Vitesse VSC8201/Cicada CIS8201 errata:
689 * Interoperability problem with Intel 82547EI phys
690 * This work around (provided by Vitesse) changes
691 * the default timer convergence from 8ms to 12ms
692 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200693 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
694 miiphy_write (dev->name, reg, 0x08, 0x0200);
695 miiphy_write (dev->name, reg, 0x1f, 0x52b5);
696 miiphy_write (dev->name, reg, 0x02, 0x0004);
697 miiphy_write (dev->name, reg, 0x01, 0x0671);
698 miiphy_write (dev->name, reg, 0x00, 0x8fae);
699 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
700 miiphy_write (dev->name, reg, 0x08, 0x0000);
701 miiphy_write (dev->name, reg, 0x1f, 0x0000);
Stefan Roese17f50f222005-08-04 17:09:16 +0200702 /* end Vitesse/Cicada errata */
703 }
wdenk0e6d7982004-03-14 00:07:33 +0000704#endif
Stefan Roese5fb692c2007-01-18 10:25:34 +0100705
706#if defined(CONFIG_ET1011C_PHY)
707 /*
708 * Agere ET1011c PHY needs to have an extended register whacked
709 * for RGMII mode.
710 */
711 if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
712 miiphy_read (dev->name, reg, 0x16, &reg_short);
713 reg_short &= ~(0x7);
714 reg_short |= 0x6; /* RGMII DLL Delay*/
715 miiphy_write (dev->name, reg, 0x16, reg_short);
716
717 miiphy_read (dev->name, reg, 0x17, &reg_short);
718 reg_short &= ~(0x40);
719 miiphy_write (dev->name, reg, 0x17, reg_short);
720
721 miiphy_write(dev->name, reg, 0x1c, 0x74f0);
722 }
723#endif
724
wdenk855a4962004-03-14 18:23:55 +0000725#endif
wdenka06752e2004-09-29 22:43:59 +0000726 /* Start/Restart autonegotiation */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200727 phy_setup_aneg (dev->name, reg);
wdenka06752e2004-09-29 22:43:59 +0000728 udelay (1000);
729 }
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200730#endif /* defined(CONFIG_PHY_RESET) */
wdenkba56f622004-02-06 23:19:44 +0000731
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200732 miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
wdenkba56f622004-02-06 23:19:44 +0000733
734 /*
wdenk0e6d7982004-03-14 00:07:33 +0000735 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
wdenkba56f622004-02-06 23:19:44 +0000736 */
737 if ((reg_short & PHY_BMSR_AUTN_ABLE)
738 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
739 puts ("Waiting for PHY auto negotiation to complete");
740 i = 0;
741 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
742 /*
743 * Timeout reached ?
744 */
745 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
746 puts (" TIMEOUT !\n");
747 break;
748 }
749
750 if ((i++ % 1000) == 0) {
751 putc ('.');
752 }
753 udelay (1000); /* 1 ms */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200754 miiphy_read (dev->name, reg, PHY_BMSR, &reg_short);
wdenkba56f622004-02-06 23:19:44 +0000755
756 }
757 puts (" done\n");
758 udelay (500000); /* another 500 ms (results in faster booting) */
759 }
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200760#endif /* #ifndef CONFIG_CS8952_PHY */
761
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200762 speed = miiphy_speed (dev->name, reg);
763 duplex = miiphy_duplex (dev->name, reg);
wdenkba56f622004-02-06 23:19:44 +0000764
765 if (hw_p->print_speed) {
766 hw_p->print_speed = 0;
Stefan Roese5fb692c2007-01-18 10:25:34 +0100767 printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
768 (int) speed, (duplex == HALF) ? "HALF" : "FULL",
769 hw_p->devnum);
wdenkba56f622004-02-06 23:19:44 +0000770 }
771
Stefan Roese887e2ec2006-09-07 11:51:23 +0200772#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
773 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
Stefan Roese846b0dd2005-08-08 12:42:22 +0200774#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200775 mfsdr(sdr_mfr, reg);
776 if (speed == 100) {
777 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
778 } else {
779 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
780 }
781 mtsdr(sdr_mfr, reg);
782#endif
Stefan Roesec57c7982005-08-11 17:56:56 +0200783
wdenkba56f622004-02-06 23:19:44 +0000784 /* Set ZMII/RGMII speed according to the phy link speed */
Stefan Roeseff768cb2007-10-31 18:01:24 +0100785 reg = in_be32((void *)ZMII_SSR);
wdenk855a4962004-03-14 18:23:55 +0000786 if ( (speed == 100) || (speed == 1000) )
Stefan Roeseff768cb2007-10-31 18:01:24 +0100787 out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
wdenkba56f622004-02-06 23:19:44 +0000788 else
Stefan Roeseff768cb2007-10-31 18:01:24 +0100789 out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
wdenkba56f622004-02-06 23:19:44 +0000790
791 if ((devnum == 2) || (devnum == 3)) {
792 if (speed == 1000)
793 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
794 else if (speed == 100)
795 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
Stefan Roese887e2ec2006-09-07 11:51:23 +0200796 else if (speed == 10)
wdenkba56f622004-02-06 23:19:44 +0000797 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
Stefan Roese887e2ec2006-09-07 11:51:23 +0200798 else {
799 printf("Error in RGMII Speed\n");
800 return -1;
801 }
Stefan Roeseff768cb2007-10-31 18:01:24 +0100802 out_be32((void *)RGMII_SSR, reg);
wdenkba56f622004-02-06 23:19:44 +0000803 }
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100804#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
wdenkba56f622004-02-06 23:19:44 +0000805
Stefan Roesedbbd1252007-10-05 17:10:59 +0200806#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
807 defined(CONFIG_405EX)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200808 if (speed == 1000)
809 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
810 else if (speed == 100)
811 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
812 else if (speed == 10)
813 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
814 else {
815 printf("Error in RGMII Speed\n");
816 return -1;
817 }
Stefan Roese2d834762007-10-23 14:03:17 +0200818 out_be32((void *)RGMII_SSR, reg);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200819#endif
820
wdenkba56f622004-02-06 23:19:44 +0000821 /* set the Mal configuration reg */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200822#if defined(CONFIG_440GX) || \
823 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200824 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
825 defined(CONFIG_405EX)
Stefan Roese17f50f222005-08-04 17:09:16 +0200826 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
827 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
828#else
829 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
wdenkba56f622004-02-06 23:19:44 +0000830 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
Stefan Roese17f50f222005-08-04 17:09:16 +0200831 if (get_pvr() == PVR_440GP_RB) {
832 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
833 }
834#endif
wdenkba56f622004-02-06 23:19:44 +0000835
wdenkba56f622004-02-06 23:19:44 +0000836 /*
837 * Malloc MAL buffer desciptors, make sure they are
838 * aligned on cache line boundary size
839 * (401/403/IOP480 = 16, 405 = 32)
840 * and doesn't cross cache block boundaries.
841 */
Stefan Roeseff768cb2007-10-31 18:01:24 +0100842 if (hw_p->first_init == 0) {
843 debug("*** Allocating descriptor memory ***\n");
wdenkba56f622004-02-06 23:19:44 +0000844
Stefan Roeseff768cb2007-10-31 18:01:24 +0100845 bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
846 if (!bd_cached) {
847 printf("%s: Error allocating MAL descriptor buffers!\n");
848 return -1;
849 }
Stefan Roeseb79316f2005-08-15 12:31:23 +0200850
Stefan Roeseff768cb2007-10-31 18:01:24 +0100851#ifdef CONFIG_4xx_DCACHE
Matthias Fuchsfbde2162007-11-09 15:36:44 +0100852 flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE - 1);
Stefan Roeseff768cb2007-10-31 18:01:24 +0100853 bd_uncached = bis->bi_memsize;
854 program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
855 TLB_WORD2_I_ENABLE);
856#else
857 bd_uncached = bd_cached;
858#endif
859 hw_p->tx_phys = bd_cached;
860 hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
861 hw_p->tx = (mal_desc_t *)(bd_uncached);
862 hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
863 debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx);
wdenkba56f622004-02-06 23:19:44 +0000864 }
865
866 for (i = 0; i < NUM_TX_BUFF; i++) {
867 hw_p->tx[i].ctrl = 0;
868 hw_p->tx[i].data_len = 0;
Stefan Roeseff768cb2007-10-31 18:01:24 +0100869 if (hw_p->first_init == 0)
870 hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
871 L1_CACHE_BYTES);
wdenkba56f622004-02-06 23:19:44 +0000872 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
873 if ((NUM_TX_BUFF - 1) == i)
874 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
875 hw_p->tx_run[i] = -1;
Stefan Roeseff768cb2007-10-31 18:01:24 +0100876 debug("TX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->tx[i].data_ptr);
wdenkba56f622004-02-06 23:19:44 +0000877 }
878
879 for (i = 0; i < NUM_RX_BUFF; i++) {
880 hw_p->rx[i].ctrl = 0;
881 hw_p->rx[i].data_len = 0;
Stefan Roeseff768cb2007-10-31 18:01:24 +0100882 hw_p->rx[i].data_ptr = (char *)NetRxPackets[i];
wdenkba56f622004-02-06 23:19:44 +0000883 if ((NUM_RX_BUFF - 1) == i)
884 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
885 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
886 hw_p->rx_ready[i] = -1;
Stefan Roeseff768cb2007-10-31 18:01:24 +0100887 debug("RX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->rx[i].data_ptr);
wdenkba56f622004-02-06 23:19:44 +0000888 }
889
890 reg = 0x00000000;
891
892 reg |= dev->enetaddr[0]; /* set high address */
893 reg = reg << 8;
894 reg |= dev->enetaddr[1];
895
Stefan Roese2d834762007-10-23 14:03:17 +0200896 out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg);
wdenkba56f622004-02-06 23:19:44 +0000897
898 reg = 0x00000000;
899 reg |= dev->enetaddr[2]; /* set low address */
900 reg = reg << 8;
901 reg |= dev->enetaddr[3];
902 reg = reg << 8;
903 reg |= dev->enetaddr[4];
904 reg = reg << 8;
905 reg |= dev->enetaddr[5];
906
Stefan Roese2d834762007-10-23 14:03:17 +0200907 out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg);
wdenkba56f622004-02-06 23:19:44 +0000908
909 switch (devnum) {
910 case 1:
911 /* setup MAL tx & rx channel pointers */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200912#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
Stefan Roeseff768cb2007-10-31 18:01:24 +0100913 mtdcr (maltxctp2r, hw_p->tx_phys);
Stefan Roesec157d8e2005-08-01 16:41:48 +0200914#else
Stefan Roeseff768cb2007-10-31 18:01:24 +0100915 mtdcr (maltxctp1r, hw_p->tx_phys);
Stefan Roesec157d8e2005-08-01 16:41:48 +0200916#endif
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200917#if defined(CONFIG_440)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200918 mtdcr (maltxbattr, 0x0);
wdenkba56f622004-02-06 23:19:44 +0000919 mtdcr (malrxbattr, 0x0);
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200920#endif
Stefan Roeseff768cb2007-10-31 18:01:24 +0100921 mtdcr (malrxctp1r, hw_p->rx_phys);
wdenkba56f622004-02-06 23:19:44 +0000922 /* set RX buffer size */
923 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
924 break;
Stefan Roese846b0dd2005-08-08 12:42:22 +0200925#if defined (CONFIG_440GX)
wdenkba56f622004-02-06 23:19:44 +0000926 case 2:
927 /* setup MAL tx & rx channel pointers */
928 mtdcr (maltxbattr, 0x0);
wdenkba56f622004-02-06 23:19:44 +0000929 mtdcr (malrxbattr, 0x0);
Stefan Roeseff768cb2007-10-31 18:01:24 +0100930 mtdcr (maltxctp2r, hw_p->tx_phys);
931 mtdcr (malrxctp2r, hw_p->rx_phys);
wdenkba56f622004-02-06 23:19:44 +0000932 /* set RX buffer size */
933 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
934 break;
935 case 3:
936 /* setup MAL tx & rx channel pointers */
937 mtdcr (maltxbattr, 0x0);
Stefan Roeseff768cb2007-10-31 18:01:24 +0100938 mtdcr (maltxctp3r, hw_p->tx_phys);
wdenkba56f622004-02-06 23:19:44 +0000939 mtdcr (malrxbattr, 0x0);
Stefan Roeseff768cb2007-10-31 18:01:24 +0100940 mtdcr (malrxctp3r, hw_p->rx_phys);
wdenkba56f622004-02-06 23:19:44 +0000941 /* set RX buffer size */
942 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
943 break;
Stefan Roesec57c7982005-08-11 17:56:56 +0200944#endif /* CONFIG_440GX */
wdenkba56f622004-02-06 23:19:44 +0000945 case 0:
946 default:
947 /* setup MAL tx & rx channel pointers */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200948#if defined(CONFIG_440)
wdenkba56f622004-02-06 23:19:44 +0000949 mtdcr (maltxbattr, 0x0);
wdenkba56f622004-02-06 23:19:44 +0000950 mtdcr (malrxbattr, 0x0);
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200951#endif
Stefan Roeseff768cb2007-10-31 18:01:24 +0100952 mtdcr (maltxctp0r, hw_p->tx_phys);
953 mtdcr (malrxctp0r, hw_p->rx_phys);
wdenkba56f622004-02-06 23:19:44 +0000954 /* set RX buffer size */
955 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
956 break;
957 }
958
959 /* Enable MAL transmit and receive channels */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200960#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200961 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
962#else
wdenkba56f622004-02-06 23:19:44 +0000963 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
Stefan Roesec157d8e2005-08-01 16:41:48 +0200964#endif
wdenkba56f622004-02-06 23:19:44 +0000965 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
966
967 /* set transmit enable & receive enable */
Stefan Roese2d834762007-10-23 14:03:17 +0200968 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
wdenkba56f622004-02-06 23:19:44 +0000969
970 /* set receive fifo to 4k and tx fifo to 2k */
Stefan Roese2d834762007-10-23 14:03:17 +0200971 mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
wdenkba56f622004-02-06 23:19:44 +0000972 mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
973
974 /* set speed */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100975 if (speed == _1000BASET) {
Stefan Roese738815c2007-10-02 11:44:46 +0200976#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
977 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100978 unsigned long pfc1;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200979
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100980 mfsdr (sdr_pfc1, pfc1);
981 pfc1 |= SDR0_PFC1_EM_1000;
982 mtsdr (sdr_pfc1, pfc1);
983#endif
wdenk855a4962004-03-14 18:23:55 +0000984 mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100985 } else if (speed == _100BASET)
wdenkba56f622004-02-06 23:19:44 +0000986 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
987 else
988 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
989 if (duplex == FULL)
990 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
991
Stefan Roese2d834762007-10-23 14:03:17 +0200992 out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
wdenkba56f622004-02-06 23:19:44 +0000993
994 /* Enable broadcast and indvidual address */
995 /* TBS: enabling runts as some misbehaved nics will send runts */
Stefan Roese2d834762007-10-23 14:03:17 +0200996 out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
wdenkba56f622004-02-06 23:19:44 +0000997
998 /* we probably need to set the tx mode1 reg? maybe at tx time */
999
1000 /* set transmit request threshold register */
Stefan Roese2d834762007-10-23 14:03:17 +02001001 out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
wdenkba56f622004-02-06 23:19:44 +00001002
Wolfgang Denk265817c2005-09-25 00:53:22 +02001003 /* set receive low/high water mark register */
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001004#if defined(CONFIG_440)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001005 /* 440s has a 64 byte burst length */
Stefan Roese2d834762007-10-23 14:03:17 +02001006 out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001007#else
1008 /* 405s have a 16 byte burst length */
Stefan Roese2d834762007-10-23 14:03:17 +02001009 out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001010#endif /* defined(CONFIG_440) */
Stefan Roese2d834762007-10-23 14:03:17 +02001011 out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
wdenkba56f622004-02-06 23:19:44 +00001012
1013 /* Set fifo limit entry in tx mode 0 */
Stefan Roese2d834762007-10-23 14:03:17 +02001014 out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
wdenkba56f622004-02-06 23:19:44 +00001015 /* Frame gap set */
Stefan Roese2d834762007-10-23 14:03:17 +02001016 out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
wdenkba56f622004-02-06 23:19:44 +00001017
1018 /* Set EMAC IER */
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001019 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
wdenkba56f622004-02-06 23:19:44 +00001020 if (speed == _100BASET)
1021 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
1022
Stefan Roese2d834762007-10-23 14:03:17 +02001023 out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
1024 out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
wdenkba56f622004-02-06 23:19:44 +00001025
1026 if (hw_p->first_init == 0) {
1027 /*
1028 * Connect interrupt service routines
1029 */
Stefan Roesedbbd1252007-10-05 17:10:59 +02001030 irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
1031 (interrupt_handler_t *) enetInt, dev);
wdenkba56f622004-02-06 23:19:44 +00001032 }
wdenkba56f622004-02-06 23:19:44 +00001033
1034 mtmsr (msr); /* enable interrupts again */
1035
1036 hw_p->bis = bis;
1037 hw_p->first_init = 1;
1038
1039 return (1);
1040}
1041
1042
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001043static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
wdenkba56f622004-02-06 23:19:44 +00001044 int len)
1045{
1046 struct enet_frame *ef_ptr;
1047 ulong time_start, time_now;
1048 unsigned long temp_txm0;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001049 EMAC_4XX_HW_PST hw_p = dev->priv;
wdenkba56f622004-02-06 23:19:44 +00001050
1051 ef_ptr = (struct enet_frame *) ptr;
1052
1053 /*-----------------------------------------------------------------------+
1054 * Copy in our address into the frame.
1055 *-----------------------------------------------------------------------*/
1056 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
1057
1058 /*-----------------------------------------------------------------------+
1059 * If frame is too long or too short, modify length.
1060 *-----------------------------------------------------------------------*/
1061 /* TBS: where does the fragment go???? */
1062 if (len > ENET_MAX_MTU)
1063 len = ENET_MAX_MTU;
1064
1065 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
1066 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
Matthias Fuchsfbde2162007-11-09 15:36:44 +01001067 flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len - 1);
wdenkba56f622004-02-06 23:19:44 +00001068
1069 /*-----------------------------------------------------------------------+
1070 * set TX Buffer busy, and send it
1071 *-----------------------------------------------------------------------*/
1072 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
1073 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
1074 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
1075 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
1076 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
1077
1078 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
1079 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
1080
1081 __asm__ volatile ("eieio");
1082
Stefan Roese2d834762007-10-23 14:03:17 +02001083 out_be32((void *)EMAC_TXM0 + hw_p->hw_addr,
1084 in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001085#ifdef INFO_4XX_ENET
wdenkba56f622004-02-06 23:19:44 +00001086 hw_p->stats.pkts_tx++;
1087#endif
1088
1089 /*-----------------------------------------------------------------------+
1090 * poll unitl the packet is sent and then make sure it is OK
1091 *-----------------------------------------------------------------------*/
1092 time_start = get_timer (0);
1093 while (1) {
Stefan Roese2d834762007-10-23 14:03:17 +02001094 temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr);
wdenkba56f622004-02-06 23:19:44 +00001095 /* loop until either TINT turns on or 3 seconds elapse */
1096 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
1097 /* transmit is done, so now check for errors
1098 * If there is an error, an interrupt should
1099 * happen when we return
1100 */
1101 time_now = get_timer (0);
1102 if ((time_now - time_start) > 3000) {
1103 return (-1);
1104 }
1105 } else {
1106 return (len);
1107 }
1108 }
1109}
1110
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001111
Stefan Roesedbbd1252007-10-05 17:10:59 +02001112#if defined (CONFIG_440) || defined(CONFIG_405EX)
wdenkba56f622004-02-06 23:19:44 +00001113
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001114#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001115/*
1116 * Hack: On 440SP all enet irq sources are located on UIC1
1117 * Needs some cleanup. --sr
1118 */
1119#define UIC0MSR uic1msr
1120#define UIC0SR uic1sr
1121#else
1122#define UIC0MSR uic0msr
1123#define UIC0SR uic0sr
1124#endif
1125
Stefan Roesedbbd1252007-10-05 17:10:59 +02001126#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1127 defined(CONFIG_405EX)
Stefan Roese887e2ec2006-09-07 11:51:23 +02001128#define UICMSR_ETHX uic0msr
1129#define UICSR_ETHX uic0sr
1130#else
1131#define UICMSR_ETHX uic1msr
1132#define UICSR_ETHX uic1sr
1133#endif
1134
wdenkba56f622004-02-06 23:19:44 +00001135int enetInt (struct eth_device *dev)
1136{
1137 int serviced;
1138 int rc = -1; /* default to not us */
1139 unsigned long mal_isr;
1140 unsigned long emac_isr = 0;
1141 unsigned long mal_rx_eob;
1142 unsigned long my_uic0msr, my_uic1msr;
Stefan Roese887e2ec2006-09-07 11:51:23 +02001143 unsigned long my_uicmsr_ethx;
wdenkba56f622004-02-06 23:19:44 +00001144
Stefan Roese846b0dd2005-08-08 12:42:22 +02001145#if defined(CONFIG_440GX)
wdenkba56f622004-02-06 23:19:44 +00001146 unsigned long my_uic2msr;
1147#endif
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001148 EMAC_4XX_HW_PST hw_p;
wdenkba56f622004-02-06 23:19:44 +00001149
1150 /*
1151 * Because the mal is generic, we need to get the current
1152 * eth device
1153 */
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001154#if defined(CONFIG_NET_MULTI)
1155 dev = eth_get_dev();
1156#else
1157 dev = emac0_dev;
1158#endif
wdenkba56f622004-02-06 23:19:44 +00001159
1160 hw_p = dev->priv;
1161
wdenkba56f622004-02-06 23:19:44 +00001162 /* enter loop that stays in interrupt code until nothing to service */
1163 do {
1164 serviced = 0;
1165
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001166 my_uic0msr = mfdcr (UIC0MSR);
wdenkba56f622004-02-06 23:19:44 +00001167 my_uic1msr = mfdcr (uic1msr);
Stefan Roese846b0dd2005-08-08 12:42:22 +02001168#if defined(CONFIG_440GX)
wdenkba56f622004-02-06 23:19:44 +00001169 my_uic2msr = mfdcr (uic2msr);
1170#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +02001171 my_uicmsr_ethx = mfdcr (UICMSR_ETHX);
1172
wdenkba56f622004-02-06 23:19:44 +00001173 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
Stefan Roese887e2ec2006-09-07 11:51:23 +02001174 && !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))
1175 && !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) {
wdenkba56f622004-02-06 23:19:44 +00001176 /* not for us */
1177 return (rc);
1178 }
Stefan Roese846b0dd2005-08-08 12:42:22 +02001179#if defined (CONFIG_440GX)
wdenkba56f622004-02-06 23:19:44 +00001180 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
1181 && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
1182 /* not for us */
1183 return (rc);
1184 }
1185#endif
1186 /* get and clear controller status interrupts */
1187 /* look at Mal and EMAC interrupts */
1188 if ((my_uic0msr & (UIC_MRE | UIC_MTE))
1189 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1190 /* we have a MAL interrupt */
1191 mal_isr = mfdcr (malesr);
1192 /* look for mal error */
1193 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
Stefan Roese887e2ec2006-09-07 11:51:23 +02001194 mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR);
wdenkba56f622004-02-06 23:19:44 +00001195 serviced = 1;
1196 rc = 0;
1197 }
1198 }
1199
1200 /* port by port dispatch of emac interrupts */
1201 if (hw_p->devnum == 0) {
Stefan Roese887e2ec2006-09-07 11:51:23 +02001202 if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */
Stefan Roese2d834762007-10-23 14:03:17 +02001203 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
wdenkba56f622004-02-06 23:19:44 +00001204 if ((hw_p->emac_ier & emac_isr) != 0) {
1205 emac_err (dev, emac_isr);
1206 serviced = 1;
1207 rc = 0;
1208 }
1209 }
1210 if ((hw_p->emac_ier & emac_isr)
1211 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001212 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
Stefan Roese887e2ec2006-09-07 11:51:23 +02001213 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1214 mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */
wdenkba56f622004-02-06 23:19:44 +00001215 return (rc); /* we had errors so get out */
1216 }
1217 }
1218
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001219#if !defined(CONFIG_440SP)
wdenkba56f622004-02-06 23:19:44 +00001220 if (hw_p->devnum == 1) {
Stefan Roese887e2ec2006-09-07 11:51:23 +02001221 if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */
Stefan Roese2d834762007-10-23 14:03:17 +02001222 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
wdenkba56f622004-02-06 23:19:44 +00001223 if ((hw_p->emac_ier & emac_isr) != 0) {
1224 emac_err (dev, emac_isr);
1225 serviced = 1;
1226 rc = 0;
1227 }
1228 }
1229 if ((hw_p->emac_ier & emac_isr)
1230 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001231 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
Stefan Roese887e2ec2006-09-07 11:51:23 +02001232 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1233 mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */
wdenkba56f622004-02-06 23:19:44 +00001234 return (rc); /* we had errors so get out */
1235 }
1236 }
Stefan Roese846b0dd2005-08-08 12:42:22 +02001237#if defined (CONFIG_440GX)
wdenkba56f622004-02-06 23:19:44 +00001238 if (hw_p->devnum == 2) {
1239 if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
Stefan Roese2d834762007-10-23 14:03:17 +02001240 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
wdenkba56f622004-02-06 23:19:44 +00001241 if ((hw_p->emac_ier & emac_isr) != 0) {
1242 emac_err (dev, emac_isr);
1243 serviced = 1;
1244 rc = 0;
1245 }
1246 }
1247 if ((hw_p->emac_ier & emac_isr)
1248 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001249 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
wdenkba56f622004-02-06 23:19:44 +00001250 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1251 mtdcr (uic2sr, UIC_ETH2);
1252 return (rc); /* we had errors so get out */
1253 }
1254 }
1255
1256 if (hw_p->devnum == 3) {
1257 if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
Stefan Roese2d834762007-10-23 14:03:17 +02001258 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
wdenkba56f622004-02-06 23:19:44 +00001259 if ((hw_p->emac_ier & emac_isr) != 0) {
1260 emac_err (dev, emac_isr);
1261 serviced = 1;
1262 rc = 0;
1263 }
1264 }
1265 if ((hw_p->emac_ier & emac_isr)
1266 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001267 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
wdenkba56f622004-02-06 23:19:44 +00001268 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1269 mtdcr (uic2sr, UIC_ETH3);
1270 return (rc); /* we had errors so get out */
1271 }
1272 }
Stefan Roese846b0dd2005-08-08 12:42:22 +02001273#endif /* CONFIG_440GX */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001274#endif /* !CONFIG_440SP */
1275
wdenkba56f622004-02-06 23:19:44 +00001276 /* handle MAX TX EOB interrupt from a tx */
1277 if (my_uic0msr & UIC_MTE) {
1278 mal_rx_eob = mfdcr (maltxeobisr);
1279 mtdcr (maltxeobisr, mal_rx_eob);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001280 mtdcr (UIC0SR, UIC_MTE);
wdenkba56f622004-02-06 23:19:44 +00001281 }
1282 /* handle MAL RX EOB interupt from a receive */
wdenkfc1cfcd2004-04-25 15:41:35 +00001283 /* check for EOB on valid channels */
wdenkba56f622004-02-06 23:19:44 +00001284 if (my_uic0msr & UIC_MRE) {
1285 mal_rx_eob = mfdcr (malrxeobisr);
Wolfgang Denk265817c2005-09-25 00:53:22 +02001286 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
wdenkba56f622004-02-06 23:19:44 +00001287 /* clear EOB
1288 mtdcr(malrxeobisr, mal_rx_eob); */
1289 enet_rcv (dev, emac_isr);
1290 /* indicate that we serviced an interrupt */
1291 serviced = 1;
1292 rc = 0;
1293 }
1294 }
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001295
1296 mtdcr (UIC0SR, UIC_MRE); /* Clear */
wdenkba56f622004-02-06 23:19:44 +00001297 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1298 switch (hw_p->devnum) {
1299 case 0:
Stefan Roese887e2ec2006-09-07 11:51:23 +02001300 mtdcr (UICSR_ETHX, UIC_ETH0);
wdenkba56f622004-02-06 23:19:44 +00001301 break;
1302 case 1:
Stefan Roese887e2ec2006-09-07 11:51:23 +02001303 mtdcr (UICSR_ETHX, UIC_ETH1);
wdenkba56f622004-02-06 23:19:44 +00001304 break;
Stefan Roese846b0dd2005-08-08 12:42:22 +02001305#if defined (CONFIG_440GX)
wdenkba56f622004-02-06 23:19:44 +00001306 case 2:
1307 mtdcr (uic2sr, UIC_ETH2);
1308 break;
1309 case 3:
1310 mtdcr (uic2sr, UIC_ETH3);
1311 break;
Stefan Roese846b0dd2005-08-08 12:42:22 +02001312#endif /* CONFIG_440GX */
wdenkba56f622004-02-06 23:19:44 +00001313 default:
1314 break;
1315 }
1316 } while (serviced);
1317
1318 return (rc);
1319}
1320
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001321#else /* CONFIG_440 */
1322
1323int enetInt (struct eth_device *dev)
1324{
1325 int serviced;
1326 int rc = -1; /* default to not us */
1327 unsigned long mal_isr;
1328 unsigned long emac_isr = 0;
1329 unsigned long mal_rx_eob;
1330 unsigned long my_uicmsr;
1331
1332 EMAC_4XX_HW_PST hw_p;
1333
1334 /*
1335 * Because the mal is generic, we need to get the current
1336 * eth device
1337 */
1338#if defined(CONFIG_NET_MULTI)
1339 dev = eth_get_dev();
1340#else
1341 dev = emac0_dev;
1342#endif
1343
1344 hw_p = dev->priv;
1345
1346 /* enter loop that stays in interrupt code until nothing to service */
1347 do {
1348 serviced = 0;
1349
1350 my_uicmsr = mfdcr (uicmsr);
1351
1352 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
1353 return (rc);
1354 }
1355 /* get and clear controller status interrupts */
1356 /* look at Mal and EMAC interrupts */
1357 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
1358 mal_isr = mfdcr (malesr);
1359 /* look for mal error */
1360 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
1361 mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
1362 serviced = 1;
1363 rc = 0;
1364 }
1365 }
1366
1367 /* port by port dispatch of emac interrupts */
1368
1369 if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
Stefan Roese2d834762007-10-23 14:03:17 +02001370 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001371 if ((hw_p->emac_ier & emac_isr) != 0) {
1372 emac_err (dev, emac_isr);
1373 serviced = 1;
1374 rc = 0;
1375 }
1376 }
1377 if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
1378 mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
1379 return (rc); /* we had errors so get out */
1380 }
1381
1382 /* handle MAX TX EOB interrupt from a tx */
1383 if (my_uicmsr & UIC_MAL_TXEOB) {
1384 mal_rx_eob = mfdcr (maltxeobisr);
1385 mtdcr (maltxeobisr, mal_rx_eob);
1386 mtdcr (uicsr, UIC_MAL_TXEOB);
1387 }
1388 /* handle MAL RX EOB interupt from a receive */
1389 /* check for EOB on valid channels */
1390 if (my_uicmsr & UIC_MAL_RXEOB)
1391 {
1392 mal_rx_eob = mfdcr (malrxeobisr);
Wolfgang Denk265817c2005-09-25 00:53:22 +02001393 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001394 /* clear EOB
1395 mtdcr(malrxeobisr, mal_rx_eob); */
1396 enet_rcv (dev, emac_isr);
1397 /* indicate that we serviced an interrupt */
1398 serviced = 1;
1399 rc = 0;
1400 }
1401 }
1402 mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
Stefan Roesee01bd212007-03-21 13:38:59 +01001403#if defined(CONFIG_405EZ)
1404 mtsdr (sdricintstat, SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
1405#endif /* defined(CONFIG_405EZ) */
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001406 }
1407 while (serviced);
1408
1409 return (rc);
1410}
1411
1412#endif /* CONFIG_440 */
1413
wdenkba56f622004-02-06 23:19:44 +00001414/*-----------------------------------------------------------------------------+
1415 * MAL Error Routine
1416 *-----------------------------------------------------------------------------*/
1417static void mal_err (struct eth_device *dev, unsigned long isr,
1418 unsigned long uic, unsigned long maldef,
1419 unsigned long mal_errr)
1420{
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001421 EMAC_4XX_HW_PST hw_p = dev->priv;
wdenkba56f622004-02-06 23:19:44 +00001422
1423 mtdcr (malesr, isr); /* clear interrupt */
1424
1425 /* clear DE interrupt */
1426 mtdcr (maltxdeir, 0xC0000000);
1427 mtdcr (malrxdeir, 0x80000000);
1428
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001429#ifdef INFO_4XX_ENET
Wolfgang Denk265817c2005-09-25 00:53:22 +02001430 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
wdenkba56f622004-02-06 23:19:44 +00001431#endif
1432
1433 eth_init (hw_p->bis); /* start again... */
1434}
1435
1436/*-----------------------------------------------------------------------------+
1437 * EMAC Error Routine
1438 *-----------------------------------------------------------------------------*/
1439static void emac_err (struct eth_device *dev, unsigned long isr)
1440{
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001441 EMAC_4XX_HW_PST hw_p = dev->priv;
wdenkba56f622004-02-06 23:19:44 +00001442
1443 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
Stefan Roese2d834762007-10-23 14:03:17 +02001444 out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr);
wdenkba56f622004-02-06 23:19:44 +00001445}
1446
1447/*-----------------------------------------------------------------------------+
1448 * enet_rcv() handles the ethernet receive data
1449 *-----------------------------------------------------------------------------*/
1450static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1451{
1452 struct enet_frame *ef_ptr;
1453 unsigned long data_len;
1454 unsigned long rx_eob_isr;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001455 EMAC_4XX_HW_PST hw_p = dev->priv;
wdenkba56f622004-02-06 23:19:44 +00001456
1457 int handled = 0;
1458 int i;
1459 int loop_count = 0;
1460
1461 rx_eob_isr = mfdcr (malrxeobisr);
1462 if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
1463 /* clear EOB */
1464 mtdcr (malrxeobisr, rx_eob_isr);
1465
1466 /* EMAC RX done */
1467 while (1) { /* do all */
1468 i = hw_p->rx_slot;
1469
1470 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1471 || (loop_count >= NUM_RX_BUFF))
1472 break;
Stefan Roesea2e1c702007-07-12 16:32:08 +02001473
wdenkba56f622004-02-06 23:19:44 +00001474 loop_count++;
wdenkba56f622004-02-06 23:19:44 +00001475 handled++;
1476 data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
1477 if (data_len) {
1478 if (data_len > ENET_MAX_MTU) /* Check len */
1479 data_len = 0;
1480 else {
1481 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1482 data_len = 0;
1483 hw_p->stats.rx_err_log[hw_p->
1484 rx_err_index]
1485 = hw_p->rx[i].ctrl;
1486 hw_p->rx_err_index++;
1487 if (hw_p->rx_err_index ==
1488 MAX_ERR_LOG)
1489 hw_p->rx_err_index =
1490 0;
wdenkfc1cfcd2004-04-25 15:41:35 +00001491 } /* emac_erros */
wdenkba56f622004-02-06 23:19:44 +00001492 } /* data_len < max mtu */
wdenkfc1cfcd2004-04-25 15:41:35 +00001493 } /* if data_len */
wdenkba56f622004-02-06 23:19:44 +00001494 if (!data_len) { /* no data */
1495 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1496
1497 hw_p->stats.data_len_err++; /* Error at Rx */
1498 }
1499
1500 /* !data_len */
1501 /* AS.HARNOIS */
1502 /* Check if user has already eaten buffer */
1503 /* if not => ERROR */
1504 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1505 if (hw_p->is_receiving)
1506 printf ("ERROR : Receive buffers are full!\n");
1507 break;
1508 } else {
1509 hw_p->stats.rx_frames++;
1510 hw_p->stats.rx += data_len;
1511 ef_ptr = (struct enet_frame *) hw_p->rx[i].
1512 data_ptr;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001513#ifdef INFO_4XX_ENET
wdenkba56f622004-02-06 23:19:44 +00001514 hw_p->stats.pkts_rx++;
1515#endif
1516 /* AS.HARNOIS
1517 * use ring buffer
1518 */
1519 hw_p->rx_ready[hw_p->rx_i_index] = i;
1520 hw_p->rx_i_index++;
1521 if (NUM_RX_BUFF == hw_p->rx_i_index)
1522 hw_p->rx_i_index = 0;
1523
Stefan Roesea2e1c702007-07-12 16:32:08 +02001524 hw_p->rx_slot++;
1525 if (NUM_RX_BUFF == hw_p->rx_slot)
1526 hw_p->rx_slot = 0;
1527
wdenkba56f622004-02-06 23:19:44 +00001528 /* AS.HARNOIS
1529 * free receive buffer only when
1530 * buffer has been handled (eth_rx)
1531 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1532 */
1533 } /* if data_len */
1534 } /* while */
1535 } /* if EMACK_RXCHL */
1536}
1537
1538
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001539static int ppc_4xx_eth_rx (struct eth_device *dev)
wdenkba56f622004-02-06 23:19:44 +00001540{
1541 int length;
1542 int user_index;
1543 unsigned long msr;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001544 EMAC_4XX_HW_PST hw_p = dev->priv;
wdenkba56f622004-02-06 23:19:44 +00001545
Wolfgang Denk265817c2005-09-25 00:53:22 +02001546 hw_p->is_receiving = 1; /* tell driver */
wdenkba56f622004-02-06 23:19:44 +00001547
1548 for (;;) {
1549 /* AS.HARNOIS
1550 * use ring buffer and
1551 * get index from rx buffer desciptor queue
1552 */
1553 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1554 if (user_index == -1) {
1555 length = -1;
1556 break; /* nothing received - leave for() loop */
1557 }
1558
1559 msr = mfmsr ();
1560 mtmsr (msr & ~(MSR_EE));
1561
1562 length = hw_p->rx[user_index].data_len;
1563
1564 /* Pass the packet up to the protocol layers. */
Wolfgang Denk265817c2005-09-25 00:53:22 +02001565 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1566 /* NetReceive(NetRxPackets[i], length); */
Stefan Roeseff768cb2007-10-31 18:01:24 +01001567 invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
1568 (u32)hw_p->rx[user_index].data_ptr +
Matthias Fuchsfbde2162007-11-09 15:36:44 +01001569 length - 4 - 1);
wdenkba56f622004-02-06 23:19:44 +00001570 NetReceive (NetRxPackets[user_index], length - 4);
1571 /* Free Recv Buffer */
1572 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1573 /* Free rx buffer descriptor queue */
1574 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1575 hw_p->rx_u_index++;
1576 if (NUM_RX_BUFF == hw_p->rx_u_index)
1577 hw_p->rx_u_index = 0;
1578
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001579#ifdef INFO_4XX_ENET
wdenkba56f622004-02-06 23:19:44 +00001580 hw_p->stats.pkts_handled++;
1581#endif
1582
1583 mtmsr (msr); /* Enable IRQ's */
1584 }
1585
Wolfgang Denk265817c2005-09-25 00:53:22 +02001586 hw_p->is_receiving = 0; /* tell driver */
wdenkba56f622004-02-06 23:19:44 +00001587
1588 return length;
1589}
1590
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001591int ppc_4xx_eth_initialize (bd_t * bis)
wdenkba56f622004-02-06 23:19:44 +00001592{
1593 static int virgin = 0;
wdenkba56f622004-02-06 23:19:44 +00001594 struct eth_device *dev;
1595 int eth_num = 0;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001596 EMAC_4XX_HW_PST hw = NULL;
Stefan Roese5fb692c2007-01-18 10:25:34 +01001597 u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
1598 u32 hw_addr[4];
wdenkba56f622004-02-06 23:19:44 +00001599
Stefan Roese846b0dd2005-08-08 12:42:22 +02001600#if defined(CONFIG_440GX)
Stefan Roesec157d8e2005-08-01 16:41:48 +02001601 unsigned long pfc1;
1602
wdenkba56f622004-02-06 23:19:44 +00001603 mfsdr (sdr_pfc1, pfc1);
1604 pfc1 &= ~(0x01e00000);
1605 pfc1 |= 0x01200000;
1606 mtsdr (sdr_pfc1, pfc1);
Stefan Roesec157d8e2005-08-01 16:41:48 +02001607#endif
Stefan Roese5fb692c2007-01-18 10:25:34 +01001608
1609 /* first clear all mac-addresses */
1610 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
1611 memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
1612
1613 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1614 switch (eth_num) {
1615 default: /* fall through */
1616 case 0:
1617 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1618 bis->bi_enetaddr, 6);
1619 hw_addr[eth_num] = 0x0;
1620 break;
1621#ifdef CONFIG_HAS_ETH1
1622 case 1:
1623 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1624 bis->bi_enet1addr, 6);
1625 hw_addr[eth_num] = 0x100;
1626 break;
1627#endif
1628#ifdef CONFIG_HAS_ETH2
1629 case 2:
1630 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1631 bis->bi_enet2addr, 6);
1632 hw_addr[eth_num] = 0x400;
1633 break;
1634#endif
1635#ifdef CONFIG_HAS_ETH3
1636 case 3:
1637 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1638 bis->bi_enet3addr, 6);
1639 hw_addr[eth_num] = 0x600;
1640 break;
1641#endif
1642 }
1643 }
1644
wdenk3c74e322004-02-22 23:46:08 +00001645 /* set phy num and mode */
1646 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001647 bis->bi_phymode[0] = 0;
1648
Stefan Roesec157d8e2005-08-01 16:41:48 +02001649#if defined(CONFIG_PHY1_ADDR)
wdenk3c74e322004-02-22 23:46:08 +00001650 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001651 bis->bi_phymode[1] = 0;
Stefan Roesec157d8e2005-08-01 16:41:48 +02001652#endif
Stefan Roese846b0dd2005-08-08 12:42:22 +02001653#if defined(CONFIG_440GX)
wdenk3c74e322004-02-22 23:46:08 +00001654 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1655 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
wdenk3c74e322004-02-22 23:46:08 +00001656 bis->bi_phymode[2] = 2;
1657 bis->bi_phymode[3] = 2;
Stefan Roesedbbd1252007-10-05 17:10:59 +02001658#endif
wdenkba56f622004-02-06 23:19:44 +00001659
Stefan Roesedbbd1252007-10-05 17:10:59 +02001660#if defined(CONFIG_440GX) || \
1661 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1662 defined(CONFIG_405EX)
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001663 ppc_4xx_eth_setup_bridge(0, bis);
wdenka06752e2004-09-29 22:43:59 +00001664#endif
1665
Stefan Roese1e25f952005-10-20 16:34:28 +02001666 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
Stefan Roese5fb692c2007-01-18 10:25:34 +01001667 /*
1668 * See if we can actually bring up the interface,
1669 * otherwise, skip it
1670 */
1671 if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
1672 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1673 continue;
wdenkba56f622004-02-06 23:19:44 +00001674 }
1675
1676 /* Allocate device structure */
1677 dev = (struct eth_device *) malloc (sizeof (*dev));
1678 if (dev == NULL) {
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001679 printf ("ppc_4xx_eth_initialize: "
wdenk3f85ce22004-02-23 16:11:30 +00001680 "Cannot allocate eth_device %d\n", eth_num);
wdenkba56f622004-02-06 23:19:44 +00001681 return (-1);
1682 }
wdenkb2532ef2005-06-20 10:17:34 +00001683 memset(dev, 0, sizeof(*dev));
wdenkba56f622004-02-06 23:19:44 +00001684
1685 /* Allocate our private use data */
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001686 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
wdenkba56f622004-02-06 23:19:44 +00001687 if (hw == NULL) {
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001688 printf ("ppc_4xx_eth_initialize: "
wdenk3f85ce22004-02-23 16:11:30 +00001689 "Cannot allocate private hw data for eth_device %d",
wdenkba56f622004-02-06 23:19:44 +00001690 eth_num);
1691 free (dev);
1692 return (-1);
1693 }
wdenkb2532ef2005-06-20 10:17:34 +00001694 memset(hw, 0, sizeof(*hw));
wdenkba56f622004-02-06 23:19:44 +00001695
Stefan Roese5fb692c2007-01-18 10:25:34 +01001696 hw->hw_addr = hw_addr[eth_num];
1697 memcpy (dev->enetaddr, ethaddr[eth_num], 6);
wdenkba56f622004-02-06 23:19:44 +00001698 hw->devnum = eth_num;
Stefan Roesec157d8e2005-08-01 16:41:48 +02001699 hw->print_speed = 1;
wdenkba56f622004-02-06 23:19:44 +00001700
Stefan Roese5fb692c2007-01-18 10:25:34 +01001701 sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
wdenkba56f622004-02-06 23:19:44 +00001702 dev->priv = (void *) hw;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001703 dev->init = ppc_4xx_eth_init;
1704 dev->halt = ppc_4xx_eth_halt;
1705 dev->send = ppc_4xx_eth_send;
1706 dev->recv = ppc_4xx_eth_rx;
wdenkba56f622004-02-06 23:19:44 +00001707
1708 if (0 == virgin) {
1709 /* set the MAL IER ??? names may change with new spec ??? */
Stefan Roesedbbd1252007-10-05 17:10:59 +02001710#if defined(CONFIG_440SPE) || \
1711 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1712 defined(CONFIG_405EX)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001713 mal_ier =
1714 MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
1715 MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
1716#else
wdenkba56f622004-02-06 23:19:44 +00001717 mal_ier =
1718 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
1719 MAL_IER_OPBE | MAL_IER_PLBE;
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001720#endif
wdenkba56f622004-02-06 23:19:44 +00001721 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
1722 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
1723 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
1724 mtdcr (malier, mal_ier);
1725
1726 /* install MAL interrupt handler */
1727 irq_install_handler (VECNUM_MS,
1728 (interrupt_handler_t *) enetInt,
1729 dev);
1730 irq_install_handler (VECNUM_MTE,
1731 (interrupt_handler_t *) enetInt,
1732 dev);
1733 irq_install_handler (VECNUM_MRE,
1734 (interrupt_handler_t *) enetInt,
1735 dev);
1736 irq_install_handler (VECNUM_TXDE,
1737 (interrupt_handler_t *) enetInt,
1738 dev);
1739 irq_install_handler (VECNUM_RXDE,
1740 (interrupt_handler_t *) enetInt,
1741 dev);
1742 virgin = 1;
1743 }
1744
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001745#if defined(CONFIG_NET_MULTI)
wdenkba56f622004-02-06 23:19:44 +00001746 eth_register (dev);
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001747#else
1748 emac0_dev = dev;
1749#endif
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001750
1751#if defined(CONFIG_NET_MULTI)
Jon Loeliger3a1ed1e2007-07-09 18:57:22 -05001752#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001753 miiphy_register (dev->name,
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001754 emac4xx_miiphy_read, emac4xx_miiphy_write);
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001755#endif
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001756#endif
wdenkba56f622004-02-06 23:19:44 +00001757 } /* end for each supported device */
1758 return (1);
1759}
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001760
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001761#if !defined(CONFIG_NET_MULTI)
1762void eth_halt (void) {
1763 if (emac0_dev) {
1764 ppc_4xx_eth_halt(emac0_dev);
1765 free(emac0_dev);
1766 emac0_dev = NULL;
1767 }
1768}
1769
1770int eth_init (bd_t *bis)
1771{
1772 ppc_4xx_eth_initialize(bis);
Stefan Roese4f92ac32005-10-10 17:43:58 +02001773 if (emac0_dev) {
1774 return ppc_4xx_eth_init(emac0_dev, bis);
1775 } else {
1776 printf("ERROR: ethaddr not set!\n");
1777 return -1;
1778 }
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001779}
1780
1781int eth_send(volatile void *packet, int length)
1782{
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001783 return (ppc_4xx_eth_send(emac0_dev, packet, length));
1784}
1785
1786int eth_rx(void)
1787{
1788 return (ppc_4xx_eth_rx(emac0_dev));
1789}
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001790
1791int emac4xx_miiphy_initialize (bd_t * bis)
1792{
Jon Loeliger3a1ed1e2007-07-09 18:57:22 -05001793#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001794 miiphy_register ("ppc_4xx_eth0",
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001795 emac4xx_miiphy_read, emac4xx_miiphy_write);
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001796#endif
1797
1798 return 0;
1799}
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001800#endif /* !defined(CONFIG_NET_MULTI) */
1801
Jon Loeliger3a1ed1e2007-07-09 18:57:22 -05001802#endif