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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / fbe76ae4e3bacd5183294488947ec148df28d55b / . / board / rpxsuper / rpxsuper.c
blob: dc558707faab89bdb2444b061e07283bf98cf5fe [file] [log] [blame]
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]1/*
2 * (C) Copyright 2000
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2001
7 * Advent Networks, Inc. <http://www.adventnetworks.com>
8 * Jay Monkman <jtm@smoothsmoothie.com>
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]10 * SPDX-License-Identifier: GPL-2.0+
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]11 */
12
13#include <common.h>
14#include <ioports.h>
15#include <mpc8260.h>
16#include "rpxsuper.h"
17
18/*
19 * I/O Port configuration table
20 *
21 * if conf is 1, then that port pin will be configured at boot time
22 * according to the five values podr/pdir/ppar/psor/pdat for that entry
23 */
24
25const iop_conf_t iop_conf_tab[4][32] = {
26
27 /* Port A configuration */
28 { /* conf ppar psor pdir podr pdat */
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]29 /* PA31 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 *ATMTXEN */
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]30 /* PA30 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTCA */
31 /* PA29 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTSOC */
32 /* PA28 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 *ATMRXEN */
33 /* PA27 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRSOC */
34 /* PA26 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRCA */
35 /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[0] */
36 /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[1] */
37 /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[2] */
38 /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[3] */
39 /* PA21 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[4] */
40 /* PA20 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[5] */
41 /* PA19 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[6] */
42 /* PA18 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXD[7] */
43 /* PA17 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
44 /* PA16 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
45 /* PA15 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
46 /* PA14 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
47 /* PA13 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
48 /* PA12 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
49 /* PA11 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
50 /* PA10 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
51 /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
52 /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
53 /* PA7 */ { 1, 0, 0, 0, 0, 0 }, /* PA7 */
54 /* PA6 */ { 1, 0, 0, 0, 0, 0 }, /* PA6 */
55 /* PA5 */ { 1, 0, 0, 0, 0, 0 }, /* PA5 */
56 /* PA4 */ { 1, 0, 0, 0, 0, 0 }, /* PA4 */
57 /* PA3 */ { 1, 0, 0, 0, 0, 0 }, /* PA3 */
58 /* PA2 */ { 1, 0, 0, 0, 0, 0 }, /* PA2 */
59 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* PA1 */
60 /* PA0 */ { 1, 0, 0, 0, 0, 0 } /* PA0 */
61 },
62
63 /* Port B configuration */
64 { /* conf ppar psor pdir podr pdat */
65 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
66 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
67 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
68 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
69 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
70 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
71 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
72 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
73 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
74 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
75 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
76 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
77 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
78 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
79 /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
80 /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
81 /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
82 /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
83 /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
84 /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
85 /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
86 /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
87 /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
88 /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
89 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
90 /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
91 /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
92 /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
93 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
94 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
95 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
96 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
97 },
98
99 /* Port C */
100 { /* conf ppar psor pdir podr pdat */
101 /* PC31 */ { 1, 0, 0, 1, 0, 0 }, /* PC31 */
102 /* PC30 */ { 1, 0, 0, 1, 0, 0 }, /* PC30 */
103 /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
104 /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* PC28 */
105 /* PC27 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
106 /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* PC26 */
107 /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* PC25 */
108 /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* PC24 */
109 /* PC23 */ { 1, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
110 /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
111 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
112 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
113 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
114 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
115 /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */
116 /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */
117 /* PC15 */ { 1, 0, 0, 0, 0, 0 }, /* PC15 */
118 /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
119 /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* PC13 */
120 /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* PC12 */
121 /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* PC11 */
122 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
123 /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
124 /* PC8 */ { 1, 0, 0, 1, 0, 0 }, /* PC8 */
125 /* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* PC7 */
126 /* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* PC6 */
127 /* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* PC5 */
128 /* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* PC4 */
129 /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* PC3 */
130 /* PC2 */ { 1, 0, 0, 1, 0, 1 }, /* ENET FDE */
131 /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* ENET DSQE */
132 /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* ENET LBK */
133 },
134
135 /* Port D */
136 { /* conf ppar psor pdir podr pdat */
137 /* PD31 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN RxD */
138 /* PD30 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN TxD */
139 /* PD29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 EN TENA */
140 /* PD28 */ { 1, 0, 0, 0, 0, 0 }, /* PD28 */
141 /* PD27 */ { 1, 0, 0, 0, 0, 0 }, /* PD27 */
142 /* PD26 */ { 1, 0, 0, 0, 0, 0 }, /* PD26 */
143 /* PD25 */ { 1, 0, 0, 0, 0, 0 }, /* PD25 */
144 /* PD24 */ { 1, 0, 0, 0, 0, 0 }, /* PD24 */
145 /* PD23 */ { 1, 0, 0, 0, 0, 0 }, /* PD23 */
146 /* PD22 */ { 1, 0, 0, 0, 0, 0 }, /* PD22 */
147 /* PD21 */ { 1, 0, 0, 0, 0, 0 }, /* PD21 */
148 /* PD20 */ { 1, 0, 0, 0, 0, 0 }, /* PD20 */
149 /* PD19 */ { 1, 0, 0, 0, 0, 0 }, /* PD19 */
150 /* PD18 */ { 1, 0, 0, 0, 0, 0 }, /* PD19 */
151 /* PD17 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
152 /* PD16 */ { 1, 0, 0, 0, 0, 0 }, /* FCC1 ATMTXPRTY */
153 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
154 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
155 /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* PD13 */
156 /* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* PD12 */
157 /* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* PD11 */
158 /* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* PD10 */
159 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
160 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
161 /* PD7 */ { 1, 0, 0, 0, 0, 0 }, /* PD7 */
162 /* PD6 */ { 1, 0, 0, 0, 0, 0 }, /* PD6 */
163 /* PD5 */ { 1, 0, 0, 0, 0, 0 }, /* PD5 */
164 /* PD4 */ { 1, 0, 0, 0, 0, 0 }, /* PD4 */
165 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
166 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
167 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
168 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
169 }
170};
171
172/* ------------------------------------------------------------------------- */
173
174/*
175 * Setup CS4 to enable the Board Control/Status registers.
176 * Otherwise the smcs won't work.
177*/
wdenkc837dcb2004-01-20 23:12:12 +0000[diff] [blame]178int board_early_init_f (void)
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]179{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]180 volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
181 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]182 volatile memctl8260_t *memctl = &immap->im_memctl;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]183 memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
184 memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]185 regs->bcsr1 = 0x70; /* to enable terminal no SMC1 */
186 regs->bcsr2 = 0x20; /* mut be written to enable writing FLASH */
187 return 0;
188}
189
190void
191reset_phy(void)
192{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]193 volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]194 regs->bcsr4 = 0xC3;
195}
196
197/*
198 * Check Board Identity:
199 */
200
201int checkboard(void)
202{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]203 volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]204 printf ("Board: Embedded Planet RPX Super, Revision %d\n",
205 regs->bcsr0 >> 4);
206
207 return 0;
208}
209
210/* ------------------------------------------------------------------------- */
211
Becky Bruce9973e3c2008-06-09 16:03:40 -0500[diff] [blame]212phys_size_t initdram(int board_type)
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]213{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]214 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]215 volatile memctl8260_t *memctl = &immap->im_memctl;
216 volatile uchar c = 0, *ramaddr;
217 ulong psdmr, lsdmr, bcr;
218 long size = 0;
219 int i;
220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]221 psdmr = CONFIG_SYS_PSDMR;
222 lsdmr = CONFIG_SYS_LSDMR;
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]223
224 /*
225 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
226 *
227 * "At system reset, initialization software must set up the
228 * programmable parameters in the memory controller banks registers
229 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
230 * system software should execute the following initialization sequence
231 * for each SDRAM device.
232 *
233 * 1. Issue a PRECHARGE-ALL-BANKS command
234 * 2. Issue eight CBR REFRESH commands
235 * 3. Issue a MODE-SET command to initialize the mode register
236 *
237 * The initial commands are executed by setting P/LSDMR[OP] and
238 * accessing the SDRAM with a single-byte transaction."
239 *
240 * The appropriate BRx/ORx registers have already been set when we
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]241 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]242 */
243
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]244 size = CONFIG_SYS_SDRAM0_SIZE;
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]245 bcr = immap->im_siu_conf.sc_bcr;
246 immap->im_siu_conf.sc_bcr = (bcr & ~BCR_EBM);
247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]248 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]250 ramaddr = (uchar *)(CONFIG_SYS_SDRAM0_BASE);
251 memctl->memc_psrt = CONFIG_SYS_PSRT;
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]252
253 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
254 *ramaddr = c;
255
256 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
257 for (i = 0; i < 8; i++)
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]258 *ramaddr = c;
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]259
260 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
261 *ramaddr = c;
262
263 memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
264 *ramaddr = c;
265
266 immap->im_siu_conf.sc_bcr = bcr;
267
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]268#ifndef CONFIG_SYS_RAMBOOT
269/* size += CONFIG_SYS_SDRAM1_SIZE; */
270 ramaddr = (uchar *)(CONFIG_SYS_SDRAM1_BASE);
271 memctl->memc_lsrt = CONFIG_SYS_LSRT;
wdenkfe8c2802002-11-03 00:38:21 +0000[diff] [blame]272
273 memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA;
274 *ramaddr = c;
275
276 memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR;
277 for (i = 0; i < 8; i++)
278 *ramaddr = c;
279
280 memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW;
281 *ramaddr = c;
282
283 memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN;
284 *ramaddr = c;
285#endif
286
287 /* return total ram size */
288 return (size * 1024 * 1024);
289}