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Matt Waddelb80e41a2010-10-07 15:48:45 -06001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8 *
9 * (C) Copyright 2003
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
12 *
13 * (C) Copyright 2004
14 * ARM Ltd.
15 * Philippe Robin, <philippe.robin@arm.com>
16 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020017 * SPDX-License-Identifier: GPL-2.0+
Matt Waddelb80e41a2010-10-07 15:48:45 -060018 */
19#include <common.h>
John Rigby10ed93d2012-07-31 08:59:31 +000020#include <malloc.h>
21#include <errno.h>
Matt Waddelb80e41a2010-10-07 15:48:45 -060022#include <netdev.h>
23#include <asm/io.h>
24#include <asm/arch/systimer.h>
25#include <asm/arch/sysctrl.h>
26#include <asm/arch/wdt.h>
Dirk Behmea6f479c2011-05-23 07:40:26 +000027#include "../drivers/mmc/arm_pl180_mmci.h"
Matt Waddelb80e41a2010-10-07 15:48:45 -060028
Ryan Harkincd4f46e2013-04-09 02:20:31 +000029static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01;
Matt Waddelb80e41a2010-10-07 15:48:45 -060030static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
31
32static void flash__init(void);
33static void vexpress_timer_init(void);
34DECLARE_GLOBAL_DATA_PTR;
35
36#if defined(CONFIG_SHOW_BOOT_PROGRESS)
37void show_boot_progress(int progress)
38{
39 printf("Boot reached stage %d\n", progress);
40}
41#endif
42
43static inline void delay(ulong loops)
44{
45 __asm__ volatile ("1:\n"
46 "subs %0, %1, #1\n"
47 "bne 1b" : "=r" (loops) : "0" (loops));
48}
49
50int board_init(void)
51{
52 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
53 gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
54 gd->flags = 0;
55
56 icache_enable();
57 flash__init();
58 vexpress_timer_init();
59
60 return 0;
61}
62
63int board_eth_init(bd_t *bis)
64{
65 int rc = 0;
66#ifdef CONFIG_SMC911X
67 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
68#endif
69 return rc;
70}
71
Matt Waddelf0c64522011-04-16 11:54:08 +000072int cpu_mmc_init(bd_t *bis)
73{
74 int rc = 0;
John Rigby10ed93d2012-07-31 08:59:31 +000075 (void) bis;
Matt Waddelf0c64522011-04-16 11:54:08 +000076#ifdef CONFIG_ARM_PL180_MMCI
John Rigby10ed93d2012-07-31 08:59:31 +000077 struct pl180_mmc_host *host;
78
79 host = malloc(sizeof(struct pl180_mmc_host));
80 if (!host)
81 return -ENOMEM;
82 memset(host, 0, sizeof(*host));
83
84 strcpy(host->name, "MMC");
85 host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
86 host->pwr_init = INIT_PWR;
87 host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN;
88 host->voltages = VOLTAGE_WINDOW_MMC;
89 host->caps = 0;
90 host->clock_in = ARM_MCLK;
91 host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
92 host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
93 rc = arm_pl180_mmci_init(host);
Matt Waddelf0c64522011-04-16 11:54:08 +000094#endif
95 return rc;
96}
97
Matt Waddelb80e41a2010-10-07 15:48:45 -060098static void flash__init(void)
99{
100 /* Setup the sytem control register to allow writing to flash */
101 writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
102 &sysctrl_base->scflashctrl);
103}
104
105int dram_init(void)
106{
Matt Waddel9d37cf32010-11-02 17:25:21 -0600107 gd->ram_size =
108 get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
Matt Waddelb80e41a2010-10-07 15:48:45 -0600109 return 0;
110}
111
112void dram_init_banksize(void)
113{
114 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
Matt Waddel9d37cf32010-11-02 17:25:21 -0600115 gd->bd->bi_dram[0].size =
116 get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
Matt Waddelb80e41a2010-10-07 15:48:45 -0600117 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
Matt Waddel9d37cf32010-11-02 17:25:21 -0600118 gd->bd->bi_dram[1].size =
119 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
Matt Waddelb80e41a2010-10-07 15:48:45 -0600120}
121
Matt Waddelb80e41a2010-10-07 15:48:45 -0600122/*
123 * Start timer:
124 * Setup a 32 bit timer, running at 1KHz
125 * Versatile Express Motherboard provides 1 MHz timer
126 */
127static void vexpress_timer_init(void)
128{
129 /*
130 * Set clock frequency in system controller:
131 * VEXPRESS_REFCLK is 32KHz
132 * VEXPRESS_TIMCLK is 1MHz
133 */
134 writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
135 SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
136 readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
137
138 /*
139 * Set Timer0 to be:
140 * Enabled, free running, no interrupt, 32-bit, wrapping
141 */
142 writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
143 writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
Ryan Harkin9b58a3f2013-04-09 02:20:30 +0000144 writel(SYSTIMER_EN | SYSTIMER_32BIT |
145 readl(&systimer_base->timer0control),
Matt Waddelb80e41a2010-10-07 15:48:45 -0600146 &systimer_base->timer0control);
Matt Waddelb80e41a2010-10-07 15:48:45 -0600147}
148
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000149int v2m_cfg_write(u32 devfn, u32 data)
150{
151 /* Configuration interface broken? */
152 u32 val;
153
154 devfn |= SYS_CFG_START | SYS_CFG_WRITE;
155
156 val = readl(V2M_SYS_CFGSTAT);
157 writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT);
158
159 writel(data, V2M_SYS_CFGDATA);
160 writel(devfn, V2M_SYS_CFGCTRL);
161
162 do {
163 val = readl(V2M_SYS_CFGSTAT);
164 } while (val == 0);
165
166 return !!(val & SYS_CFG_ERR);
167}
168
Matt Waddelb80e41a2010-10-07 15:48:45 -0600169/* Use the ARM Watchdog System to cause reset */
170void reset_cpu(ulong addr)
171{
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000172 if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
173 printf("Unable to reboot\n");
Matt Waddelb80e41a2010-10-07 15:48:45 -0600174}
175
Matt Waddelb80e41a2010-10-07 15:48:45 -0600176void lowlevel_init(void)
177{
178}
179
180ulong get_board_rev(void){
181 return readl((u32 *)SYS_ID);
182}
Liming Wangd721a3a2012-02-22 04:56:31 +0000183
Jan Kiszka104d6fb2015-04-21 07:18:24 +0200184#ifdef CONFIG_ARMV7_NONSEC
Andre Przywarae261c832013-09-19 18:06:46 +0200185/* Setting the address at which secondary cores start from.
186 * Versatile Express uses one address for all cores, so ignore corenr
187 */
188void smp_set_core_boot_addr(unsigned long addr, int corenr)
189{
190 /* The SYSFLAGS register on VExpress needs to be cleared first
191 * by writing to the next address, since any writes to the address
192 * at offset 0 will only be ORed in
193 */
194 writel(~0, CONFIG_SYSFLAGS_ADDR + 4);
195 writel(addr, CONFIG_SYSFLAGS_ADDR);
196}
197#endif