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wdenk5b1d7132002-11-03 00:07:02 +00001#ifndef __CONFIG_H
2#define __CONFIG_H
3
Wolfgang Denk2ae18242010-10-06 09:05:45 +02004#define CONFIG_SYS_TEXT_BASE 0x80F00000
wdenk5b1d7132002-11-03 00:07:02 +00005
6/*****************************************************************************
7 *
8 * These settings must match the way _your_ board is set up
9 *
10 *****************************************************************************/
11/* for the AY-Revision which does not use the HRCW */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020012#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
wdenk5b1d7132002-11-03 00:07:02 +000013
14/* What is the oscillator's (UX2) frequency in Hz? */
15#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
16
17/* How is switch S2 set? We really only want the MODCK[1-3] bits, so
18 * only the 3 least significant bits are important.
19*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020020#define CONFIG_SYS_SBC_S2 0x04
wdenk5b1d7132002-11-03 00:07:02 +000021
22/* What should MODCK_H be? It is dependent on the oscillator
23 * frequency, MODCK[1-3], and desired CPM and core frequencies.
24 * Some example values (all frequencies are in MHz):
25 *
26 * MODCK_H MODCK[1-3] Osc CPM Core
27 * 0x2 0x2 33 133 133
28 * 0x2 0x4 33 133 200
29 * 0x5 0x5 66 133 133
30 * 0x5 0x7 66 133 200
31 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032#define CONFIG_SYS_SBC_MODCK_H 0x06
wdenk5b1d7132002-11-03 00:07:02 +000033
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034#define CONFIG_SYS_SBC_BOOT_LOW 1 /* only for HRCW */
35#undef CONFIG_SYS_SBC_BOOT_LOW
wdenk5b1d7132002-11-03 00:07:02 +000036
37/* What should the base address of the main FLASH be and how big is
Paul Gortmakerb30d41c2011-09-17 13:47:47 +000038 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE.
wdenk5b1d7132002-11-03 00:07:02 +000039 * The main FLASH is whichever is connected to *CS0. U-Boot expects
40 * this to be the SIMM.
41 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_FLASH0_BASE 0x80000000
43#define CONFIG_SYS_FLASH0_SIZE 16
wdenk5b1d7132002-11-03 00:07:02 +000044
45/* What should the base address of the secondary FLASH be and how big
46 * is it (in Mbytes)? The secondary FLASH is whichever is connected
47 * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
48 * want it enabled, don't define these constants.
49 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#define CONFIG_SYS_FLASH1_BASE 0
51#define CONFIG_SYS_FLASH1_SIZE 0
52#undef CONFIG_SYS_FLASH1_BASE
53#undef CONFIG_SYS_FLASH1_SIZE
wdenk5b1d7132002-11-03 00:07:02 +000054
55/* What should be the base address of SDRAM DIMM and how big is
56 * it (in Mbytes)?
57*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#define CONFIG_SYS_SDRAM0_BASE 0x00000000
59#define CONFIG_SYS_SDRAM0_SIZE 64
wdenk5b1d7132002-11-03 00:07:02 +000060
61/* What should be the base address of SDRAM DIMM and how big is
62 * it (in Mbytes)?
63*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_SDRAM1_BASE 0x04000000
65#define CONFIG_SYS_SDRAM1_SIZE 32
wdenk5b1d7132002-11-03 00:07:02 +000066
67/* What should be the base address of the LEDs and switch S0?
68 * If you don't want them enabled, don't define this.
69 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_LED_BASE 0x00000000
wdenk5b1d7132002-11-03 00:07:02 +000071
72/*
73 * select serial console configuration
74 *
75 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
76 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
77 * for SCC).
78 *
79 * if CONFIG_CONS_NONE is defined, then the serial console routines must
80 * defined elsewhere.
81 */
82#define CONFIG_CONS_ON_SMC /* define if console on SMC */
83#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
84#undef CONFIG_CONS_NONE /* define if console on neither */
85#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
86
87/*
88 * select ethernet configuration
89 *
90 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
91 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
92 * for FCC)
93 *
94 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050095 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenk5b1d7132002-11-03 00:07:02 +000096 */
97#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
98#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
99#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
100#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */
101
102#if ( CONFIG_ETHER_INDEX == 3 )
103
104/*
105 * - Rx-CLK is CLK15
106 * - Tx-CLK is CLK16
107 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
108 * - Enable Half Duplex in FSMR
109 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000110# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
111# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112# define CONFIG_SYS_CPMFCR_RAMTYPE 0
113/*#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */
114# define CONFIG_SYS_FCC_PSMR 0
wdenk5b1d7132002-11-03 00:07:02 +0000115
116#else /* CONFIG_ETHER_INDEX */
117# error "on RPX Super ethernet must be FCC3"
118#endif /* CONFIG_ETHER_INDEX */
119
120#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
122#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk5b1d7132002-11-03 00:07:02 +0000123
124
125/* Define this to reserve an entire FLASH sector (256 KB) for
126 * environment variables. Otherwise, the environment will be
127 * put in the same sector as U-Boot, and changing variables
128 * will erase U-Boot temporarily
129 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200130#define CONFIG_ENV_IN_OWN_SECT
wdenk5b1d7132002-11-03 00:07:02 +0000131
132/* Define to allow the user to overwrite serial and ethaddr */
133#define CONFIG_ENV_OVERWRITE
134
135/* What should the console's baud rate be? */
136#define CONFIG_BAUDRATE 115200
137
138/* Ethernet MAC address */
139#define CONFIG_ETHADDR 08:00:22:50:70:63
140
141#define CONFIG_IPADDR 192.168.1.99
142#define CONFIG_SERVERIP 192.168.1.3
143
144/* Set to a positive value to delay for running BOOTCOMMAND */
145#define CONFIG_BOOTDELAY -1
146
147/* undef this to save memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_LONGHELP
wdenk5b1d7132002-11-03 00:07:02 +0000149
150/* Monitor Command Prompt */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_PROMPT "=> "
wdenk5b1d7132002-11-03 00:07:02 +0000152
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500153
154/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500155 * BOOTP options
156 */
157#define CONFIG_BOOTP_BOOTFILESIZE
158#define CONFIG_BOOTP_BOOTPATH
159#define CONFIG_BOOTP_GATEWAY
160#define CONFIG_BOOTP_HOSTNAME
161
162
163/*
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500164 * Command line configuration.
165 */
166#include <config_cmd_default.h>
167
168#define CONFIG_CMD_IMMAP
169#define CONFIG_CMD_ASKENV
170#define CONFIG_CMD_I2C
171#define CONFIG_CMD_REGINFO
172
173#undef CONFIG_CMD_KGDB
174
wdenk5b1d7132002-11-03 00:07:02 +0000175
176/* Where do the internal registers live? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_IMMR 0xF0000000
wdenk5b1d7132002-11-03 00:07:02 +0000178
179/* Where do the on board registers (CS4) live? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_REGS_BASE 0xFA000000
wdenk5b1d7132002-11-03 00:07:02 +0000181
182/*****************************************************************************
183 *
184 * You should not have to modify any of the following settings
185 *
186 *****************************************************************************/
187
188#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
189#define CONFIG_RPXSUPER 1 /* on an Embedded Planet RPX Super Board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500190#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk5b1d7132002-11-03 00:07:02 +0000191
wdenkc837dcb2004-01-20 23:12:12 +0000192#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
Peter Tyser004eca02009-09-16 22:03:08 -0500193#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenk5b1d7132002-11-03 00:07:02 +0000194
wdenk5b1d7132002-11-03 00:07:02 +0000195/*
196 * Miscellaneous configurable options
197 */
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500198#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk5b1d7132002-11-03 00:07:02 +0000200#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk5b1d7132002-11-03 00:07:02 +0000202#endif
203
204/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
wdenk5b1d7132002-11-03 00:07:02 +0000206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
wdenk5b1d7132002-11-03 00:07:02 +0000208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk5b1d7132002-11-03 00:07:02 +0000210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_MEMTEST_START 0x04000000 /* memtest works on */
212#define CONFIG_SYS_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */
wdenk5b1d7132002-11-03 00:07:02 +0000213
214#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
217#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk5b1d7132002-11-03 00:07:02 +0000218
wdenk5b1d7132002-11-03 00:07:02 +0000219/*
220 * Low Level Configuration Settings
221 * (address mappings, register initial values, etc.)
222 * You should know what you are doing if you make changes here.
223 */
224
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
226#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
wdenk5b1d7132002-11-03 00:07:02 +0000227
228/*-----------------------------------------------------------------------
229 * Hard Reset Configuration Words
230 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#if defined(CONFIG_SYS_SBC_BOOT_LOW)
232# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
wdenk5b1d7132002-11-03 00:07:02 +0000233#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0)
235#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
wdenk5b1d7132002-11-03 00:07:02 +0000236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237/* get the HRCW ISB field from CONFIG_SYS_IMMR */
238#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\
239 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) |\
240 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
wdenk5b1d7132002-11-03 00:07:02 +0000241
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11 |\
wdenk8bde7f72003-06-27 21:31:46 +0000243 HRCW_DPPC11 |\
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244 CONFIG_SYS_SBC_HRCW_IMMR |\
wdenk8bde7f72003-06-27 21:31:46 +0000245 HRCW_MMR00 |\
246 HRCW_LBPC11 |\
247 HRCW_APPC10 |\
248 HRCW_CS10PC00 |\
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249 (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) |\
250 CONFIG_SYS_SBC_HRCW_BOOT_FLAGS)
wdenk5b1d7132002-11-03 00:07:02 +0000251
252/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_HRCW_SLAVE1 0
254#define CONFIG_SYS_HRCW_SLAVE2 0
255#define CONFIG_SYS_HRCW_SLAVE3 0
256#define CONFIG_SYS_HRCW_SLAVE4 0
257#define CONFIG_SYS_HRCW_SLAVE5 0
258#define CONFIG_SYS_HRCW_SLAVE6 0
259#define CONFIG_SYS_HRCW_SLAVE7 0
wdenk5b1d7132002-11-03 00:07:02 +0000260
261/*-----------------------------------------------------------------------
262 * Definitions for initial stack pointer and data area (in DPRAM)
263 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200265#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200266#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk5b1d7132002-11-03 00:07:02 +0000268
269/*-----------------------------------------------------------------------
270 * Start addresses for the final memory configuration
271 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
273 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
wdenk5b1d7132002-11-03 00:07:02 +0000274 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH0_BASE + 0x00F00000)
wdenk5b1d7132002-11-03 00:07:02 +0000276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
278# define CONFIG_SYS_RAMBOOT
wdenk5b1d7132002-11-03 00:07:02 +0000279#endif
280
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
282#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk5b1d7132002-11-03 00:07:02 +0000283
284/*
285 * For booting Linux, the board info and command line data
286 * have to be in the first 8 MB of memory, since this is
287 * the maximum mapped by the Linux kernel during initialization.
288 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk5b1d7132002-11-03 00:07:02 +0000290
291/*-----------------------------------------------------------------------
292 * FLASH and environment organization
293 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
295#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenk5b1d7132002-11-03 00:07:02 +0000296
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
298#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
wdenk5b1d7132002-11-03 00:07:02 +0000299
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200301# define CONFIG_ENV_IS_IN_FLASH 1
wdenk5b1d7132002-11-03 00:07:02 +0000302
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200303# ifdef CONFIG_ENV_IN_OWN_SECT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200305# define CONFIG_ENV_SECT_SIZE 0x40000
wdenk5b1d7132002-11-03 00:07:02 +0000306# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200308# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
309# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
310# endif /* CONFIG_ENV_IN_OWN_SECT */
wdenk5b1d7132002-11-03 00:07:02 +0000311#else
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200312# define CONFIG_ENV_IS_IN_NVRAM 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200314# define CONFIG_ENV_SIZE 0x200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#endif /* CONFIG_SYS_RAMBOOT */
wdenk5b1d7132002-11-03 00:07:02 +0000316
317/*-----------------------------------------------------------------------
318 * Cache Configuration
319 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
wdenk5b1d7132002-11-03 00:07:02 +0000321
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500322#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk5b1d7132002-11-03 00:07:02 +0000324#endif
325
326/*-----------------------------------------------------------------------
327 * HIDx - Hardware Implementation-dependent Registers 2-11
328 *-----------------------------------------------------------------------
329 * HID0 also contains cache control - initially enable both caches and
330 * invalidate contents, then the final state leaves only the instruction
331 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
332 * but Soft reset does not.
333 *
334 * HID1 has only read-only information - nothing to set.
335 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_HID0_INIT (/*HID0_ICE |*/\
wdenk5b1d7132002-11-03 00:07:02 +0000337 /*HID0_DCE |*/\
338 HID0_ICFI |\
339 HID0_DCI |\
340 HID0_IFEM |\
341 HID0_ABE)
342
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_HID0_FINAL (/*HID0_ICE |*/\
wdenk5b1d7132002-11-03 00:07:02 +0000344 HID0_IFEM |\
345 HID0_ABE |\
346 HID0_EMCP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_HID2 0
wdenk5b1d7132002-11-03 00:07:02 +0000348
349/*-----------------------------------------------------------------------
350 * RMR - Reset Mode Register
351 *-----------------------------------------------------------------------
352 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_RMR 0
wdenk5b1d7132002-11-03 00:07:02 +0000354
355/*-----------------------------------------------------------------------
356 * BCR - Bus Configuration 4-25
357 *-----------------------------------------------------------------------
358 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_BCR (BCR_EBM |\
wdenk5b1d7132002-11-03 00:07:02 +0000360 BCR_PLDP |\
361 BCR_EAV |\
362 BCR_NPQM0)
363
364/*-----------------------------------------------------------------------
365 * SIUMCR - SIU Module Configuration 4-31
366 *-----------------------------------------------------------------------
367 */
368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_SIUMCR (SIUMCR_L2CPC01 |\
wdenk8bde7f72003-06-27 21:31:46 +0000370 SIUMCR_APPC10 |\
371 SIUMCR_CS10PC01)
wdenk5b1d7132002-11-03 00:07:02 +0000372
373
374/*-----------------------------------------------------------------------
375 * SYPCR - System Protection Control 11-9
376 * SYPCR can only be written once after reset!
377 *-----------------------------------------------------------------------
378 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
379 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
wdenk8bde7f72003-06-27 21:31:46 +0000381 SYPCR_BMT |\
382 SYPCR_PBME |\
383 SYPCR_LBME |\
384 SYPCR_SWRI |\
385 SYPCR_SWP)
wdenk5b1d7132002-11-03 00:07:02 +0000386
387/*-----------------------------------------------------------------------
388 * TMCNTSC - Time Counter Status and Control 4-40
389 *-----------------------------------------------------------------------
390 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
391 * and enable Time Counter
392 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
wdenk8bde7f72003-06-27 21:31:46 +0000394 TMCNTSC_ALR |\
395 TMCNTSC_TCF |\
396 TMCNTSC_TCE)
wdenk5b1d7132002-11-03 00:07:02 +0000397
398/*-----------------------------------------------------------------------
399 * PISCR - Periodic Interrupt Status and Control 4-42
400 *-----------------------------------------------------------------------
401 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
402 * Periodic timer
403 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_PISCR (PISCR_PS |\
wdenk8bde7f72003-06-27 21:31:46 +0000405 PISCR_PTF |\
406 PISCR_PTE)
wdenk5b1d7132002-11-03 00:07:02 +0000407
408/*-----------------------------------------------------------------------
409 * SCCR - System Clock Control 9-8
410 *-----------------------------------------------------------------------
411 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_SCCR (SCCR_DFBRG01)
wdenk5b1d7132002-11-03 00:07:02 +0000413
414/*-----------------------------------------------------------------------
415 * RCCR - RISC Controller Configuration 13-7
416 *-----------------------------------------------------------------------
417 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_RCCR 0
wdenk5b1d7132002-11-03 00:07:02 +0000419
420/*
421 * Init Memory Controller:
422 *
423 * Bank Bus Machine PortSz Device
424 * ---- --- ------- ------ ------
425 * 0 60x GPCM 64 bit FLASH (BGA - 16MB AMD AM29DL323DB90)
426 * 1 60x SDRAM 64 bit SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60)
427 * 2 Local SDRAM 32 bit SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60)
428 * 3 unused
429 * 4 60x GPCM 8 bit Board Regs, LEDs, switches
430 * 5 unused
431 * 6 unused
432 * 7 unused
433 * 8 PCMCIA
434 * 9 unused
435 * 10 unused
436 * 11 unused
437*/
438
439/* Bank 0 - FLASH
440 *
441 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000443 BRx_PS_64 |\
wdenk5b1d7132002-11-03 00:07:02 +0000444 BRx_DECC_NONE |\
wdenk8bde7f72003-06-27 21:31:46 +0000445 BRx_MS_GPCM_P |\
446 BRx_V)
wdenk5b1d7132002-11-03 00:07:02 +0000447
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000449 ORxG_CSNT |\
450 ORxG_ACS_DIV1 |\
451 ORxG_SCY_6_CLK |\
452 ORxG_EHTR)
wdenk5b1d7132002-11-03 00:07:02 +0000453
454/* Bank 1 - SDRAM
455 *
456 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000458 BRx_PS_64 |\
459 BRx_MS_SDRAM_P |\
460 BRx_V)
wdenk5b1d7132002-11-03 00:07:02 +0000461
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000463 ORxS_BPD_4 |\
464 ORxS_ROWST_PBI0_A8 |\
465 ORxS_NUMR_12 |\
wdenk5b1d7132002-11-03 00:07:02 +0000466 ORxS_IBID)
467
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_PSDMR 0x014DA412
469#define CONFIG_SYS_PSRT 0x79
wdenk5b1d7132002-11-03 00:07:02 +0000470
471
472/* Bank 2 - SDRAM
473 *
474 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000476 BRx_PS_32 |\
477 BRx_MS_SDRAM_L |\
478 BRx_V)
wdenk5b1d7132002-11-03 00:07:02 +0000479
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000481 ORxS_BPD_4 |\
482 ORxS_ROWST_PBI0_A9 |\
483 ORxS_NUMR_12)
wdenk5b1d7132002-11-03 00:07:02 +0000484
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485#define CONFIG_SYS_LSDMR 0x0169A512
486#define CONFIG_SYS_LSRT 0x79
wdenk5b1d7132002-11-03 00:07:02 +0000487
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200488#define CONFIG_SYS_MPTPR (0x0800 & MPTPR_PTP_MSK)
wdenk5b1d7132002-11-03 00:07:02 +0000489
490/* Bank 4 - On board registers
491 *
492 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200493#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000494 BRx_PS_8 |\
495 BRx_MS_GPCM_P |\
496 BRx_V)
wdenk5b1d7132002-11-03 00:07:02 +0000497
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200498#define CONFIG_SYS_OR4_PRELIM (ORxG_AM_MSK |\
wdenk8bde7f72003-06-27 21:31:46 +0000499 ORxG_CSNT |\
500 ORxG_ACS_DIV1 |\
501 ORxG_SCY_5_CLK |\
502 ORxG_TRLX)
wdenk5b1d7132002-11-03 00:07:02 +0000503
wdenk5b1d7132002-11-03 00:07:02 +0000504#endif /* __CONFIG_H */