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Albert Aribaudce9c2272010-06-17 19:38:21 +05301/*
Albert ARIBAUD57b4bce2011-04-22 19:41:02 +02002 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
Albert Aribaudce9c2272010-06-17 19:38:21 +05303 *
4 * Based on original Kirkwood support which is
5 * (C) Copyright 2009
6 * Marvell Semiconductor <www.marvell.com>
7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
25 * MA 02110-1301 USA
26 */
27
28#ifndef _CONFIG_EDMINIV2_H
29#define _CONFIG_EDMINIV2_H
30
31/*
32 * Version number information
33 */
34
35#define CONFIG_IDENT_STRING " EDMiniV2"
36
37/*
38 * High Level Configuration Options (easy to change)
39 */
40
41#define CONFIG_MARVELL 1
42#define CONFIG_ARM926EJS 1 /* Basic Architecture */
43#define CONFIG_FEROCEON 1 /* CPU Core subversion */
44#define CONFIG_ORION5X 1 /* SOC Family Name */
45#define CONFIG_88F5182 1 /* SOC Name */
46#define CONFIG_MACH_EDMINIV2 1 /* Machine type */
47
Lei Wen5ff8b352011-10-24 16:27:32 +000048#include <asm/arch/orion5x.h>
Albert Aribaudce9c2272010-06-17 19:38:21 +053049/*
50 * CLKs configurations
51 */
52
53#define CONFIG_SYS_HZ 1000
54
55/*
56 * Board-specific values for Orion5x MPP low level init:
57 * - MPPs 12 to 15 are SATA LEDs (mode 5)
58 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
59 * MPP16 to MPP19, mode 0 for others
60 */
61
62#define ORION5X_MPP0_7 0x00000003
63#define ORION5X_MPP8_15 0x55550000
Albert Aribaudecaf3af2010-08-08 05:17:06 +053064#define ORION5X_MPP16_23 0x00005555
Albert Aribaudce9c2272010-06-17 19:38:21 +053065
66/*
67 * Board-specific values for Orion5x GPIO low level init:
68 * - GPIO3 is input (RTC interrupt)
69 * - GPIO16 is Power LED control (0 = on, 1 = off)
70 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
71 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
72 * - Last GPIO is 26, further bits are supposed to be 0.
73 * Enable mask has ones for INPUT, 0 for OUTPUT.
74 * Default is LED ON.
75 */
76
77#define ORION5X_GPIO_OUT_ENABLE 0x03fcffff
78#define ORION5X_GPIO_OUT_VALUE 0x03fcffff
79
80/*
81 * NS16550 Configuration
82 */
83
84#define CONFIG_SYS_NS16550
85#define CONFIG_SYS_NS16550_SERIAL
86#define CONFIG_SYS_NS16550_REG_SIZE (-4)
87#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
88#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE
89
90/*
91 * Serial Port configuration
92 * The following definitions let you select what serial you want to use
93 * for your console driver.
94 */
95
96#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
97#define CONFIG_BAUDRATE 115200
98#define CONFIG_SYS_BAUDRATE_TABLE \
99 { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
100
101/*
102 * FLASH configuration
103 */
104
105#define CONFIG_SYS_FLASH_CFI
106#define CONFIG_FLASH_CFI_DRIVER
107#define CONFIG_FLASH_CFI_LEGACY
108#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
109#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
110#define CONFIG_SYS_FLASH_BASE 0xfff80000
111#define CONFIG_SYS_FLASH_SECTSZ \
112 {16384, 8192, 8192, 32768, \
113 65536, 65536, 65536, 65536, 65536, 65536, 65536}
114
115/* auto boot */
116#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
117
118/*
119 * For booting Linux, the board info and command line data
120 * have to be in the first 8 MB of memory, since this is
121 * the maximum mapped by the Linux kernel during initialization.
122 */
123#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
124#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
125#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
126
127#define CONFIG_SYS_PROMPT "EDMiniV2> " /* Command Prompt */
128#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
129#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
130 +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
131/*
132 * Commands configuration - using default command set for now
133 */
134#include <config_cmd_default.h>
Albert Aribaudecaf3af2010-08-08 05:17:06 +0530135#define CONFIG_CMD_IDE
Albert Aribaudc2ca44c2010-08-27 18:26:06 +0200136#define CONFIG_CMD_I2C
Albert ARIBAUD81a6c002012-01-15 22:08:41 +0000137#define CONFIG_CMD_USB
Albert Aribaudab9164d2010-07-12 22:24:30 +0200138
Albert Aribaudce9c2272010-06-17 19:38:21 +0530139/*
Albert Aribaudab9164d2010-07-12 22:24:30 +0200140 * Network
Albert Aribaudce9c2272010-06-17 19:38:21 +0530141 */
Albert Aribaudab9164d2010-07-12 22:24:30 +0200142
143#ifdef CONFIG_CMD_NET
144#define CONFIG_MVGBE /* Enable Marvell GbE Driver */
145#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */
146#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */
147#define CONFIG_PHY_BASE_ADR 0x8
148#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
149#define CONFIG_NETCONSOLE /* include NetConsole support */
Albert Aribaudab9164d2010-07-12 22:24:30 +0200150#define CONFIG_MII /* expose smi ove miiphy interface */
151#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
152#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
153#endif
Albert Aribaudce9c2272010-06-17 19:38:21 +0530154
155/*
Albert Aribaudecaf3af2010-08-08 05:17:06 +0530156 * IDE
157 */
158#ifdef CONFIG_CMD_IDE
159#define __io
160#define CONFIG_IDE_PREINIT
161#define CONFIG_DOS_PARTITION
162#define CONFIG_CMD_EXT2
163/* ED Mini V has an IDE-compatible SATA connector for port 1 */
164#define CONFIG_MVSATA_IDE
165#define CONFIG_MVSATA_IDE_USE_PORT1
166/* Needs byte-swapping for ATA data register */
167#define CONFIG_IDE_SWAP_IO
168/* Data, registers and alternate blocks are at the same offset */
169#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
170#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
171#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
172/* Each 8-bit ATA register is aligned to a 4-bytes address */
173#define CONFIG_SYS_ATA_STRIDE 4
174/* Controller supports 48-bits LBA addressing */
175#define CONFIG_LBA48
176/* A single bus, a single device */
177#define CONFIG_SYS_IDE_MAXBUS 1
178#define CONFIG_SYS_IDE_MAXDEVICE 1
179/* ATA registers base is at SATA controller base */
180#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE
181/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
182#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET
183/* end of IDE defines */
184#endif /* CMD_IDE */
185
186/*
Albert ARIBAUD81a6c002012-01-15 22:08:41 +0000187 * Common USB/EHCI configuration
188 */
189#ifdef CONFIG_CMD_USB
190#define CONFIG_USB_EHCI /* Enable EHCI USB support */
191#define CONFIG_USB_EHCI_MARVELL
192#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
193#define CONFIG_USB_STORAGE
194#define CONFIG_DOS_PARTITION
195#define CONFIG_ISO_PARTITION
196#define CONFIG_SUPPORT_VFAT
197#endif /* CONFIG_CMD_USB */
198
199/*
Albert Aribaudc2ca44c2010-08-27 18:26:06 +0200200 * I2C related stuff
201 */
202#ifdef CONFIG_CMD_I2C
203#define CONFIG_I2C_MVTWSI
204#define CONFIG_I2C_MVTWSI_BASE ORION5X_TWSI_BASE
205#define CONFIG_SYS_I2C_SLAVE 0x0
206#define CONFIG_SYS_I2C_SPEED 100000
207#endif
208
209/*
Albert Aribaudce9c2272010-06-17 19:38:21 +0530210 * Environment variables configurations
211 */
212#define CONFIG_ENV_IS_IN_FLASH 1
213#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */
214#define CONFIG_ENV_SIZE 0x2000
215#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */
216
217/*
218 * Size of malloc() pool
219 */
220#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
Albert Aribaudce9c2272010-06-17 19:38:21 +0530221
222/*
223 * Other required minimal configurations
224 */
225#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
226#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
227#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
228#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
229#define CONFIG_NR_DRAM_BANKS 1
230
231#define CONFIG_STACKSIZE 0x00100000
232#define CONFIG_SYS_LOAD_ADDR 0x00800000
233#define CONFIG_SYS_MEMTEST_START 0x00400000
234#define CONFIG_SYS_MEMTEST_END 0x007fffff
235#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
236#define CONFIG_SYS_MAXARGS 16
237
Albert ARIBAUDa203a7c2012-02-06 20:32:19 +0530238/* Use the HUSH parser */
239#define CONFIG_SYS_HUSH_PARSER
Albert ARIBAUDa203a7c2012-02-06 20:32:19 +0530240
241/* Enable command line editing */
242#define CONFIG_CMDLINE_EDITING
243
244/* provide extensive help */
245#define CONFIG_SYS_LONGHELP
246
Albert Aribaud06939232010-10-11 13:13:29 +0200247/* additions for new relocation code, must be added to all boards */
248#define CONFIG_SYS_SDRAM_BASE 0
249#define CONFIG_SYS_INIT_SP_ADDR \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200250 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
Albert Aribaud06939232010-10-11 13:13:29 +0200251
Albert Aribaudce9c2272010-06-17 19:38:21 +0530252#endif /* _CONFIG_EDMINIV2_H */