| Mike Frysinger | d4d7730 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 1 | /* |
| 2 | * TWI Masks |
| 3 | */ |
| 4 | |
| 5 | #ifndef __BFIN_PERIPHERAL_TWI__ |
| 6 | #define __BFIN_PERIPHERAL_TWI__ |
| 7 | |
| 8 | /* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ |
| 9 | #define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ |
| 10 | #define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ |
| 11 | |
| 12 | /* TWI_PRESCALE Masks */ |
| 13 | #define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ |
| 14 | #define TWI_ENA 0x0080 /* TWI Enable */ |
| 15 | #define SCCB 0x0200 /* SCCB Compatibility Enable */ |
| 16 | |
| 17 | /* TWI_SLAVE_CTL Masks */ |
| 18 | #define SEN 0x0001 /* Slave Enable */ |
| 19 | #define SADD_LEN 0x0002 /* Slave Address Length */ |
| 20 | #define STDVAL 0x0004 /* Slave Transmit Data Valid */ |
| 21 | #define TSC_NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ |
| 22 | #define GEN 0x0010 /* General Call Adrress Matching Enabled */ |
| 23 | |
| 24 | /* TWI_SLAVE_STAT Masks */ |
| 25 | #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ |
| 26 | #define GCALL 0x0002 /* General Call Indicator */ |
| 27 | |
| 28 | /* TWI_MASTER_CTRL Masks */ |
| 29 | #define MEN 0x0001 /* Master Mode Enable */ |
| 30 | #define MADD_LEN 0x0002 /* Master Address Length */ |
| 31 | #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ |
| 32 | #define FAST 0x0008 /* Use Fast Mode Timing Specs */ |
| 33 | #define STOP 0x0010 /* Issue Stop Condition */ |
| 34 | #define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ |
| 35 | #define DCNT 0x3FC0 /* Data Bytes To Transfer */ |
| 36 | #define SDAOVR 0x4000 /* Serial Data Override */ |
| 37 | #define SCLOVR 0x8000 /* Serial Clock Override */ |
| 38 | |
| 39 | /* TWI_MASTER_STAT Masks */ |
| 40 | #define MPROG 0x0001 /* Master Transfer In Progress */ |
| 41 | #define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ |
| 42 | #define ANAK 0x0004 /* Address Not Acknowledged */ |
| 43 | #define DNAK 0x0008 /* Data Not Acknowledged */ |
| 44 | #define BUFRDERR 0x0010 /* Buffer Read Error */ |
| 45 | #define BUFWRERR 0x0020 /* Buffer Write Error */ |
| 46 | #define SDASEN 0x0040 /* Serial Data Sense */ |
| 47 | #define SCLSEN 0x0080 /* Serial Clock Sense */ |
| 48 | #define BUSBUSY 0x0100 /* Bus Busy Indicator */ |
| 49 | |
| 50 | /* TWI_INT_SRC and TWI_INT_ENABLE Masks */ |
| 51 | #define SINIT 0x0001 /* Slave Transfer Initiated */ |
| 52 | #define SCOMP 0x0002 /* Slave Transfer Complete */ |
| 53 | #define SERR 0x0004 /* Slave Transfer Error */ |
| 54 | #define SOVF 0x0008 /* Slave Overflow */ |
| 55 | #define MCOMP 0x0010 /* Master Transfer Complete */ |
| 56 | #define MERR 0x0020 /* Master Transfer Error */ |
| 57 | #define XMTSERV 0x0040 /* Transmit FIFO Service */ |
| 58 | #define RCVSERV 0x0080 /* Receive FIFO Service */ |
| 59 | |
| 60 | /* TWI_FIFO_CTRL Masks */ |
| 61 | #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ |
| 62 | #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ |
| 63 | #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ |
| 64 | #define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ |
| 65 | |
| 66 | /* TWI_FIFO_STAT Masks */ |
| 67 | #define XMTSTAT 0x0003 /* Transmit FIFO Status */ |
| 68 | #define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ |
| 69 | #define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ |
| 70 | #define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ |
| 71 | |
| 72 | #define RCVSTAT 0x000C /* Receive FIFO Status */ |
| 73 | #define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ |
| 74 | #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ |
| 75 | #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ |
| 76 | |
| 77 | #endif |