blob: 656d10dffbf8f93e1c9f13978a400fa8f72a80d9 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mingkai Huf3a8e2b2015-10-26 19:47:52 +08002/*
3 * Copyright (C) 2015 Freescale Semiconductor
Mingkai Huf3a8e2b2015-10-26 19:47:52 +08004 */
5
6#ifndef __LS1043A_COMMON_H
7#define __LS1043A_COMMON_H
8
Sumit Garg4139b172017-03-30 09:52:38 +05309/* SPL build */
10#ifdef CONFIG_SPL_BUILD
11#define SPL_NO_FMAN
12#define SPL_NO_DSPI
13#define SPL_NO_PCIE
14#define SPL_NO_ENV
15#define SPL_NO_MISC
16#define SPL_NO_USB
17#define SPL_NO_SATA
18#define SPL_NO_QE
19#define SPL_NO_EEPROM
20#endif
21#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
22#define SPL_NO_MMC
23#endif
Yangbo Lu3c7d6472017-09-15 09:51:58 +080024#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
Sumit Garg4139b172017-03-30 09:52:38 +053025#define SPL_NO_IFC
26#endif
27
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080028#define CONFIG_REMAKE_ELF
29#define CONFIG_FSL_LAYERSCAPE
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080030#define CONFIG_GICV2
31
Bharat Bhushan5344c7b2017-03-22 12:06:27 +053032#include <asm/arch/stream_id_lsch2.h>
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080033#include <asm/arch/config.h>
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080034
35/* Link Definitions */
36#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
37
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080038#define CONFIG_SKIP_LOWLEVEL_INIT
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080039
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080040#define CONFIG_VERY_BIG_RAM
41#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
42#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
43#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Shaohui Xiee994ddd2015-11-23 15:23:48 +080044#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080045
Hou Zhiqiang831c0682015-10-26 19:47:57 +080046#define CPU_RELEASE_ADDR secondary_boot_func
47
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080048/* Generic Timer Definitions */
49#define COUNTER_FREQUENCY 25000000 /* 25MHz */
50
51/* Size of malloc() pool */
52#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
53
54/* Serial Port */
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080055#define CONFIG_SYS_NS16550_SERIAL
56#define CONFIG_SYS_NS16550_REG_SIZE 1
Hou Zhiqiang904110c2017-01-10 16:44:15 +080057#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080058
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080059#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
60
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080061/* SD boot SPL */
62#ifdef CONFIG_SD_BOOT
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080063
64#define CONFIG_SPL_TEXT_BASE 0x10000000
Ruchika Gupta70f96612017-04-17 18:07:17 +053065#define CONFIG_SPL_MAX_SIZE 0x17000
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080066#define CONFIG_SPL_STACK 0x1001e000
67#define CONFIG_SPL_PAD_TO 0x1d000
68
York Sun23af4842017-09-28 08:42:16 -070069#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
70 CONFIG_SPL_BSS_MAX_SIZE)
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080071#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
York Sun23af4842017-09-28 08:42:16 -070072#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080073#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
Ruchika Gupta70f96612017-04-17 18:07:17 +053074
75#ifdef CONFIG_SECURE_BOOT
76#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
77/*
78 * HDR would be appended at end of image and copied to DDR along
79 * with U-Boot image. Here u-boot max. size is 512K. So if binary
80 * size increases then increase this size in case of secure boot as
81 * it uses raw u-boot image instead of fit image.
82 */
83#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
84#else
85#define CONFIG_SYS_MONITOR_LEN 0x100000
86#endif /* ifdef CONFIG_SECURE_BOOT */
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080087#endif
88
Gong Qianyu3ad44722015-10-26 19:47:53 +080089/* NAND SPL */
90#ifdef CONFIG_NAND_BOOT
91#define CONFIG_SPL_PBL_PAD
Gong Qianyu3ad44722015-10-26 19:47:53 +080092#define CONFIG_SPL_TEXT_BASE 0x10000000
93#define CONFIG_SPL_MAX_SIZE 0x1a000
94#define CONFIG_SPL_STACK 0x1001d000
95#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
96#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
97#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
98#define CONFIG_SPL_BSS_START_ADDR 0x80100000
99#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
100#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
Ruchika Gupta762f92a2017-04-17 18:07:18 +0530101
102#ifdef CONFIG_SECURE_BOOT
103#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
104#endif /* ifdef CONFIG_SECURE_BOOT */
105
106#ifdef CONFIG_U_BOOT_HDR_SIZE
107/*
108 * HDR would be appended at end of image and copied to DDR along
109 * with U-Boot image. Here u-boot max. size is 512K. So if binary
110 * size increases then increase this size in case of secure boot as
111 * it uses raw u-boot image instead of fit image.
112 */
113#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
114#else
115#define CONFIG_SYS_MONITOR_LEN 0x100000
116#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
117
Gong Qianyu3ad44722015-10-26 19:47:53 +0800118#endif
119
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800120/* IFC */
Sumit Garg4139b172017-03-30 09:52:38 +0530121#ifndef SPL_NO_IFC
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800122#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800123#define CONFIG_FSL_IFC
124/*
125 * CONFIG_SYS_FLASH_BASE has the final address (core view)
126 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
127 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
128 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
129 */
130#define CONFIG_SYS_FLASH_BASE 0x60000000
131#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
132#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
133
Masahiro Yamadae856bdc2017-02-11 22:43:54 +0900134#ifdef CONFIG_MTD_NOR_FLASH
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800135#define CONFIG_FLASH_CFI_DRIVER
136#define CONFIG_SYS_FLASH_CFI
137#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
138#define CONFIG_SYS_FLASH_QUIET_TEST
139#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
140#endif
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800141#endif
Sumit Garg4139b172017-03-30 09:52:38 +0530142#endif
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800143
144/* I2C */
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800145#define CONFIG_SYS_I2C
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800146
147/* PCIe */
Sumit Garg4139b172017-03-30 09:52:38 +0530148#ifndef SPL_NO_PCIE
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800149#define CONFIG_PCIE1 /* PCIE controller 1 */
150#define CONFIG_PCIE2 /* PCIE controller 2 */
151#define CONFIG_PCIE3 /* PCIE controller 3 */
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800152
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800153#ifdef CONFIG_PCI
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800154#define CONFIG_PCI_SCAN_SHOW
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800155#endif
Sumit Garg4139b172017-03-30 09:52:38 +0530156#endif
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800157
158/* Command line configuration */
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800159
Yangbo Lu8ef0d5c2015-10-26 19:47:55 +0800160/* MMC */
Sumit Garg4139b172017-03-30 09:52:38 +0530161#ifndef SPL_NO_MMC
Yangbo Lu8ef0d5c2015-10-26 19:47:55 +0800162#ifdef CONFIG_MMC
Yangbo Lu8ef0d5c2015-10-26 19:47:55 +0800163#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
Yangbo Lu8ef0d5c2015-10-26 19:47:55 +0800164#endif
Sumit Garg4139b172017-03-30 09:52:38 +0530165#endif
Yangbo Lu8ef0d5c2015-10-26 19:47:55 +0800166
Gong Qianyue0579a52016-01-25 15:16:05 +0800167/* DSPI */
Sumit Garg4139b172017-03-30 09:52:38 +0530168#ifndef SPL_NO_DSPI
Gong Qianyue0579a52016-01-25 15:16:05 +0800169#define CONFIG_FSL_DSPI
170#ifdef CONFIG_FSL_DSPI
Gong Qianyue0579a52016-01-25 15:16:05 +0800171#define CONFIG_DM_SPI_FLASH
172#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
173#define CONFIG_SPI_FLASH_SST /* cs1 */
174#define CONFIG_SPI_FLASH_EON /* cs2 */
Qianyu Gongb0f20ca2016-01-25 15:16:07 +0800175#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Gong Qianyue0579a52016-01-25 15:16:05 +0800176#define CONFIG_SF_DEFAULT_BUS 1
177#define CONFIG_SF_DEFAULT_CS 0
178#endif
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800179#endif
Sumit Garg4139b172017-03-30 09:52:38 +0530180#endif
Gong Qianyue0579a52016-01-25 15:16:05 +0800181
Shaohui Xiee8297342015-10-26 19:47:54 +0800182/* FMan ucode */
Sumit Garg4139b172017-03-30 09:52:38 +0530183#ifndef SPL_NO_FMAN
Shaohui Xiee8297342015-10-26 19:47:54 +0800184#define CONFIG_SYS_DPAA_FMAN
185#ifdef CONFIG_SYS_DPAA_FMAN
186#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
187
Qianyu Gongfd1b1472016-04-01 17:52:52 +0800188#ifdef CONFIG_NAND_BOOT
Alison Wanga9a5cef2017-05-16 10:45:58 +0800189/* Store Fman ucode at offeset 0x900000(72 blocks). */
Qianyu Gongfd1b1472016-04-01 17:52:52 +0800190#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Alison Wanga9a5cef2017-05-16 10:45:58 +0800191#define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
Qianyu Gong2a555832016-04-01 17:52:53 +0800192#elif defined(CONFIG_SD_BOOT)
193/*
194 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
195 * about 1MB (2040 blocks), Env is stored after the image, and the env size is
Alison Wanga9a5cef2017-05-16 10:45:58 +0800196 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
Qianyu Gong2a555832016-04-01 17:52:53 +0800197 */
198#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Alison Wanga9a5cef2017-05-16 10:45:58 +0800199#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
Zhao Qiang5aa03dd2017-05-25 09:47:40 +0800200#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08)
Qianyu Gong2a555832016-04-01 17:52:53 +0800201#elif defined(CONFIG_QSPI_BOOT)
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800202#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Alison Wanga9a5cef2017-05-16 10:45:58 +0800203#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800204#define CONFIG_ENV_SPI_BUS 0
205#define CONFIG_ENV_SPI_CS 0
206#define CONFIG_ENV_SPI_MAX_HZ 1000000
207#define CONFIG_ENV_SPI_MODE 0x03
208#else
Shaohui Xiee8297342015-10-26 19:47:54 +0800209#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
210/* FMan fireware Pre-load address */
Alison Wanga9a5cef2017-05-16 10:45:58 +0800211#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
Zhao Qiang5aa03dd2017-05-25 09:47:40 +0800212#define CONFIG_SYS_QE_FW_ADDR 0x60940000
Gong Qianyu166ef1e2016-01-25 15:16:06 +0800213#endif
Shaohui Xiee8297342015-10-26 19:47:54 +0800214#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
215#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
216#endif
Sumit Garg4139b172017-03-30 09:52:38 +0530217#endif
Shaohui Xiee8297342015-10-26 19:47:54 +0800218
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800219/* Miscellaneous configurable options */
220#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800221
222#define CONFIG_HWCONFIG
223#define HWCONFIG_BUFFER_SIZE 128
224
Sumit Garg4139b172017-03-30 09:52:38 +0530225#ifndef SPL_NO_MISC
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800226#ifndef CONFIG_SPL_BUILD
227#define BOOT_TARGET_DEVICES(func) \
228 func(MMC, mmc, 0) \
229 func(USB, usb, 0)
230#include <config_distro_bootcmd.h>
231#endif
232
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800233/* Initial environment variables */
234#define CONFIG_EXTRA_ENV_SETTINGS \
235 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800236 "fdt_high=0xffffffffffffffff\0" \
237 "initrd_high=0xffffffffffffffff\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800238 "fdt_addr=0x64f00000\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530239 "kernel_addr=0x61000000\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800240 "scriptaddr=0x80000000\0" \
Sumit Garg76bbf1c2017-06-05 23:51:51 +0530241 "scripthdraddr=0x80080000\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800242 "fdtheader_addr_r=0x80100000\0" \
243 "kernelheader_addr_r=0x80200000\0" \
244 "kernel_addr_r=0x81000000\0" \
245 "fdt_addr_r=0x90000000\0" \
246 "load_addr=0xa0000000\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530247 "kernelheader_addr=0x60800000\0" \
Qianyu Gongad6767b2016-03-15 16:35:57 +0800248 "kernel_size=0x2800000\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530249 "kernelheader_size=0x40000\0" \
Shengzhou Liu1c8263d2017-11-09 17:57:55 +0800250 "kernel_addr_sd=0x8000\0" \
251 "kernel_size_sd=0x14000\0" \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530252 "kernelhdr_addr_sd=0x4000\0" \
253 "kernelhdr_size_sd=0x10\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800254 "console=ttyS0,115200\0" \
York Sun23af4842017-09-28 08:42:16 -0700255 "boot_os=y\0" \
Tom Rini43ede0b2017-10-22 17:55:07 -0400256 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800257 BOOTENV \
258 "boot_scripts=ls1043ardb_boot.scr\0" \
Sumit Garg76bbf1c2017-06-05 23:51:51 +0530259 "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800260 "scan_dev_for_boot_part=" \
261 "part list ${devtype} ${devnum} devplist; " \
262 "env exists devplist || setenv devplist 1; " \
263 "for distro_bootpart in ${devplist}; do " \
264 "if fstype ${devtype} " \
265 "${devnum}:${distro_bootpart} " \
266 "bootfstype; then " \
267 "run scan_dev_for_boot; " \
268 "fi; " \
269 "done\0" \
Sumit Garg76bbf1c2017-06-05 23:51:51 +0530270 "scan_dev_for_boot=" \
271 "echo Scanning ${devtype} " \
272 "${devnum}:${distro_bootpart}...; " \
273 "for prefix in ${boot_prefixes}; do " \
274 "run scan_dev_for_scripts; " \
275 "done;\0" \
276 "boot_a_script=" \
277 "load ${devtype} ${devnum}:${distro_bootpart} " \
278 "${scriptaddr} ${prefix}${script}; " \
279 "env exists secureboot && load ${devtype} " \
280 "${devnum}:${distro_bootpart} " \
281 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
282 "&& esbc_validate ${scripthdraddr};" \
283 "source ${scriptaddr}\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800284 "qspi_bootcmd=echo Trying load from qspi..;" \
285 "sf probe && sf read $load_addr " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530286 "$kernel_addr $kernel_size; env exists secureboot " \
287 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
288 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
289 "bootm $load_addr#$board\0" \
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800290 "nor_bootcmd=echo Trying load from nor..;" \
291 "cp.b $kernel_addr $load_addr " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530292 "$kernel_size; env exists secureboot " \
293 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \
294 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
295 "bootm $load_addr#$board\0" \
Shengzhou Liu1c8263d2017-11-09 17:57:55 +0800296 "sd_bootcmd=echo Trying load from SD ..;" \
297 "mmcinfo; mmc read $load_addr " \
298 "$kernel_addr_sd $kernel_size_sd && " \
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530299 "env exists secureboot && mmc read $kernelheader_addr_r " \
300 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
301 " && esbc_validate ${kernelheader_addr_r};" \
Shengzhou Liu1c8263d2017-11-09 17:57:55 +0800302 "bootm $load_addr#$board\0"
303
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800304
305#undef CONFIG_BOOTCOMMAND
306#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530307#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
308 "env exists secureboot && esbc_halt;"
Shengzhou Liu1c8263d2017-11-09 17:57:55 +0800309#elif defined(CONFIG_SD_BOOT)
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530310#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
311 "env exists secureboot && esbc_halt;"
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800312#else
Vinitha Pillai-B572239b457cc2017-11-22 10:38:35 +0530313#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
314 "env exists secureboot && esbc_halt;"
Shengzhou Liu5ba909f2017-06-08 15:59:48 +0800315#endif
Sumit Garg4139b172017-03-30 09:52:38 +0530316#endif
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800317
318/* Monitor Command Prompt */
319#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
Sumit Garg4139b172017-03-30 09:52:38 +0530320
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800321#define CONFIG_SYS_MAXARGS 64 /* max command args */
322
323#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
324
Simon Glass457e51c2017-05-17 08:23:10 -0600325#include <asm/arch/soc.h>
326
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800327#endif /* __LS1043A_COMMON_H */