blob: 5041eaf7d3099691cb353a93e9fb24f2a5d030f4 [file] [log] [blame]
Tapani Utriainen550e3752013-12-04 09:27:33 +01001/*
2 * Maintainer :
3 * Tapani Utriainen <linuxfae@technexion.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7#include <common.h>
8#include <netdev.h>
9#include <twl4030.h>
10#include <asm/io.h>
11#include <asm/arch/mmc_host_def.h>
12#include <asm/arch/mem.h>
13#include <asm/arch/mux.h>
14#include <asm/arch/sys_proto.h>
15#include <asm/arch/gpio.h>
16#include <asm/gpio.h>
17#include <asm/mach-types.h>
18
19#include <usb.h>
20#include <asm/ehci-omap.h>
21
22#include "tao3530.h"
23
24DECLARE_GLOBAL_DATA_PTR;
25
26int tao3530_revision(void)
27{
28 int ret = 0;
29
30 /* char *label argument is unused in gpio_request() */
31 ret = gpio_request(65, "");
32 if (ret) {
33 puts("Error: GPIO 65 not available\n");
34 goto out;
35 }
36 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4));
37
38 ret = gpio_request(1, "");
39 if (ret) {
40 puts("Error: GPIO 1 not available\n");
41 goto out2;
42 }
43 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M4));
44
45 ret = gpio_direction_input(65);
46 if (ret) {
47 puts("Error: GPIO 65 not available for input\n");
48 goto out3;
49 }
50
51 ret = gpio_direction_input(1);
52 if (ret) {
53 puts("Error: GPIO 1 not available for input\n");
54 goto out3;
55 }
56
57 ret = gpio_get_value(65) << 1 | gpio_get_value(1);
58
59out3:
60 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M0));
61 gpio_free(1);
62out2:
63 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0));
64 gpio_free(65);
65out:
66
67 return ret;
68}
69
Stefan Roesea9f52492013-12-04 09:27:34 +010070#ifdef CONFIG_SPL_BUILD
71/*
72 * Routine: get_board_mem_timings
73 * Description: If we use SPL then there is no x-loader nor config header
74 * so we have to setup the DDR timings ourself on both banks.
75 */
76void get_board_mem_timings(struct board_sdrc_timings *timings)
77{
78 if (tao3530_revision() < 3) {
79 /* 256MB / Bank */
80 timings->mcfg = MCFG(256 << 20, 14); /* RAS-width 14 */
81 timings->ctrla = HYNIX_V_ACTIMA_165;
82 timings->ctrlb = HYNIX_V_ACTIMB_165;
83 } else {
84 /* 128MB / Bank */
85 timings->mcfg = MCFG(128 << 20, 13); /* RAS-width 13 */
86 timings->ctrla = MICRON_V_ACTIMA_165;
87 timings->ctrlb = MICRON_V_ACTIMB_165;
88 }
89
90 timings->mr = MICRON_V_MR_165;
91 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
92}
93#endif
94
Tapani Utriainen550e3752013-12-04 09:27:33 +010095/*
96 * Routine: board_init
97 * Description: Early hardware init.
98 */
99int board_init(void)
100{
101 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
102 /* board id for Linux */
103 gd->bd->bi_arch_number = MACH_TYPE_OMAP3_TAO3530;
104 /* boot param addr */
105 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
106
107 return 0;
108}
109
110/*
111 * Routine: misc_init_r
112 * Description: Configure board specific parts
113 */
114int misc_init_r(void)
115{
116 struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
117 struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
118
119 twl4030_power_init();
120 twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
121
122 /* Configure GPIOs to output */
123 /* GPIO23 */
124 writel(~(GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
125 writel(~(GPIO31 | GPIO30 | GPIO22 | GPIO21 |
126 GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
127
128 /* Set GPIOs */
129 writel(GPIO10 | GPIO8 | GPIO2 | GPIO1,
130 &gpio6_base->setdataout);
131 writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
132 GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
133
Stefan Roesefcd9adc2013-12-04 09:27:36 +0100134 switch (tao3530_revision()) {
135 case 0:
136 puts("TAO-3530 REV Reserve 1\n");
137 break;
138 case 1:
139 puts("TAO-3530 REV Reserve 2\n");
140 break;
141 case 2:
142 puts("TAO-3530 REV Cx\n");
143 break;
144 case 3:
145 puts("TAO-3530 REV Ax/Bx\n");
146 break;
147 default:
148 puts("Unknown board revision\n");
149 }
150
Tapani Utriainen550e3752013-12-04 09:27:33 +0100151 dieid_num_r();
152
Tapani Utriainen550e3752013-12-04 09:27:33 +0100153 return 0;
154}
155
156/*
157 * Routine: set_muxconf_regs
158 * Description: Setting up the configuration Mux registers specific to the
159 * hardware. Many pins need to be moved from protect to primary
160 * mode.
161 */
162void set_muxconf_regs(void)
163{
164 MUX_TAO3530();
165}
166
Stefan Roesea9f52492013-12-04 09:27:34 +0100167#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
Tapani Utriainen550e3752013-12-04 09:27:33 +0100168int board_mmc_init(bd_t *bis)
169{
170 omap_mmc_init(0, 0, 0, -1, -1);
171
172 return 0;
173}
174#endif
175
176#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
177/* Call usb_stop() before starting the kernel */
178void show_boot_progress(int val)
179{
180 if (val == BOOTSTAGE_ID_RUN_OS)
181 usb_stop();
182}
183
184static struct omap_usbhs_board_data usbhs_bdata = {
185 .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
186 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
187 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
188};
189
190int ehci_hcd_init(int index, enum usb_init_type init,
191 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
192{
193 return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
194}
195
196int ehci_hcd_stop(int index)
197{
198 return omap_ehci_hcd_stop();
199}
200#endif /* CONFIG_USB_EHCI */