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wdenk024a26b2002-08-21 21:35:08 +00001/*
2 * (C) Copyright 2002
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk024a26b2002-08-21 21:35:08 +00006 */
7
Wolfgang Denk53677ef2008-05-20 16:00:29 +02008#include <linux/types.h> /* for ulong typedef */
wdenk024a26b2002-08-21 21:35:08 +00009
10#ifndef _FPGA_H_
11#define _FPGA_H_
12
13#ifndef CONFIG_MAX_FPGA_DEVICES
14#define CONFIG_MAX_FPGA_DEVICES 5
15#endif
16
wdenk024a26b2002-08-21 21:35:08 +000017/* fpga_xxxx function return value definitions */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020018#define FPGA_SUCCESS 0
19#define FPGA_FAIL -1
wdenk024a26b2002-08-21 21:35:08 +000020
21/* device numbers must be non-negative */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020022#define FPGA_INVALID_DEVICE -1
wdenk024a26b2002-08-21 21:35:08 +000023
24/* root data type defintions */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020025typedef enum { /* typedef fpga_type */
26 fpga_min_type, /* range check value */
27 fpga_xilinx, /* Xilinx Family) */
28 fpga_altera, /* unimplemented */
Stefano Babic3b8ac462010-06-29 11:47:48 +020029 fpga_lattice, /* Lattice family */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020030 fpga_undefined /* invalid range check value */
31} fpga_type; /* end, typedef fpga_type */
wdenk024a26b2002-08-21 21:35:08 +000032
Wolfgang Denk53677ef2008-05-20 16:00:29 +020033typedef struct { /* typedef fpga_desc */
34 fpga_type devtype; /* switch value to select sub-functions */
35 void *devdesc; /* real device descriptor */
36} fpga_desc; /* end, typedef fpga_desc */
wdenk024a26b2002-08-21 21:35:08 +000037
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053038typedef struct { /* typedef fpga_desc */
39 unsigned int blocksize;
40 char *interface;
41 char *dev_part;
42 char *filename;
43 int fstype;
44} fpga_fs_info;
wdenk024a26b2002-08-21 21:35:08 +000045
Michal Simek7a78bd22014-05-02 14:09:30 +020046typedef enum {
47 BIT_FULL = 0,
Michal Simek67193862014-05-02 13:43:39 +020048 BIT_PARTIAL,
Siva Durga Prasad Paladuguddbcf8f2015-12-09 18:46:42 +053049 BIT_NONE = 0xFF,
Michal Simek7a78bd22014-05-02 14:09:30 +020050} bitstream_type;
51
wdenk024a26b2002-08-21 21:35:08 +000052/* root function definitions */
Michal Simek65835052015-01-14 09:59:00 +010053void fpga_init(void);
54int fpga_add(fpga_type devtype, void *desc);
55int fpga_count(void);
Michal Simekebd322d2015-01-13 16:09:53 +010056const fpga_desc *const fpga_get_desc(int devnum);
Goldschmidt Simon8b93a922017-11-10 14:17:41 +000057int fpga_is_partial_data(int devnum, size_t img_len);
Michal Simek65835052015-01-14 09:59:00 +010058int fpga_load(int devnum, const void *buf, size_t bsize,
59 bitstream_type bstype);
60int fpga_fsload(int devnum, const void *buf, size_t size,
61 fpga_fs_info *fpga_fsinfo);
62int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
63 bitstream_type bstype);
64int fpga_dump(int devnum, const void *buf, size_t bsize);
65int fpga_info(int devnum);
66const fpga_desc *const fpga_validate(int devnum, const void *buf,
67 size_t bsize, char *fn);
wdenk024a26b2002-08-21 21:35:08 +000068
69#endif /* _FPGA_H_ */