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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / fd358121bdb809d3896f55853567769c14a80e96 / . / drivers / pinctrl / nuvoton / pinctrl-npcm7xx.c
blob: 92513822e70c6e829522781d9a451f20501256ee [file] [log] [blame]
Jim Liuf49d6162022-05-17 16:30:32 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2020 Nuvoton Technology Corp.
4 * Author: Joseph Liu <kwliu@nuvoton.com>
5 * Author: Tomer Maimon <tomer.maimon@nuvoton.com>
6 */
7
8#include <dm.h>
9#include <errno.h>
10#include <regmap.h>
11#include <syscon.h>
12#include <asm/io.h>
13#include <dm/device_compat.h>
14#include <dm/pinctrl.h>
15
16/* GCR registers */
17#define NPCM7XX_GCR_PDID 0x00
18#define NPCM7XX_GCR_MFSEL1 0x0C
19#define NPCM7XX_GCR_MFSEL2 0x10
20#define NPCM7XX_GCR_MFSEL3 0x64
21#define NPCM7XX_GCR_MFSEL4 0xb0
22#define NPCM7XX_GCR_CPCTL 0xD0
23#define NPCM7XX_GCR_CP2BST 0xD4
24#define NPCM7XX_GCR_B2CPNT 0xD8
25#define NPCM7XX_GCR_I2CSEGSEL 0xE0
26#define NPCM7XX_GCR_I2CSEGCTL 0xE4
27#define NPCM7XX_GCR_INTCR2 0x60
28#define NPCM7XX_GCR_SRCNT 0x68
29#define NPCM7XX_GCR_RESSR 0x6C
30#define NPCM7XX_GCR_FLOCKR1 0x74
31#define NPCM7XX_GCR_DSCNT 0x78
32
33#define SRCNT_ESPI BIT(3)
34
35/* reset registers */
36#define NPCM7XX_RST_WD0RCR 0x38
37#define NPCM7XX_RST_WD1RCR 0x3C
38#define NPCM7XX_RST_WD2RCR 0x40
39#define NPCM7XX_RST_SWRSTC1 0x44
40#define NPCM7XX_RST_SWRSTC2 0x48
41#define NPCM7XX_RST_SWRSTC3 0x4C
42#define NPCM7XX_RST_SWRSTC4 0x50
43#define NPCM7XX_RST_CORSTC 0x5C
44
45#define PORST BIT(31)
46#define CORST BIT(30)
47#define WD0RST BIT(29)
48#define WD1RST BIT(24)
49#define WD2RST BIT(23)
Jim Liu7ee1c4d2022-12-20 16:49:31 +0800[diff] [blame]50#define SWRST1 BIT(28)
51#define SWRST2 BIT(27)
52#define SWRST3 BIT(26)
53#define SW4RST BIT(25)
Jim Liuf49d6162022-05-17 16:30:32 +0800[diff] [blame]54
55#define GPIOX_MODULE_RESET 16
56#define CA9C_RESET BIT(0)
57
58/* GPIO registers */
59#define NPCM7XX_GP_N_TLOCK1 0x00
60#define NPCM7XX_GP_N_DIN 0x04 /* Data IN */
61#define NPCM7XX_GP_N_POL 0x08 /* Polarity */
62#define NPCM7XX_GP_N_DOUT 0x0c /* Data OUT */
63#define NPCM7XX_GP_N_OE 0x10 /* Output Enable */
64#define NPCM7XX_GP_N_OTYP 0x14
65#define NPCM7XX_GP_N_MP 0x18
66#define NPCM7XX_GP_N_PU 0x1c /* Pull-up */
67#define NPCM7XX_GP_N_PD 0x20 /* Pull-down */
68#define NPCM7XX_GP_N_DBNC 0x24 /* Debounce */
69#define NPCM7XX_GP_N_EVTYP 0x28 /* Event Type */
70#define NPCM7XX_GP_N_EVBE 0x2c /* Event Both Edge */
71#define NPCM7XX_GP_N_OBL0 0x30
72#define NPCM7XX_GP_N_OBL1 0x34
73#define NPCM7XX_GP_N_OBL2 0x38
74#define NPCM7XX_GP_N_OBL3 0x3c
75#define NPCM7XX_GP_N_EVEN 0x40 /* Event Enable */
76#define NPCM7XX_GP_N_EVENS 0x44 /* Event Set (enable) */
77#define NPCM7XX_GP_N_EVENC 0x48 /* Event Clear (disable) */
78#define NPCM7XX_GP_N_EVST 0x4c /* Event Status */
79#define NPCM7XX_GP_N_SPLCK 0x50
80#define NPCM7XX_GP_N_MPLCK 0x54
81#define NPCM7XX_GP_N_IEM 0x58 /* Input Enable */
82#define NPCM7XX_GP_N_OSRC 0x5c
83#define NPCM7XX_GP_N_ODSC 0x60
84#define NPCM7XX_GP_N_DOS 0x68 /* Data OUT Set */
85#define NPCM7XX_GP_N_DOC 0x6c /* Data OUT Clear */
86#define NPCM7XX_GP_N_OES 0x70 /* Output Enable Set */
87#define NPCM7XX_GP_N_OEC 0x74 /* Output Enable Clear */
88#define NPCM7XX_GP_N_TLOCK2 0x7c
89
90#define NPCM7XX_GPIO_BANK_OFFSET 0x1000
91#define NPCM7XX_GPIO_PER_BITS 32
92#define NPCM7XX_GPIO_PER_BANK 32
93#define NPCM7XX_GPIO_BANK_NUM 8
94#define NPCM7XX_GCR_NONE 0
95
96/* pinmux handing in the pinctrl driver*/
97static const int smb0_pins[] = { 115, 114 };
98static const int smb0b_pins[] = { 195, 194 };
99static const int smb0c_pins[] = { 202, 196 };
100static const int smb0d_pins[] = { 198, 199 };
101static const int smb0den_pins[] = { 197 };
102
103static const int smb1_pins[] = { 117, 116 };
104static const int smb1b_pins[] = { 126, 127 };
105static const int smb1c_pins[] = { 124, 125 };
106static const int smb1d_pins[] = { 4, 5 };
107
108static const int smb2_pins[] = { 119, 118 };
109static const int smb2b_pins[] = { 122, 123 };
110static const int smb2c_pins[] = { 120, 121 };
111static const int smb2d_pins[] = { 6, 7 };
112
113static const int smb3_pins[] = { 30, 31 };
114static const int smb3b_pins[] = { 39, 40 };
115static const int smb3c_pins[] = { 37, 38 };
116static const int smb3d_pins[] = { 59, 60 };
117
118static const int smb4_pins[] = { 28, 29 };
119static const int smb4b_pins[] = { 18, 19 };
120static const int smb4c_pins[] = { 20, 21 };
121static const int smb4d_pins[] = { 22, 23 };
122static const int smb4den_pins[] = { 17 };
123
124static const int smb5_pins[] = { 26, 27 };
125static const int smb5b_pins[] = { 13, 12 };
126static const int smb5c_pins[] = { 15, 14 };
127static const int smb5d_pins[] = { 94, 93 };
128static const int ga20kbc_pins[] = { 94, 93 };
129
130static const int smb6_pins[] = { 172, 171 };
131static const int smb7_pins[] = { 174, 173 };
132static const int smb8_pins[] = { 129, 128 };
133static const int smb9_pins[] = { 131, 130 };
134static const int smb10_pins[] = { 133, 132 };
135static const int smb11_pins[] = { 135, 134 };
136static const int smb12_pins[] = { 221, 220 };
137static const int smb13_pins[] = { 223, 222 };
138static const int smb14_pins[] = { 22, 23 };
139static const int smb15_pins[] = { 20, 21 };
140
141static const int fanin0_pins[] = { 64 };
142static const int fanin1_pins[] = { 65 };
143static const int fanin2_pins[] = { 66 };
144static const int fanin3_pins[] = { 67 };
145static const int fanin4_pins[] = { 68 };
146static const int fanin5_pins[] = { 69 };
147static const int fanin6_pins[] = { 70 };
148static const int fanin7_pins[] = { 71 };
149static const int fanin8_pins[] = { 72 };
150static const int fanin9_pins[] = { 73 };
151static const int fanin10_pins[] = { 74 };
152static const int fanin11_pins[] = { 75 };
153static const int fanin12_pins[] = { 76 };
154static const int fanin13_pins[] = { 77 };
155static const int fanin14_pins[] = { 78 };
156static const int fanin15_pins[] = { 79 };
157static const int faninx_pins[] = { 175, 176, 177, 203 };
158
159static const int pwm0_pins[] = { 80 };
160static const int pwm1_pins[] = { 81 };
161static const int pwm2_pins[] = { 82 };
162static const int pwm3_pins[] = { 83 };
163static const int pwm4_pins[] = { 144 };
164static const int pwm5_pins[] = { 145 };
165static const int pwm6_pins[] = { 146 };
166static const int pwm7_pins[] = { 147 };
167
168static const int uart1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 };
169static const int uart2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 };
170
171/* RGMII 1 pin group */
172static const int rg1_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103, 104, 105,
173 106, 107 };
174/* RGMII 1 MD interface pin group */
175static const int rg1mdio_pins[] = { 108, 109 };
176
177/* RGMII 2 pin group */
178static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
179 213, 214, 215 };
180/* RGMII 2 MD interface pin group */
181static const int rg2mdio_pins[] = { 216, 217 };
182
183static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
184 213, 214, 215, 216, 217 };
185/* Serial I/O Expander 1 */
186static const int iox1_pins[] = { 0, 1, 2, 3 };
187/* Serial I/O Expander 2 */
188static const int iox2_pins[] = { 4, 5, 6, 7 };
189/* Host Serial I/O Expander 2 */
190static const int ioxh_pins[] = { 10, 11, 24, 25 };
191
192static const int mmc_pins[] = { 152, 154, 156, 157, 158, 159 };
193static const int mmcwp_pins[] = { 153 };
194static const int mmccd_pins[] = { 155 };
195static const int mmcrst_pins[] = { 155 };
196static const int mmc8_pins[] = { 148, 149, 150, 151 };
197
198/* RMII 1 pin groups */
199static const int r1_pins[] = { 178, 179, 180, 181, 182, 193, 201 };
200static const int r1err_pins[] = { 56 };
201static const int r1md_pins[] = { 57, 58 };
202
203/* RMII 2 pin groups */
204static const int r2_pins[] = { 84, 85, 86, 87, 88, 89, 200 };
205static const int r2err_pins[] = { 90 };
206static const int r2md_pins[] = { 91, 92 };
207
208static const int sd1_pins[] = { 136, 137, 138, 139, 140, 141, 142, 143 };
209static const int sd1pwr_pins[] = { 143 };
210
211static const int wdog1_pins[] = { 218 };
212static const int wdog2_pins[] = { 219 };
213
214/* BMC serial port 0 */
215static const int bmcuart0a_pins[] = { 41, 42 };
216static const int bmcuart0b_pins[] = { 48, 49 };
217
218static const int bmcuart1_pins[] = { 43, 44, 62, 63 };
219
220/* System Control Interrupt and Power Management Event pin group */
221static const int scipme_pins[] = { 169 };
222/* System Management Interrupt pin group */
223static const int sci_pins[] = { 170 };
224/* Serial Interrupt Line pin group */
225static const int serirq_pins[] = { 162 };
226
227static const int clkout_pins[] = { 160 };
228static const int clkreq_pins[] = { 231 };
229
230static const int jtag2_pins[] = { 43, 44, 45, 46, 47 };
231/* Graphics SPI Clock pin group */
232static const int gspi_pins[] = { 12, 13, 14, 15 };
233
234static const int spix_pins[] = { 224, 225, 226, 227, 229, 230 };
235static const int spixcs1_pins[] = { 228 };
236
237static const int pspi1_pins[] = { 175, 176, 177 };
238static const int pspi2_pins[] = { 17, 18, 19 };
239
240static const int spi0cs1_pins[] = { 32 };
241
242static const int spi3_pins[] = { 183, 184, 185, 186 };
243static const int spi3cs1_pins[] = { 187 };
244static const int spi3quad_pins[] = { 188, 189 };
245static const int spi3cs2_pins[] = { 188 };
246static const int spi3cs3_pins[] = { 189 };
247
248static const int ddc_pins[] = { 204, 205, 206, 207 };
249
250static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 };
251static const int lpcclk_pins[] = { 168 };
252static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 };
253
254static const int lkgpo0_pins[] = { 16 };
255static const int lkgpo1_pins[] = { 8 };
256static const int lkgpo2_pins[] = { 9 };
257
258static const int nprd_smi_pins[] = { 190 };
259
260static const int hgpio0_pins[] = { 20 };
261static const int hgpio1_pins[] = { 21 };
262static const int hgpio2_pins[] = { 22 };
263static const int hgpio3_pins[] = { 23 };
264static const int hgpio4_pins[] = { 24 };
265static const int hgpio5_pins[] = { 25 };
266static const int hgpio6_pins[] = { 59 };
267static const int hgpio7_pins[] = { 60 };
268
269/*
270 * pin: name, number
271 * group: name, npins, pins
272 * function: name, ngroups, groups
273 */
274struct npcm7xx_group {
275 const char *name;
276 const int *pins;
277 int npins;
278};
279
280#define NPCM7XX_GRPS \
281 NPCM7XX_GRP(smb0), \
282 NPCM7XX_GRP(smb0b), \
283 NPCM7XX_GRP(smb0c), \
284 NPCM7XX_GRP(smb0d), \
285 NPCM7XX_GRP(smb0den), \
286 NPCM7XX_GRP(smb1), \
287 NPCM7XX_GRP(smb1b), \
288 NPCM7XX_GRP(smb1c), \
289 NPCM7XX_GRP(smb1d), \
290 NPCM7XX_GRP(smb2), \
291 NPCM7XX_GRP(smb2b), \
292 NPCM7XX_GRP(smb2c), \
293 NPCM7XX_GRP(smb2d), \
294 NPCM7XX_GRP(smb3), \
295 NPCM7XX_GRP(smb3b), \
296 NPCM7XX_GRP(smb3c), \
297 NPCM7XX_GRP(smb3d), \
298 NPCM7XX_GRP(smb4), \
299 NPCM7XX_GRP(smb4b), \
300 NPCM7XX_GRP(smb4c), \
301 NPCM7XX_GRP(smb4d), \
302 NPCM7XX_GRP(smb4den), \
303 NPCM7XX_GRP(smb5), \
304 NPCM7XX_GRP(smb5b), \
305 NPCM7XX_GRP(smb5c), \
306 NPCM7XX_GRP(smb5d), \
307 NPCM7XX_GRP(ga20kbc), \
308 NPCM7XX_GRP(smb6), \
309 NPCM7XX_GRP(smb7), \
310 NPCM7XX_GRP(smb8), \
311 NPCM7XX_GRP(smb9), \
312 NPCM7XX_GRP(smb10), \
313 NPCM7XX_GRP(smb11), \
314 NPCM7XX_GRP(smb12), \
315 NPCM7XX_GRP(smb13), \
316 NPCM7XX_GRP(smb14), \
317 NPCM7XX_GRP(smb15), \
318 NPCM7XX_GRP(fanin0), \
319 NPCM7XX_GRP(fanin1), \
320 NPCM7XX_GRP(fanin2), \
321 NPCM7XX_GRP(fanin3), \
322 NPCM7XX_GRP(fanin4), \
323 NPCM7XX_GRP(fanin5), \
324 NPCM7XX_GRP(fanin6), \
325 NPCM7XX_GRP(fanin7), \
326 NPCM7XX_GRP(fanin8), \
327 NPCM7XX_GRP(fanin9), \
328 NPCM7XX_GRP(fanin10), \
329 NPCM7XX_GRP(fanin11), \
330 NPCM7XX_GRP(fanin12), \
331 NPCM7XX_GRP(fanin13), \
332 NPCM7XX_GRP(fanin14), \
333 NPCM7XX_GRP(fanin15), \
334 NPCM7XX_GRP(faninx), \
335 NPCM7XX_GRP(pwm0), \
336 NPCM7XX_GRP(pwm1), \
337 NPCM7XX_GRP(pwm2), \
338 NPCM7XX_GRP(pwm3), \
339 NPCM7XX_GRP(pwm4), \
340 NPCM7XX_GRP(pwm5), \
341 NPCM7XX_GRP(pwm6), \
342 NPCM7XX_GRP(pwm7), \
343 NPCM7XX_GRP(rg1), \
344 NPCM7XX_GRP(rg1mdio), \
345 NPCM7XX_GRP(rg2), \
346 NPCM7XX_GRP(rg2mdio), \
347 NPCM7XX_GRP(ddr), \
348 NPCM7XX_GRP(uart1), \
349 NPCM7XX_GRP(uart2), \
350 NPCM7XX_GRP(bmcuart0a), \
351 NPCM7XX_GRP(bmcuart0b), \
352 NPCM7XX_GRP(bmcuart1), \
353 NPCM7XX_GRP(iox1), \
354 NPCM7XX_GRP(iox2), \
355 NPCM7XX_GRP(ioxh), \
356 NPCM7XX_GRP(gspi), \
357 NPCM7XX_GRP(mmc), \
358 NPCM7XX_GRP(mmcwp), \
359 NPCM7XX_GRP(mmccd), \
360 NPCM7XX_GRP(mmcrst), \
361 NPCM7XX_GRP(mmc8), \
362 NPCM7XX_GRP(r1), \
363 NPCM7XX_GRP(r1err), \
364 NPCM7XX_GRP(r1md), \
365 NPCM7XX_GRP(r2), \
366 NPCM7XX_GRP(r2err), \
367 NPCM7XX_GRP(r2md), \
368 NPCM7XX_GRP(sd1), \
369 NPCM7XX_GRP(sd1pwr), \
370 NPCM7XX_GRP(wdog1), \
371 NPCM7XX_GRP(wdog2), \
372 NPCM7XX_GRP(scipme), \
373 NPCM7XX_GRP(sci), \
374 NPCM7XX_GRP(serirq), \
375 NPCM7XX_GRP(jtag2), \
376 NPCM7XX_GRP(spix), \
377 NPCM7XX_GRP(spixcs1), \
378 NPCM7XX_GRP(pspi1), \
379 NPCM7XX_GRP(pspi2), \
380 NPCM7XX_GRP(ddc), \
381 NPCM7XX_GRP(clkreq), \
382 NPCM7XX_GRP(clkout), \
383 NPCM7XX_GRP(spi3), \
384 NPCM7XX_GRP(spi3cs1), \
385 NPCM7XX_GRP(spi3quad), \
386 NPCM7XX_GRP(spi3cs2), \
387 NPCM7XX_GRP(spi3cs3), \
388 NPCM7XX_GRP(spi0cs1), \
389 NPCM7XX_GRP(lpc), \
390 NPCM7XX_GRP(lpcclk), \
391 NPCM7XX_GRP(espi), \
392 NPCM7XX_GRP(lkgpo0), \
393 NPCM7XX_GRP(lkgpo1), \
394 NPCM7XX_GRP(lkgpo2), \
395 NPCM7XX_GRP(nprd_smi), \
396 NPCM7XX_GRP(hgpio0), \
397 NPCM7XX_GRP(hgpio1), \
398 NPCM7XX_GRP(hgpio2), \
399 NPCM7XX_GRP(hgpio3), \
400 NPCM7XX_GRP(hgpio4), \
401 NPCM7XX_GRP(hgpio5), \
402 NPCM7XX_GRP(hgpio6), \
403 NPCM7XX_GRP(hgpio7), \
404 \
405
406enum {
407#define NPCM7XX_GRP(x) fn_ ## x
408 NPCM7XX_GRPS
409 /* add placeholder for none/gpio */
410 NPCM7XX_GRP(none),
411 NPCM7XX_GRP(gpio),
412#undef NPCM7XX_GRP
413};
414
415static struct npcm7xx_group npcm7xx_groups[] = {
416#define NPCM7XX_GRP(x) { .name = #x, .pins = x ## _pins, \
417 .npins = ARRAY_SIZE(x ## _pins) }
418 NPCM7XX_GRPS
419#undef NPCM7XX_GRP
420};
421
422#define NPCM7XX_SFUNC(a) NPCM7XX_FUNC(a, #a)
423#define NPCM7XX_FUNC(a, b...) static const char *a ## _grp[] = { b }
424#define NPCM7XX_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \
425 .groups = nm ## _grp }
426struct npcm7xx_func {
427 const char *name;
428 const unsigned int ngroups;
429 const char *const *groups;
430};
431
432NPCM7XX_SFUNC(smb0);
433NPCM7XX_SFUNC(smb0b);
434NPCM7XX_SFUNC(smb0c);
435NPCM7XX_SFUNC(smb0d);
436NPCM7XX_SFUNC(smb0den);
437NPCM7XX_SFUNC(smb1);
438NPCM7XX_SFUNC(smb1b);
439NPCM7XX_SFUNC(smb1c);
440NPCM7XX_SFUNC(smb1d);
441NPCM7XX_SFUNC(smb2);
442NPCM7XX_SFUNC(smb2b);
443NPCM7XX_SFUNC(smb2c);
444NPCM7XX_SFUNC(smb2d);
445NPCM7XX_SFUNC(smb3);
446NPCM7XX_SFUNC(smb3b);
447NPCM7XX_SFUNC(smb3c);
448NPCM7XX_SFUNC(smb3d);
449NPCM7XX_SFUNC(smb4);
450NPCM7XX_SFUNC(smb4b);
451NPCM7XX_SFUNC(smb4c);
452NPCM7XX_SFUNC(smb4d);
453NPCM7XX_SFUNC(smb4den);
454NPCM7XX_SFUNC(smb5);
455NPCM7XX_SFUNC(smb5b);
456NPCM7XX_SFUNC(smb5c);
457NPCM7XX_SFUNC(smb5d);
458NPCM7XX_SFUNC(ga20kbc);
459NPCM7XX_SFUNC(smb6);
460NPCM7XX_SFUNC(smb7);
461NPCM7XX_SFUNC(smb8);
462NPCM7XX_SFUNC(smb9);
463NPCM7XX_SFUNC(smb10);
464NPCM7XX_SFUNC(smb11);
465NPCM7XX_SFUNC(smb12);
466NPCM7XX_SFUNC(smb13);
467NPCM7XX_SFUNC(smb14);
468NPCM7XX_SFUNC(smb15);
469NPCM7XX_SFUNC(fanin0);
470NPCM7XX_SFUNC(fanin1);
471NPCM7XX_SFUNC(fanin2);
472NPCM7XX_SFUNC(fanin3);
473NPCM7XX_SFUNC(fanin4);
474NPCM7XX_SFUNC(fanin5);
475NPCM7XX_SFUNC(fanin6);
476NPCM7XX_SFUNC(fanin7);
477NPCM7XX_SFUNC(fanin8);
478NPCM7XX_SFUNC(fanin9);
479NPCM7XX_SFUNC(fanin10);
480NPCM7XX_SFUNC(fanin11);
481NPCM7XX_SFUNC(fanin12);
482NPCM7XX_SFUNC(fanin13);
483NPCM7XX_SFUNC(fanin14);
484NPCM7XX_SFUNC(fanin15);
485NPCM7XX_SFUNC(faninx);
486NPCM7XX_SFUNC(pwm0);
487NPCM7XX_SFUNC(pwm1);
488NPCM7XX_SFUNC(pwm2);
489NPCM7XX_SFUNC(pwm3);
490NPCM7XX_SFUNC(pwm4);
491NPCM7XX_SFUNC(pwm5);
492NPCM7XX_SFUNC(pwm6);
493NPCM7XX_SFUNC(pwm7);
494NPCM7XX_SFUNC(rg1);
495NPCM7XX_SFUNC(rg1mdio);
496NPCM7XX_SFUNC(rg2);
497NPCM7XX_SFUNC(rg2mdio);
498NPCM7XX_SFUNC(ddr);
499NPCM7XX_SFUNC(uart1);
500NPCM7XX_SFUNC(uart2);
501NPCM7XX_SFUNC(bmcuart0a);
502NPCM7XX_SFUNC(bmcuart0b);
503NPCM7XX_SFUNC(bmcuart1);
504NPCM7XX_SFUNC(iox1);
505NPCM7XX_SFUNC(iox2);
506NPCM7XX_SFUNC(ioxh);
507NPCM7XX_SFUNC(gspi);
508NPCM7XX_SFUNC(mmc);
509NPCM7XX_SFUNC(mmcwp);
510NPCM7XX_SFUNC(mmccd);
511NPCM7XX_SFUNC(mmcrst);
512NPCM7XX_SFUNC(mmc8);
513NPCM7XX_SFUNC(r1);
514NPCM7XX_SFUNC(r1err);
515NPCM7XX_SFUNC(r1md);
516NPCM7XX_SFUNC(r2);
517NPCM7XX_SFUNC(r2err);
518NPCM7XX_SFUNC(r2md);
519NPCM7XX_SFUNC(sd1);
520NPCM7XX_SFUNC(sd1pwr);
521NPCM7XX_SFUNC(wdog1);
522NPCM7XX_SFUNC(wdog2);
523NPCM7XX_SFUNC(scipme);
524NPCM7XX_SFUNC(sci);
525NPCM7XX_SFUNC(serirq);
526NPCM7XX_SFUNC(jtag2);
527NPCM7XX_SFUNC(spix);
528NPCM7XX_SFUNC(spixcs1);
529NPCM7XX_SFUNC(pspi1);
530NPCM7XX_SFUNC(pspi2);
531NPCM7XX_SFUNC(ddc);
532NPCM7XX_SFUNC(clkreq);
533NPCM7XX_SFUNC(clkout);
534NPCM7XX_SFUNC(spi3);
535NPCM7XX_SFUNC(spi3cs1);
536NPCM7XX_SFUNC(spi3quad);
537NPCM7XX_SFUNC(spi3cs2);
538NPCM7XX_SFUNC(spi3cs3);
539NPCM7XX_SFUNC(spi0cs1);
540NPCM7XX_SFUNC(lpc);
541NPCM7XX_SFUNC(lpcclk);
542NPCM7XX_SFUNC(espi);
543NPCM7XX_SFUNC(lkgpo0);
544NPCM7XX_SFUNC(lkgpo1);
545NPCM7XX_SFUNC(lkgpo2);
546NPCM7XX_SFUNC(nprd_smi);
547NPCM7XX_SFUNC(hgpio0);
548NPCM7XX_SFUNC(hgpio1);
549NPCM7XX_SFUNC(hgpio2);
550NPCM7XX_SFUNC(hgpio3);
551NPCM7XX_SFUNC(hgpio4);
552NPCM7XX_SFUNC(hgpio5);
553NPCM7XX_SFUNC(hgpio6);
554NPCM7XX_SFUNC(hgpio7);
555
556/* Function names */
557static struct npcm7xx_func npcm7xx_funcs[] = {
558 NPCM7XX_MKFUNC(smb0),
559 NPCM7XX_MKFUNC(smb0b),
560 NPCM7XX_MKFUNC(smb0c),
561 NPCM7XX_MKFUNC(smb0d),
562 NPCM7XX_MKFUNC(smb0den),
563 NPCM7XX_MKFUNC(smb1),
564 NPCM7XX_MKFUNC(smb1b),
565 NPCM7XX_MKFUNC(smb1c),
566 NPCM7XX_MKFUNC(smb1d),
567 NPCM7XX_MKFUNC(smb2),
568 NPCM7XX_MKFUNC(smb2b),
569 NPCM7XX_MKFUNC(smb2c),
570 NPCM7XX_MKFUNC(smb2d),
571 NPCM7XX_MKFUNC(smb3),
572 NPCM7XX_MKFUNC(smb3b),
573 NPCM7XX_MKFUNC(smb3c),
574 NPCM7XX_MKFUNC(smb3d),
575 NPCM7XX_MKFUNC(smb4),
576 NPCM7XX_MKFUNC(smb4b),
577 NPCM7XX_MKFUNC(smb4c),
578 NPCM7XX_MKFUNC(smb4d),
579 NPCM7XX_MKFUNC(smb4den),
580 NPCM7XX_MKFUNC(smb5),
581 NPCM7XX_MKFUNC(smb5b),
582 NPCM7XX_MKFUNC(smb5c),
583 NPCM7XX_MKFUNC(smb5d),
584 NPCM7XX_MKFUNC(ga20kbc),
585 NPCM7XX_MKFUNC(smb6),
586 NPCM7XX_MKFUNC(smb7),
587 NPCM7XX_MKFUNC(smb8),
588 NPCM7XX_MKFUNC(smb9),
589 NPCM7XX_MKFUNC(smb10),
590 NPCM7XX_MKFUNC(smb11),
591 NPCM7XX_MKFUNC(smb12),
592 NPCM7XX_MKFUNC(smb13),
593 NPCM7XX_MKFUNC(smb14),
594 NPCM7XX_MKFUNC(smb15),
595 NPCM7XX_MKFUNC(fanin0),
596 NPCM7XX_MKFUNC(fanin1),
597 NPCM7XX_MKFUNC(fanin2),
598 NPCM7XX_MKFUNC(fanin3),
599 NPCM7XX_MKFUNC(fanin4),
600 NPCM7XX_MKFUNC(fanin5),
601 NPCM7XX_MKFUNC(fanin6),
602 NPCM7XX_MKFUNC(fanin7),
603 NPCM7XX_MKFUNC(fanin8),
604 NPCM7XX_MKFUNC(fanin9),
605 NPCM7XX_MKFUNC(fanin10),
606 NPCM7XX_MKFUNC(fanin11),
607 NPCM7XX_MKFUNC(fanin12),
608 NPCM7XX_MKFUNC(fanin13),
609 NPCM7XX_MKFUNC(fanin14),
610 NPCM7XX_MKFUNC(fanin15),
611 NPCM7XX_MKFUNC(faninx),
612 NPCM7XX_MKFUNC(pwm0),
613 NPCM7XX_MKFUNC(pwm1),
614 NPCM7XX_MKFUNC(pwm2),
615 NPCM7XX_MKFUNC(pwm3),
616 NPCM7XX_MKFUNC(pwm4),
617 NPCM7XX_MKFUNC(pwm5),
618 NPCM7XX_MKFUNC(pwm6),
619 NPCM7XX_MKFUNC(pwm7),
620 NPCM7XX_MKFUNC(rg1),
621 NPCM7XX_MKFUNC(rg1mdio),
622 NPCM7XX_MKFUNC(rg2),
623 NPCM7XX_MKFUNC(rg2mdio),
624 NPCM7XX_MKFUNC(ddr),
625 NPCM7XX_MKFUNC(uart1),
626 NPCM7XX_MKFUNC(uart2),
627 NPCM7XX_MKFUNC(bmcuart0a),
628 NPCM7XX_MKFUNC(bmcuart0b),
629 NPCM7XX_MKFUNC(bmcuart1),
630 NPCM7XX_MKFUNC(iox1),
631 NPCM7XX_MKFUNC(iox2),
632 NPCM7XX_MKFUNC(ioxh),
633 NPCM7XX_MKFUNC(gspi),
634 NPCM7XX_MKFUNC(mmc),
635 NPCM7XX_MKFUNC(mmcwp),
636 NPCM7XX_MKFUNC(mmccd),
637 NPCM7XX_MKFUNC(mmcrst),
638 NPCM7XX_MKFUNC(mmc8),
639 NPCM7XX_MKFUNC(r1),
640 NPCM7XX_MKFUNC(r1err),
641 NPCM7XX_MKFUNC(r1md),
642 NPCM7XX_MKFUNC(r2),
643 NPCM7XX_MKFUNC(r2err),
644 NPCM7XX_MKFUNC(r2md),
645 NPCM7XX_MKFUNC(sd1),
646 NPCM7XX_MKFUNC(sd1pwr),
647 NPCM7XX_MKFUNC(wdog1),
648 NPCM7XX_MKFUNC(wdog2),
649 NPCM7XX_MKFUNC(scipme),
650 NPCM7XX_MKFUNC(sci),
651 NPCM7XX_MKFUNC(serirq),
652 NPCM7XX_MKFUNC(jtag2),
653 NPCM7XX_MKFUNC(spix),
654 NPCM7XX_MKFUNC(spixcs1),
655 NPCM7XX_MKFUNC(pspi1),
656 NPCM7XX_MKFUNC(pspi2),
657 NPCM7XX_MKFUNC(ddc),
658 NPCM7XX_MKFUNC(clkreq),
659 NPCM7XX_MKFUNC(clkout),
660 NPCM7XX_MKFUNC(spi3),
661 NPCM7XX_MKFUNC(spi3cs1),
662 NPCM7XX_MKFUNC(spi3quad),
663 NPCM7XX_MKFUNC(spi3cs2),
664 NPCM7XX_MKFUNC(spi3cs3),
665 NPCM7XX_MKFUNC(spi0cs1),
666 NPCM7XX_MKFUNC(lpc),
667 NPCM7XX_MKFUNC(lpcclk),
668 NPCM7XX_MKFUNC(espi),
669 NPCM7XX_MKFUNC(lkgpo0),
670 NPCM7XX_MKFUNC(lkgpo1),
671 NPCM7XX_MKFUNC(lkgpo2),
672 NPCM7XX_MKFUNC(nprd_smi),
673 NPCM7XX_MKFUNC(hgpio0),
674 NPCM7XX_MKFUNC(hgpio1),
675 NPCM7XX_MKFUNC(hgpio2),
676 NPCM7XX_MKFUNC(hgpio3),
677 NPCM7XX_MKFUNC(hgpio4),
678 NPCM7XX_MKFUNC(hgpio5),
679 NPCM7XX_MKFUNC(hgpio6),
680 NPCM7XX_MKFUNC(hgpio7),
681};
682
683#define NPCM7XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k) \
684 [a] { .fn0 = fn_ ## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \
685 .fn1 = fn_ ## e, .reg1 = NPCM7XX_GCR_ ## f, .bit1 = g, \
686 .fn2 = fn_ ## h, .reg2 = NPCM7XX_GCR_ ## i, .bit2 = j, \
687 .flag = k }
688
689/* Drive strength controlled by NPCM7XX_GP_N_ODSC */
690#define DRIVE_STRENGTH_LO_SHIFT 8
691#define DRIVE_STRENGTH_HI_SHIFT 12
692#define DRIVE_STRENGTH_MASK 0x0000FF00
693
694#define DS(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \
695 ((hi) << DRIVE_STRENGTH_HI_SHIFT))
696#define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & 0xF)
697#define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & 0xF)
698
699#define GPI 0x1 /* Not GPO */
700#define GPO 0x2 /* Not GPI */
701#define SLEW 0x4 /* Has Slew Control, NPCM7XX_GP_N_OSRC */
702#define SLEWLPC 0x8 /* Has Slew Control, SRCNT.3 */
703
704struct npcm7xx_pincfg {
705 int flag;
706 int fn0, reg0, bit0;
707 int fn1, reg1, bit1;
708 int fn2, reg2, bit2;
709};
710
711static const struct npcm7xx_pincfg pincfgs[] = {
712 /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */
713 NPCM7XX_PINCFG(0, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0),
714 NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)),
715 NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)),
716 NPCM7XX_PINCFG(3, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0),
717 NPCM7XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW),
718 NPCM7XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW),
719 NPCM7XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW),
720 NPCM7XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW),
721 NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DS(8, 12)),
722 NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DS(8, 12)),
723 NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)),
724 NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)),
725 NPCM7XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW),
726 NPCM7XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW),
727 NPCM7XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW),
728 NPCM7XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW),
729 NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)),
730 NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DS(8, 12)),
731 NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DS(8, 12)),
732 NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DS(8, 12)),
733 NPCM7XX_PINCFG(20, hgpio0, MFSEL2, 24, smb15, MFSEL3, 8, smb4c, I2CSEGSEL, 15, 0),
734 NPCM7XX_PINCFG(21, hgpio1, MFSEL2, 25, smb15, MFSEL3, 8, smb4c, I2CSEGSEL, 15, 0),
735 NPCM7XX_PINCFG(22, hgpio2, MFSEL2, 26, smb14, MFSEL3, 7, smb4d, I2CSEGSEL, 16, 0),
736 NPCM7XX_PINCFG(23, hgpio3, MFSEL2, 27, smb14, MFSEL3, 7, smb4d, I2CSEGSEL, 16, 0),
737 NPCM7XX_PINCFG(24, hgpio4, MFSEL2, 28, ioxh, MFSEL3, 18, none, NONE, 0, DS(8, 12)),
738 NPCM7XX_PINCFG(25, hgpio5, MFSEL2, 29, ioxh, MFSEL3, 18, none, NONE, 0, DS(8, 12)),
739 NPCM7XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0),
740 NPCM7XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0),
741 NPCM7XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0),
742 NPCM7XX_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0),
743 NPCM7XX_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0),
744 NPCM7XX_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0),
745
746 NPCM7XX_PINCFG(32, spi0cs1, MFSEL1, 3, none, NONE, 0, none, NONE, 0, 0),
747 NPCM7XX_PINCFG(33, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
748 NPCM7XX_PINCFG(34, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW),
749 NPCM7XX_PINCFG(37, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW),
750 NPCM7XX_PINCFG(38, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW),
751 NPCM7XX_PINCFG(39, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW),
752 NPCM7XX_PINCFG(40, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW),
753 NPCM7XX_PINCFG(41, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, 0),
754 NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DS(2, 4) | GPO),
755 NPCM7XX_PINCFG(43, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0),
756 NPCM7XX_PINCFG(44, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0),
757 NPCM7XX_PINCFG(45, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, 0),
758 NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DS(2, 8)),
759 NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DS(2, 8)),
760 NPCM7XX_PINCFG(48, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, GPO),
761 NPCM7XX_PINCFG(49, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, 0),
762 NPCM7XX_PINCFG(50, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
763 NPCM7XX_PINCFG(51, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO),
764 NPCM7XX_PINCFG(52, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
765 NPCM7XX_PINCFG(53, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO),
766 NPCM7XX_PINCFG(54, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
767 NPCM7XX_PINCFG(55, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0),
768 NPCM7XX_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0, none, NONE, 0, 0),
769 NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DS(2, 4)),
770 NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DS(2, 4)),
771 NPCM7XX_PINCFG(59, hgpio6, MFSEL2, 30, smb3d, I2CSEGSEL, 13, none, NONE, 0, 0),
772 NPCM7XX_PINCFG(60, hgpio7, MFSEL2, 31, smb3d, I2CSEGSEL, 13, none, NONE, 0, 0),
773 NPCM7XX_PINCFG(61, uart1, MFSEL1, 10, none, NONE, 0, none, NONE, 0, GPO),
774 NPCM7XX_PINCFG(62, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO),
775 NPCM7XX_PINCFG(63, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO),
776
777 NPCM7XX_PINCFG(64, fanin0, MFSEL2, 0, none, NONE, 0, none, NONE, 0, 0),
778 NPCM7XX_PINCFG(65, fanin1, MFSEL2, 1, none, NONE, 0, none, NONE, 0, 0),
779 NPCM7XX_PINCFG(66, fanin2, MFSEL2, 2, none, NONE, 0, none, NONE, 0, 0),
780 NPCM7XX_PINCFG(67, fanin3, MFSEL2, 3, none, NONE, 0, none, NONE, 0, 0),
781 NPCM7XX_PINCFG(68, fanin4, MFSEL2, 4, none, NONE, 0, none, NONE, 0, 0),
782 NPCM7XX_PINCFG(69, fanin5, MFSEL2, 5, none, NONE, 0, none, NONE, 0, 0),
783 NPCM7XX_PINCFG(70, fanin6, MFSEL2, 6, none, NONE, 0, none, NONE, 0, 0),
784 NPCM7XX_PINCFG(71, fanin7, MFSEL2, 7, none, NONE, 0, none, NONE, 0, 0),
785 NPCM7XX_PINCFG(72, fanin8, MFSEL2, 8, none, NONE, 0, none, NONE, 0, 0),
786 NPCM7XX_PINCFG(73, fanin9, MFSEL2, 9, none, NONE, 0, none, NONE, 0, 0),
787 NPCM7XX_PINCFG(74, fanin10, MFSEL2, 10, none, NONE, 0, none, NONE, 0, 0),
788 NPCM7XX_PINCFG(75, fanin11, MFSEL2, 11, none, NONE, 0, none, NONE, 0, 0),
789 NPCM7XX_PINCFG(76, fanin12, MFSEL2, 12, none, NONE, 0, none, NONE, 0, 0),
790 NPCM7XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, 0),
791 NPCM7XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, 0),
792 NPCM7XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, 0),
793 NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DS(4, 8)),
794 NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DS(4, 8)),
795 NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DS(4, 8)),
796 NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DS(4, 8)),
797 NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
798 NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
799 NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
800 NPCM7XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
801 NPCM7XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
802 NPCM7XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
803 NPCM7XX_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0, none, NONE, 0, 0),
804 NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DS(2, 4)),
805 NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DS(2, 4)),
806 NPCM7XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0),
807 NPCM7XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0),
808 NPCM7XX_PINCFG(95, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0),
809
810 NPCM7XX_PINCFG(96, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
811 NPCM7XX_PINCFG(97, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
812 NPCM7XX_PINCFG(98, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
813 NPCM7XX_PINCFG(99, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
814 NPCM7XX_PINCFG(100, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
815 NPCM7XX_PINCFG(101, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
816 NPCM7XX_PINCFG(102, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
817 NPCM7XX_PINCFG(103, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
818 NPCM7XX_PINCFG(104, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
819 NPCM7XX_PINCFG(105, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
820 NPCM7XX_PINCFG(106, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
821 NPCM7XX_PINCFG(107, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0),
822 NPCM7XX_PINCFG(108, rg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, 0),
823 NPCM7XX_PINCFG(109, rg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, 0),
824 NPCM7XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
825 NPCM7XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
826 NPCM7XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
827 NPCM7XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
828 NPCM7XX_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, 0),
829 NPCM7XX_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, 0),
830 NPCM7XX_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, 0),
831 NPCM7XX_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, 0),
832 NPCM7XX_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, 0),
833 NPCM7XX_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, 0),
834 NPCM7XX_PINCFG(120, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, SLEW),
835 NPCM7XX_PINCFG(121, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, SLEW),
836 NPCM7XX_PINCFG(122, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, SLEW),
837 NPCM7XX_PINCFG(123, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, SLEW),
838 NPCM7XX_PINCFG(124, smb1c, I2CSEGSEL, 6, none, NONE, 0, none, NONE, 0, SLEW),
839 NPCM7XX_PINCFG(125, smb1c, I2CSEGSEL, 6, none, NONE, 0, none, NONE, 0, SLEW),
840 NPCM7XX_PINCFG(126, smb1b, I2CSEGSEL, 5, none, NONE, 0, none, NONE, 0, SLEW),
841 NPCM7XX_PINCFG(127, smb1b, I2CSEGSEL, 5, none, NONE, 0, none, NONE, 0, SLEW),
842
843 NPCM7XX_PINCFG(128, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, 0),
844 NPCM7XX_PINCFG(129, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, 0),
845 NPCM7XX_PINCFG(130, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, 0),
846 NPCM7XX_PINCFG(131, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, 0),
847 NPCM7XX_PINCFG(132, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0),
848 NPCM7XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0),
849 NPCM7XX_PINCFG(134, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0),
850 NPCM7XX_PINCFG(135, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0),
851 NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
852 NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
853 NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
854 NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
855 NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
856 NPCM7XX_PINCFG(141, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, 0),
857 NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
858 NPCM7XX_PINCFG(143, sd1, MFSEL3, 12, sd1pwr, MFSEL4, 5, none, NONE, 0, 0),
859 NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DS(4, 8)),
860 NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DS(4, 8)),
861 NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DS(4, 8)),
862 NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DS(4, 8)),
863 NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
864 NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
865 NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
866 NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
867 NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
868 NPCM7XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, 0), /* Z1/A1 */
869 NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
870 NPCM7XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, 0), /* Z1/A1 */
871 NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
872 NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
873 NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
874 NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
875
876 NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
877 NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DS(8, 12)),
878 NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DS(8, 12)),
879 NPCM7XX_PINCFG(163, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0),
880 NPCM7XX_PINCFG(164, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
881 NPCM7XX_PINCFG(165, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
882 NPCM7XX_PINCFG(166, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
883 NPCM7XX_PINCFG(167, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC),
884 NPCM7XX_PINCFG(168, lpcclk, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL3, 16, 0),
885 NPCM7XX_PINCFG(169, scipme, MFSEL3, 0, none, NONE, 0, none, NONE, 0, 0),
886 NPCM7XX_PINCFG(170, sci, MFSEL1, 22, none, NONE, 0, none, NONE, 0, 0),
887 NPCM7XX_PINCFG(171, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0),
888 NPCM7XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0),
889 NPCM7XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0),
890 NPCM7XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0),
891 NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)),
892 NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)),
893 NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)),
894 NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
895 NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
896 NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
897 NPCM7XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
898 NPCM7XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
899 NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
900 NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO),
901 NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO),
902 NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12)),
903 NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DS(8, 12)),
904 NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DS(8, 12) | SLEW),
905 NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DS(8, 12) | SLEW),
906 NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DS(2, 4)),
907 NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), /* XX */
908
909 NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), /* XX */
910 NPCM7XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
911 NPCM7XX_PINCFG(194, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0),
912 NPCM7XX_PINCFG(195, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0),
913 NPCM7XX_PINCFG(196, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0),
914 NPCM7XX_PINCFG(197, smb0den, I2CSEGSEL, 22, none, NONE, 0, none, NONE, 0, SLEW),
915 NPCM7XX_PINCFG(198, smb0d, I2CSEGSEL, 2, none, NONE, 0, none, NONE, 0, 0),
916 NPCM7XX_PINCFG(199, smb0d, I2CSEGSEL, 2, none, NONE, 0, none, NONE, 0, 0),
917 NPCM7XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0),
918 NPCM7XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0),
919 NPCM7XX_PINCFG(202, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0),
920 NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DS(8, 12)),
921 NPCM7XX_PINCFG(204, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),
922 NPCM7XX_PINCFG(205, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW),
923 NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DS(4, 8)),
924 NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DS(4, 8)),
925 NPCM7XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
926 NPCM7XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
927 NPCM7XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
928 NPCM7XX_PINCFG(211, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
929 NPCM7XX_PINCFG(212, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
930 NPCM7XX_PINCFG(213, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
931 NPCM7XX_PINCFG(214, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
932 NPCM7XX_PINCFG(215, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0),
933 NPCM7XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0),
934 NPCM7XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0),
935 NPCM7XX_PINCFG(218, wdog1, MFSEL3, 19, none, NONE, 0, none, NONE, 0, 0),
936 NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DS(4, 8)),
937 NPCM7XX_PINCFG(220, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0),
938 NPCM7XX_PINCFG(221, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0),
939 NPCM7XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0),
940 NPCM7XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0),
941
942 NPCM7XX_PINCFG(224, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, SLEW),
943 NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO),
944 NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO),
945 NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
946 NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
947 NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
948 NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW),
949 NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DS(8, 12)),
950 NPCM7XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */
951 NPCM7XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */
952 NPCM7XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */
953};
954
955#define NPCM7XX_PIN(a, b) { .number = a, .name = b }
956struct npcm7xx_pin_desc {
957 unsigned int number;
958 const char *name;
959};
960
961/* number, name, drv_data */
962static const struct npcm7xx_pin_desc npcm7xx_pins[] = {
963 NPCM7XX_PIN(0, "GPIO0/IOX1DI"),
964 NPCM7XX_PIN(1, "GPIO1/IOX1LD"),
965 NPCM7XX_PIN(2, "GPIO2/IOX1CK"),
966 NPCM7XX_PIN(3, "GPIO3/IOX1D0"),
967 NPCM7XX_PIN(4, "GPIO4/IOX2DI/SMB1DSDA"),
968 NPCM7XX_PIN(5, "GPIO5/IOX2LD/SMB1DSCL"),
969 NPCM7XX_PIN(6, "GPIO6/IOX2CK/SMB2DSDA"),
970 NPCM7XX_PIN(7, "GPIO7/IOX2D0/SMB2DSCL"),
971 NPCM7XX_PIN(8, "GPIO8/LKGPO1"),
972 NPCM7XX_PIN(9, "GPIO9/LKGPO2"),
973 NPCM7XX_PIN(10, "GPIO10/IOXHLD"),
974 NPCM7XX_PIN(11, "GPIO11/IOXHCK"),
975 NPCM7XX_PIN(12, "GPIO12/GSPICK/SMB5BSCL"),
976 NPCM7XX_PIN(13, "GPIO13/GSPIDO/SMB5BSDA"),
977 NPCM7XX_PIN(14, "GPIO14/GSPIDI/SMB5CSCL"),
978 NPCM7XX_PIN(15, "GPIO15/GSPICS/SMB5CSDA"),
979 NPCM7XX_PIN(16, "GPIO16/LKGPO0"),
980 NPCM7XX_PIN(17, "GPIO17/PSPI2DI/SMB4DEN"),
981 NPCM7XX_PIN(18, "GPIO18/PSPI2D0/SMB4BSDA"),
982 NPCM7XX_PIN(19, "GPIO19/PSPI2CK/SMB4BSCL"),
983 NPCM7XX_PIN(20, "GPIO20/SMB4CSDA/SMB15SDA"),
984 NPCM7XX_PIN(21, "GPIO21/SMB4CSCL/SMB15SCL"),
985 NPCM7XX_PIN(22, "GPIO22/SMB4DSDA/SMB14SDA"),
986 NPCM7XX_PIN(23, "GPIO23/SMB4DSCL/SMB14SCL"),
987 NPCM7XX_PIN(24, "GPIO24/IOXHDO"),
988 NPCM7XX_PIN(25, "GPIO25/IOXHDI"),
989 NPCM7XX_PIN(26, "GPIO26/SMB5SDA"),
990 NPCM7XX_PIN(27, "GPIO27/SMB5SCL"),
991 NPCM7XX_PIN(28, "GPIO28/SMB4SDA"),
992 NPCM7XX_PIN(29, "GPIO29/SMB4SCL"),
993 NPCM7XX_PIN(30, "GPIO30/SMB3SDA"),
994 NPCM7XX_PIN(31, "GPIO31/SMB3SCL"),
995
996 NPCM7XX_PIN(32, "GPIO32/nSPI0CS1"),
997 NPCM7XX_PIN(33, "SPI0D2"),
998 NPCM7XX_PIN(34, "SPI0D3"),
999 NPCM7XX_PIN(35, "NA"),
1000 NPCM7XX_PIN(36, "NA"),
1001 NPCM7XX_PIN(37, "GPIO37/SMB3CSDA"),
1002 NPCM7XX_PIN(38, "GPIO38/SMB3CSCL"),
1003 NPCM7XX_PIN(39, "GPIO39/SMB3BSDA"),
1004 NPCM7XX_PIN(40, "GPIO40/SMB3BSCL"),
1005 NPCM7XX_PIN(41, "GPIO41/BSPRXD"),
1006 NPCM7XX_PIN(42, "GPO42/BSPTXD/STRAP11"),
1007 NPCM7XX_PIN(43, "GPIO43/RXD1/JTMS2/BU1RXD"),
1008 NPCM7XX_PIN(44, "GPIO44/nCTS1/JTDI2/BU1CTS"),
1009 NPCM7XX_PIN(45, "GPIO45/nDCD1/JTDO2"),
1010 NPCM7XX_PIN(46, "GPIO46/nDSR1/JTCK2"),
1011 NPCM7XX_PIN(47, "GPIO47/nRI1/JCP_RDY2"),
1012 NPCM7XX_PIN(48, "GPIO48/TXD2/BSPTXD"),
1013 NPCM7XX_PIN(49, "GPIO49/RXD2/BSPRXD"),
1014 NPCM7XX_PIN(50, "GPIO50/nCTS2"),
1015 NPCM7XX_PIN(51, "GPO51/nRTS2/STRAP2"),
1016 NPCM7XX_PIN(52, "GPIO52/nDCD2"),
1017 NPCM7XX_PIN(53, "GPO53/nDTR2_BOUT2/STRAP1"),
1018 NPCM7XX_PIN(54, "GPIO54/nDSR2"),
1019 NPCM7XX_PIN(55, "GPIO55/nRI2"),
1020 NPCM7XX_PIN(56, "GPIO56/R1RXERR"),
1021 NPCM7XX_PIN(57, "GPIO57/R1MDC"),
1022 NPCM7XX_PIN(58, "GPIO58/R1MDIO"),
1023 NPCM7XX_PIN(59, "GPIO59/SMB3DSDA"),
1024 NPCM7XX_PIN(60, "GPIO60/SMB3DSCL"),
1025 NPCM7XX_PIN(61, "GPO61/nDTR1_BOUT1/STRAP6"),
1026 NPCM7XX_PIN(62, "GPO62/nRTST1/STRAP5"),
1027 NPCM7XX_PIN(63, "GPO63/TXD1/STRAP4"),
1028
1029 NPCM7XX_PIN(64, "GPIO64/FANIN0"),
1030 NPCM7XX_PIN(65, "GPIO65/FANIN1"),
1031 NPCM7XX_PIN(66, "GPIO66/FANIN2"),
1032 NPCM7XX_PIN(67, "GPIO67/FANIN3"),
1033 NPCM7XX_PIN(68, "GPIO68/FANIN4"),
1034 NPCM7XX_PIN(69, "GPIO69/FANIN5"),
1035 NPCM7XX_PIN(70, "GPIO70/FANIN6"),
1036 NPCM7XX_PIN(71, "GPIO71/FANIN7"),
1037 NPCM7XX_PIN(72, "GPIO72/FANIN8"),
1038 NPCM7XX_PIN(73, "GPIO73/FANIN9"),
1039 NPCM7XX_PIN(74, "GPIO74/FANIN10"),
1040 NPCM7XX_PIN(75, "GPIO75/FANIN11"),
1041 NPCM7XX_PIN(76, "GPIO76/FANIN12"),
1042 NPCM7XX_PIN(77, "GPIO77/FANIN13"),
1043 NPCM7XX_PIN(78, "GPIO78/FANIN14"),
1044 NPCM7XX_PIN(79, "GPIO79/FANIN15"),
1045 NPCM7XX_PIN(80, "GPIO80/PWM0"),
1046 NPCM7XX_PIN(81, "GPIO81/PWM1"),
1047 NPCM7XX_PIN(82, "GPIO82/PWM2"),
1048 NPCM7XX_PIN(83, "GPIO83/PWM3"),
1049 NPCM7XX_PIN(84, "GPIO84/R2TXD0"),
1050 NPCM7XX_PIN(85, "GPIO85/R2TXD1"),
1051 NPCM7XX_PIN(86, "GPIO86/R2TXEN"),
1052 NPCM7XX_PIN(87, "GPIO87/R2RXD0"),
1053 NPCM7XX_PIN(88, "GPIO88/R2RXD1"),
1054 NPCM7XX_PIN(89, "GPIO89/R2CRSDV"),
1055 NPCM7XX_PIN(90, "GPIO90/R2RXERR"),
1056 NPCM7XX_PIN(91, "GPIO91/R2MDC"),
1057 NPCM7XX_PIN(92, "GPIO92/R2MDIO"),
1058 NPCM7XX_PIN(93, "GPIO93/GA20/SMB5DSCL"),
1059 NPCM7XX_PIN(94, "GPIO94/nKBRST/SMB5DSDA"),
1060 NPCM7XX_PIN(95, "GPIO95/nLRESET/nESPIRST"),
1061
1062 NPCM7XX_PIN(96, "GPIO96/RG1TXD0"),
1063 NPCM7XX_PIN(97, "GPIO97/RG1TXD1"),
1064 NPCM7XX_PIN(98, "GPIO98/RG1TXD2"),
1065 NPCM7XX_PIN(99, "GPIO99/RG1TXD3"),
1066 NPCM7XX_PIN(100, "GPIO100/RG1TXC"),
1067 NPCM7XX_PIN(101, "GPIO101/RG1TXCTL"),
1068 NPCM7XX_PIN(102, "GPIO102/RG1RXD0"),
1069 NPCM7XX_PIN(103, "GPIO103/RG1RXD1"),
1070 NPCM7XX_PIN(104, "GPIO104/RG1RXD2"),
1071 NPCM7XX_PIN(105, "GPIO105/RG1RXD3"),
1072 NPCM7XX_PIN(106, "GPIO106/RG1RXC"),
1073 NPCM7XX_PIN(107, "GPIO107/RG1RXCTL"),
1074 NPCM7XX_PIN(108, "GPIO108/RG1MDC"),
1075 NPCM7XX_PIN(109, "GPIO109/RG1MDIO"),
1076 NPCM7XX_PIN(110, "GPIO110/RG2TXD0/DDRV0"),
1077 NPCM7XX_PIN(111, "GPIO111/RG2TXD1/DDRV1"),
1078 NPCM7XX_PIN(112, "GPIO112/RG2TXD2/DDRV2"),
1079 NPCM7XX_PIN(113, "GPIO113/RG2TXD3/DDRV3"),
1080 NPCM7XX_PIN(114, "GPIO114/SMB0SCL"),
1081 NPCM7XX_PIN(115, "GPIO115/SMB0SDA"),
1082 NPCM7XX_PIN(116, "GPIO116/SMB1SCL"),
1083 NPCM7XX_PIN(117, "GPIO117/SMB1SDA"),
1084 NPCM7XX_PIN(118, "GPIO118/SMB2SCL"),
1085 NPCM7XX_PIN(119, "GPIO119/SMB2SDA"),
1086 NPCM7XX_PIN(120, "GPIO120/SMB2CSDA"),
1087 NPCM7XX_PIN(121, "GPIO121/SMB2CSCL"),
1088 NPCM7XX_PIN(122, "GPIO122/SMB2BSDA"),
1089 NPCM7XX_PIN(123, "GPIO123/SMB2BSCL"),
1090 NPCM7XX_PIN(124, "GPIO124/SMB1CSDA"),
1091 NPCM7XX_PIN(125, "GPIO125/SMB1CSCL"),
1092 NPCM7XX_PIN(126, "GPIO126/SMB1BSDA"),
1093 NPCM7XX_PIN(127, "GPIO127/SMB1BSCL"),
1094
1095 NPCM7XX_PIN(128, "GPIO128/SMB8SCL"),
1096 NPCM7XX_PIN(129, "GPIO129/SMB8SDA"),
1097 NPCM7XX_PIN(130, "GPIO130/SMB9SCL"),
1098 NPCM7XX_PIN(131, "GPIO131/SMB9SDA"),
1099 NPCM7XX_PIN(132, "GPIO132/SMB10SCL"),
1100 NPCM7XX_PIN(133, "GPIO133/SMB10SDA"),
1101 NPCM7XX_PIN(134, "GPIO134/SMB11SCL"),
1102 NPCM7XX_PIN(135, "GPIO135/SMB11SDA"),
1103 NPCM7XX_PIN(136, "GPIO136/SD1DT0"),
1104 NPCM7XX_PIN(137, "GPIO137/SD1DT1"),
1105 NPCM7XX_PIN(138, "GPIO138/SD1DT2"),
1106 NPCM7XX_PIN(139, "GPIO139/SD1DT3"),
1107 NPCM7XX_PIN(140, "GPIO140/SD1CLK"),
1108 NPCM7XX_PIN(141, "GPIO141/SD1WP"),
1109 NPCM7XX_PIN(142, "GPIO142/SD1CMD"),
1110 NPCM7XX_PIN(143, "GPIO143/SD1CD/SD1PWR"),
1111 NPCM7XX_PIN(144, "GPIO144/PWM4"),
1112 NPCM7XX_PIN(145, "GPIO145/PWM5"),
1113 NPCM7XX_PIN(146, "GPIO146/PWM6"),
1114 NPCM7XX_PIN(147, "GPIO147/PWM7"),
1115 NPCM7XX_PIN(148, "GPIO148/MMCDT4"),
1116 NPCM7XX_PIN(149, "GPIO149/MMCDT5"),
1117 NPCM7XX_PIN(150, "GPIO150/MMCDT6"),
1118 NPCM7XX_PIN(151, "GPIO151/MMCDT7"),
1119 NPCM7XX_PIN(152, "GPIO152/MMCCLK"),
1120 NPCM7XX_PIN(153, "GPIO153/MMCWP"),
1121 NPCM7XX_PIN(154, "GPIO154/MMCCMD"),
1122 NPCM7XX_PIN(155, "GPIO155/nMMCCD/nMMCRST"),
1123 NPCM7XX_PIN(156, "GPIO156/MMCDT0"),
1124 NPCM7XX_PIN(157, "GPIO157/MMCDT1"),
1125 NPCM7XX_PIN(158, "GPIO158/MMCDT2"),
1126 NPCM7XX_PIN(159, "GPIO159/MMCDT3"),
1127
1128 NPCM7XX_PIN(160, "GPIO160/CLKOUT/RNGOSCOUT"),
1129 NPCM7XX_PIN(161, "GPIO161/nLFRAME/nESPICS"),
1130 NPCM7XX_PIN(162, "GPIO162/SERIRQ"),
1131 NPCM7XX_PIN(163, "GPIO163/LCLK/ESPICLK"),
1132 NPCM7XX_PIN(164, "GPIO164/LAD0/ESPI_IO0"/*dscnt6*/),
1133 NPCM7XX_PIN(165, "GPIO165/LAD1/ESPI_IO1"/*dscnt6*/),
1134 NPCM7XX_PIN(166, "GPIO166/LAD2/ESPI_IO2"/*dscnt6*/),
1135 NPCM7XX_PIN(167, "GPIO167/LAD3/ESPI_IO3"/*dscnt6*/),
1136 NPCM7XX_PIN(168, "GPIO168/nCLKRUN/nESPIALERT"),
1137 NPCM7XX_PIN(169, "GPIO169/nSCIPME"),
1138 NPCM7XX_PIN(170, "GPIO170/nSMI"),
1139 NPCM7XX_PIN(171, "GPIO171/SMB6SCL"),
1140 NPCM7XX_PIN(172, "GPIO172/SMB6SDA"),
1141 NPCM7XX_PIN(173, "GPIO173/SMB7SCL"),
1142 NPCM7XX_PIN(174, "GPIO174/SMB7SDA"),
1143 NPCM7XX_PIN(175, "GPIO175/PSPI1CK/FANIN19"),
1144 NPCM7XX_PIN(176, "GPIO176/PSPI1DO/FANIN18"),
1145 NPCM7XX_PIN(177, "GPIO177/PSPI1DI/FANIN17"),
1146 NPCM7XX_PIN(178, "GPIO178/R1TXD0"),
1147 NPCM7XX_PIN(179, "GPIO179/R1TXD1"),
1148 NPCM7XX_PIN(180, "GPIO180/R1TXEN"),
1149 NPCM7XX_PIN(181, "GPIO181/R1RXD0"),
1150 NPCM7XX_PIN(182, "GPIO182/R1RXD1"),
1151 NPCM7XX_PIN(183, "GPIO183/SPI3CK"),
1152 NPCM7XX_PIN(184, "GPO184/SPI3D0/STRAP9"),
1153 NPCM7XX_PIN(185, "GPO185/SPI3D1/STRAP10"),
1154 NPCM7XX_PIN(186, "GPIO186/nSPI3CS0"),
1155 NPCM7XX_PIN(187, "GPIO187/nSPI3CS1"),
1156 NPCM7XX_PIN(188, "GPIO188/SPI3D2/nSPI3CS2"),
1157 NPCM7XX_PIN(189, "GPIO189/SPI3D3/nSPI3CS3"),
1158 NPCM7XX_PIN(190, "GPIO190/nPRD_SMI"),
1159 NPCM7XX_PIN(191, "GPIO191"),
1160
1161 NPCM7XX_PIN(192, "GPIO192"),
1162 NPCM7XX_PIN(193, "GPIO193/R1CRSDV"),
1163 NPCM7XX_PIN(194, "GPIO194/SMB0BSCL"),
1164 NPCM7XX_PIN(195, "GPIO195/SMB0BSDA"),
1165 NPCM7XX_PIN(196, "GPIO196/SMB0CSCL"),
1166 NPCM7XX_PIN(197, "GPIO197/SMB0DEN"),
1167 NPCM7XX_PIN(198, "GPIO198/SMB0DSDA"),
1168 NPCM7XX_PIN(199, "GPIO199/SMB0DSCL"),
1169 NPCM7XX_PIN(200, "GPIO200/R2CK"),
1170 NPCM7XX_PIN(201, "GPIO201/R1CK"),
1171 NPCM7XX_PIN(202, "GPIO202/SMB0CSDA"),
1172 NPCM7XX_PIN(203, "GPIO203/FANIN16"),
1173 NPCM7XX_PIN(204, "GPIO204/DDC2SCL"),
1174 NPCM7XX_PIN(205, "GPIO205/DDC2SDA"),
1175 NPCM7XX_PIN(206, "GPIO206/HSYNC2"),
1176 NPCM7XX_PIN(207, "GPIO207/VSYNC2"),
1177 NPCM7XX_PIN(208, "GPIO208/RG2TXC/DVCK"),
1178 NPCM7XX_PIN(209, "GPIO209/RG2TXCTL/DDRV4"),
1179 NPCM7XX_PIN(210, "GPIO210/RG2RXD0/DDRV5"),
1180 NPCM7XX_PIN(211, "GPIO211/RG2RXD1/DDRV6"),
1181 NPCM7XX_PIN(212, "GPIO212/RG2RXD2/DDRV7"),
1182 NPCM7XX_PIN(213, "GPIO213/RG2RXD3/DDRV8"),
1183 NPCM7XX_PIN(214, "GPIO214/RG2RXC/DDRV9"),
1184 NPCM7XX_PIN(215, "GPIO215/RG2RXCTL/DDRV10"),
1185 NPCM7XX_PIN(216, "GPIO216/RG2MDC/DDRV11"),
1186 NPCM7XX_PIN(217, "GPIO217/RG2MDIO/DVHSYNC"),
1187 NPCM7XX_PIN(218, "GPIO218/nWDO1"),
1188 NPCM7XX_PIN(219, "GPIO219/nWDO2"),
1189 NPCM7XX_PIN(220, "GPIO220/SMB12SCL"),
1190 NPCM7XX_PIN(221, "GPIO221/SMB12SDA"),
1191 NPCM7XX_PIN(222, "GPIO222/SMB13SCL"),
1192 NPCM7XX_PIN(223, "GPIO223/SMB13SDA"),
1193 NPCM7XX_PIN(224, "GPIO224/SPIXCK"),
1194 NPCM7XX_PIN(225, "GPO225/SPIXD0/STRAP12"),
1195 NPCM7XX_PIN(226, "GPO226/SPIXD1/STRAP13"),
1196 NPCM7XX_PIN(227, "GPIO227/nSPIXCS0"),
1197 NPCM7XX_PIN(228, "GPIO228/nSPIXCS1"),
1198 NPCM7XX_PIN(229, "GPO229/SPIXD2/STRAP3"),
1199 NPCM7XX_PIN(230, "GPIO230/SPIXD3"),
1200 NPCM7XX_PIN(231, "GPIO231/nCLKREQ"),
1201 NPCM7XX_PIN(232, "NA"),
1202 NPCM7XX_PIN(233, "NA"),
1203 NPCM7XX_PIN(234, "NA"),
1204 NPCM7XX_PIN(235, "NA"),
1205 NPCM7XX_PIN(236, "NA"),
1206 NPCM7XX_PIN(237, "NA"),
1207 NPCM7XX_PIN(238, "NA"),
1208 NPCM7XX_PIN(239, "NA"),
1209 NPCM7XX_PIN(240, "NA"),
1210 NPCM7XX_PIN(241, "NA"),
1211 NPCM7XX_PIN(242, "NA"),
1212 NPCM7XX_PIN(243, "NA"),
1213 NPCM7XX_PIN(244, "NA"),
1214 NPCM7XX_PIN(245, "NA"),
1215 NPCM7XX_PIN(246, "NA"),
1216 NPCM7XX_PIN(247, "NA"),
1217 NPCM7XX_PIN(248, "NA"),
1218 NPCM7XX_PIN(249, "NA"),
1219 NPCM7XX_PIN(250, "NA"),
1220 NPCM7XX_PIN(251, "NA"),
1221 NPCM7XX_PIN(252, "NA"),
1222 NPCM7XX_PIN(253, "NA"),
1223 NPCM7XX_PIN(254, "NA"),
1224 NPCM7XX_PIN(255, "GPI255/DACOSEL"),
1225};
1226
1227struct npcm7xx_pinctrl_priv {
1228 void __iomem *gpio_base;
1229 struct regmap *gcr_regmap;
1230 struct regmap *rst_regmap;
1231};
1232
1233static int npcm7xx_pinctrl_probe(struct udevice *dev)
1234{
1235 struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
1236
1237 priv->gpio_base = dev_read_addr_ptr(dev);
1238 if (!priv->gpio_base)
1239 return -EINVAL;
1240
1241 priv->gcr_regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-gcr");
1242 if (IS_ERR(priv->gcr_regmap))
1243 return -EINVAL;
1244
1245 priv->rst_regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-rst");
1246 if (IS_ERR(priv->rst_regmap))
1247 return -EINVAL;
1248
1249 return 0;
1250}
1251
1252/* Enable mode in pin group */
1253static void npcm7xx_setfunc(struct udevice *dev, const int *pin,
1254 int pin_number, int mode)
1255{
1256 struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
1257 const struct npcm7xx_pincfg *cfg;
1258 int i;
1259
1260 for (i = 0 ; i < pin_number ; i++) {
1261 cfg = &pincfgs[pin[i]];
1262 if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || cfg->fn2 == mode) {
1263 if (cfg->reg0) {
1264 if (cfg->fn0 == mode)
1265 regmap_update_bits(priv->gcr_regmap, cfg->reg0, BIT(cfg->bit0), BIT(cfg->bit0));
1266 else
1267 regmap_update_bits(priv->gcr_regmap, cfg->reg0, BIT(cfg->bit0), 0);
1268 }
1269 if (cfg->reg1) {
1270 if (cfg->fn1 == mode)
1271 regmap_update_bits(priv->gcr_regmap, cfg->reg1, BIT(cfg->bit1), BIT(cfg->bit1));
1272 else
1273 regmap_update_bits(priv->gcr_regmap, cfg->reg1, BIT(cfg->bit1), 0);
1274 }
1275 if (cfg->reg2) {
1276 if (cfg->fn2 == mode)
1277 regmap_update_bits(priv->gcr_regmap, cfg->reg2, BIT(cfg->bit2), BIT(cfg->bit2));
1278 else
1279 regmap_update_bits(priv->gcr_regmap, cfg->reg2, BIT(cfg->bit2), 0);
1280 }
1281 }
1282 }
1283}
1284
1285static int npcm7xx_get_pins_count(struct udevice *dev)
1286{
1287 return ARRAY_SIZE(npcm7xx_pins);
1288}
1289
1290static const char *npcm7xx_get_pin_name(struct udevice *dev,
1291 unsigned int selector)
1292{
1293 return npcm7xx_pins[selector].name;
1294}
1295
1296static int npcm7xx_get_groups_count(struct udevice *dev)
1297{
1298 return ARRAY_SIZE(npcm7xx_groups);
1299}
1300
1301static const char *npcm7xx_get_group_name(struct udevice *dev,
1302 unsigned int selector)
1303{
1304 return npcm7xx_groups[selector].name;
1305}
1306
1307static int npcm7xx_get_functions_count(struct udevice *dev)
1308{
1309 return ARRAY_SIZE(npcm7xx_funcs);
1310}
1311
1312static const char *npcm7xx_get_function_name(struct udevice *dev,
1313 unsigned int selector)
1314{
1315 return npcm7xx_funcs[selector].name;
1316}
1317
1318static int npcm7xx_pinmux_set(struct udevice *dev,
1319 unsigned int group,
1320 unsigned int function)
1321{
1322 dev_dbg(dev, "set_mux: %d, %d[%s]\n", function, group,
1323 npcm7xx_groups[group].name);
1324
1325 npcm7xx_setfunc(dev, npcm7xx_groups[group].pins,
1326 npcm7xx_groups[group].npins, group);
1327
1328 return 0;
1329}
1330
1331#if CONFIG_IS_ENABLED(PINCONF)
1332
1333#define PIN_CONFIG_PERSIST_STATE (PIN_CONFIG_END + 1)
1334#define PIN_CONFIG_POLARITY_STATE (PIN_CONFIG_END + 2)
1335#define PIN_CONFIG_EVENT_CLEAR (PIN_CONFIG_END + 3)
1336
1337static const struct pinconf_param npcm7xx_conf_params[] = {
1338 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
1339 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
1340 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
1341 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
1342 { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },
1343 { "output-high", PIN_CONFIG_OUTPUT, 1, },
1344 { "output-low", PIN_CONFIG_OUTPUT, 0, },
1345 { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 1 },
1346 { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 1 },
1347 { "persist-enable", PIN_CONFIG_PERSIST_STATE, 1 },
1348 { "persist-disable", PIN_CONFIG_PERSIST_STATE, 0 },
1349 { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
1350 { "active-high", PIN_CONFIG_POLARITY_STATE, 0 },
1351 { "active-low", PIN_CONFIG_POLARITY_STATE, 1 },
1352 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
1353 { "slew-rate", PIN_CONFIG_SLEW_RATE, 0},
1354 { "event-clear", PIN_CONFIG_EVENT_CLEAR, 0},
1355};
1356
1357static bool is_gpio_persist(struct udevice *dev, u8 bank)
1358{
1359 struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
1360 u32 value, tmp;
1361
1362 u8 offset = bank + GPIOX_MODULE_RESET;
1363 u32 mask = 1 << offset;
1364
1365 regmap_read(priv->gcr_regmap, NPCM7XX_GCR_RESSR, &value);
1366 if (value == 0) {
1367 regmap_read(priv->gcr_regmap, NPCM7XX_GCR_INTCR2, &tmp);
1368 value = ~tmp;
1369 }
1370
1371 dev_dbg(dev, "reboot reason: 0x%x\n", value);
1372
1373 if (value & CORST)
1374 regmap_read(priv->rst_regmap, NPCM7XX_RST_CORSTC, &tmp);
1375 else if (value & WD0RST)
1376 regmap_read(priv->rst_regmap, NPCM7XX_RST_WD0RCR, &tmp);
1377 else if (value & WD1RST)
1378 regmap_read(priv->rst_regmap, NPCM7XX_RST_WD1RCR, &tmp);
1379 else if (value & WD2RST)
1380 regmap_read(priv->rst_regmap, NPCM7XX_RST_WD2RCR, &tmp);
Jim Liu7ee1c4d2022-12-20 16:49:31 +0800[diff] [blame]1381 else if (value & SWRST1)
1382 regmap_read(priv->rst_regmap, NPCM7XX_RST_SWRSTC1, &tmp);
1383 else if (value & SWRST2)
1384 regmap_read(priv->rst_regmap, NPCM7XX_RST_SWRSTC2, &tmp);
1385 else if (value & SWRST3)
1386 regmap_read(priv->rst_regmap, NPCM7XX_RST_SWRSTC3, &tmp);
1387 else if (value & SW4RST)
1388 regmap_read(priv->rst_regmap, NPCM7XX_RST_SWRSTC4, &tmp);
Jim Liuf49d6162022-05-17 16:30:32 +0800[diff] [blame]1389 else
1390 return false;
1391
1392 return !((tmp & mask) >> offset);
1393}
1394
1395static int npcm7xx_gpio_reset_persist(struct udevice *dev, unsigned int banknum, int enable)
1396{
1397 struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
1398 u32 num = GPIOX_MODULE_RESET + banknum;
1399
1400 dev_dbg(dev, "set gpio persist, bank %d, enable %d\n", banknum, enable);
1401
1402 if (enable) {
Jim Liu45455e82022-09-13 14:23:15 +0800[diff] [blame]1403 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD0RCR, BIT(num), 0);
1404 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD1RCR, BIT(num), 0);
1405 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD2RCR, BIT(num), 0);
1406 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_CORSTC, BIT(num), 0);
Jim Liu7ee1c4d2022-12-20 16:49:31 +0800[diff] [blame]1407 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC1, BIT(num), 0);
1408 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC2, BIT(num), 0);
1409 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC3, BIT(num), 0);
1410 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC4, BIT(num), 0);
Jim Liuf49d6162022-05-17 16:30:32 +0800[diff] [blame]1411 } else {
1412 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD0RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
1413 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD1RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
1414 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_WD2RCR, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
1415 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_CORSTC, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
Jim Liu7ee1c4d2022-12-20 16:49:31 +0800[diff] [blame]1416 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC1, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
1417 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC2, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
1418 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC3, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
1419 regmap_update_bits(priv->rst_regmap, NPCM7XX_RST_SWRSTC4, BIT(num) | CA9C_RESET, BIT(num) | CA9C_RESET);
Jim Liuf49d6162022-05-17 16:30:32 +0800[diff] [blame]1420 }
1421
1422 return 0;
1423}
1424
1425/* Set drive strength for a pin, if supported */
1426static int npcm7xx_set_drive_strength(struct udevice *dev,
1427 unsigned int pin, int nval)
1428{
1429 struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
1430 int bank = pin / NPCM7XX_GPIO_PER_BANK;
1431 int gpio = (pin % NPCM7XX_GPIO_PER_BITS);
1432 void __iomem *base = priv->gpio_base + (NPCM7XX_GPIO_BANK_OFFSET * bank);
1433 int v;
1434
1435 v = (pincfgs[pin].flag & DRIVE_STRENGTH_MASK);
1436 if (!nval || !v)
1437 return -ENOTSUPP;
1438
1439 if (DSLO(v) == nval) {
1440 dev_dbg(dev,
1441 "setting pin %d to low strength [%d]\n", pin, nval);
1442 clrbits_le32(base + NPCM7XX_GP_N_ODSC, BIT(gpio));
1443 return 0;
1444 } else if (DSHI(v) == nval) {
1445 dev_dbg(dev,
1446 "setting pin %d to high strength [%d]\n", pin, nval);
1447 setbits_le32(base + NPCM7XX_GP_N_ODSC, BIT(gpio));
1448 return 0;
1449 }
1450
1451 return -ENOTSUPP;
1452}
1453
1454/* Set slew rate of pin (high/low) */
1455static int npcm7xx_set_slew_rate(struct udevice *dev, unsigned int pin,
1456 int arg)
1457{
1458 struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
1459 int bank = pin / NPCM7XX_GPIO_PER_BANK;
1460 int gpio = (pin % NPCM7XX_GPIO_PER_BITS);
1461 void __iomem *base = priv->gpio_base + (NPCM7XX_GPIO_BANK_OFFSET * bank);
1462
1463 if (pincfgs[pin].flag & SLEW) {
1464 switch (arg) {
1465 case 0:
1466 dev_dbg(dev,
1467 "setting pin %d slew rate to low\n", pin);
1468 clrbits_le32(base + NPCM7XX_GP_N_OSRC, BIT(gpio));
1469 return 0;
1470 case 1:
1471 dev_dbg(dev,
1472 "setting pin %d slew rate to high\n", pin);
1473 setbits_le32(base + NPCM7XX_GP_N_OSRC, BIT(gpio));
1474 return 0;
1475 default:
1476 return -ENOTSUPP;
1477 }
1478 }
1479
1480 /* LPC Slew rate in SRCNT register */
1481 if (pincfgs[pin].flag & SLEWLPC) {
1482 switch (arg) {
1483 case 0:
1484 dev_dbg(dev,
1485 "setting LPC/ESPI(%d) slew rate to low\n", pin);
1486 regmap_update_bits(priv->gcr_regmap, NPCM7XX_GCR_SRCNT, SRCNT_ESPI, 0);
1487 return 0;
1488 case 1:
1489 dev_dbg(dev, "setting LPC/ESPI(%d) slew rate to high\n", pin);
1490 regmap_update_bits(priv->gcr_regmap, NPCM7XX_GCR_SRCNT, SRCNT_ESPI, SRCNT_ESPI);
1491 return 0;
1492 default:
1493 return -ENOTSUPP;
1494 }
1495 }
1496
1497 return -ENOTSUPP;
1498}
1499
1500static int npcm7xx_pinconf_set(struct udevice *dev, unsigned int pin,
1501 unsigned int param, unsigned int arg)
1502{
1503 struct npcm7xx_pinctrl_priv *priv = dev_get_priv(dev);
1504 int err = 0;
1505 int bank = pin / NPCM7XX_GPIO_PER_BANK;
1506 int gpio = (pin % NPCM7XX_GPIO_PER_BITS);
1507 void __iomem *base = priv->gpio_base + (0x1000 * bank);
1508
1509 npcm7xx_setfunc(dev, (const int *)&pin, 1, fn_gpio);
1510
1511 /* To prevent unexpected IRQ trap at verctor 00 in linux kernel */
1512 if (param == PIN_CONFIG_EVENT_CLEAR) {
1513 dev_dbg(dev, "set pin %d event clear\n", pin);
1514 clrbits_le32(base + NPCM7XX_GP_N_EVEN, BIT(gpio));
1515 setbits_le32(base + NPCM7XX_GP_N_EVST, BIT(gpio));
1516 return err;
1517 }
1518
1519 // allow set persist state disable
1520 if (param == PIN_CONFIG_PERSIST_STATE) {
1521 npcm7xx_gpio_reset_persist(dev, bank, arg);
1522 return err;
1523 }
1524
1525 if (is_gpio_persist(dev, bank))
1526 return err;
1527
1528 switch (param) {
1529 case PIN_CONFIG_BIAS_DISABLE:
1530 dev_dbg(dev, "set pin %d bias dsiable\n", pin);
1531 clrbits_le32(base + NPCM7XX_GP_N_PU, BIT(gpio));
1532 clrbits_le32(base + NPCM7XX_GP_N_PD, BIT(gpio));
1533 break;
1534 case PIN_CONFIG_BIAS_PULL_DOWN:
1535 dev_dbg(dev, "set pin %d bias pull down\n", pin);
1536 clrbits_le32(base + NPCM7XX_GP_N_PU, BIT(gpio));
1537 setbits_le32(base + NPCM7XX_GP_N_PD, BIT(gpio));
1538 break;
1539 case PIN_CONFIG_BIAS_PULL_UP:
1540 dev_dbg(dev, "set pin %d bias pull up\n", pin);
1541 setbits_le32(base + NPCM7XX_GP_N_PU, BIT(gpio));
1542 clrbits_le32(base + NPCM7XX_GP_N_PD, BIT(gpio));
1543 break;
1544 case PIN_CONFIG_INPUT_ENABLE:
1545 dev_dbg(dev, "set pin %d input enable\n", pin);
1546 setbits_le32(base + NPCM7XX_GP_N_OEC, BIT(gpio));
1547 setbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio));
1548 break;
1549 case PIN_CONFIG_OUTPUT_ENABLE:
1550 dev_dbg(dev, "set pin %d output enable\n", pin);
1551 clrbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio));
1552 setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio));
1553 case PIN_CONFIG_OUTPUT:
1554 dev_dbg(dev, "set pin %d output %d\n", pin, arg);
Jim Liuf49d6162022-05-17 16:30:32 +0800[diff] [blame]1555 if (arg)
1556 setbits_le32(base + NPCM7XX_GP_N_DOUT, BIT(gpio));
1557 else
1558 clrbits_le32(base + NPCM7XX_GP_N_DOUT, BIT(gpio));
Jim Liuf517f612023-05-09 15:07:34 +0800[diff] [blame]1559 clrbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio));
1560 setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio));
Jim Liuf49d6162022-05-17 16:30:32 +0800[diff] [blame]1561 break;
1562 case PIN_CONFIG_DRIVE_PUSH_PULL:
1563 dev_dbg(dev, "set pin %d push pull\n", pin);
1564 clrbits_le32(base + NPCM7XX_GP_N_OTYP, BIT(gpio));
1565 break;
1566 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1567 dev_dbg(dev, "set pin %d open drain\n", pin);
1568 setbits_le32(base + NPCM7XX_GP_N_OTYP, BIT(gpio));
1569 break;
1570 case PIN_CONFIG_INPUT_DEBOUNCE:
1571 dev_dbg(dev, "set pin %d input debounce\n", pin);
1572 setbits_le32(base + NPCM7XX_GP_N_DBNC, BIT(gpio));
1573 break;
1574 case PIN_CONFIG_POLARITY_STATE:
1575 dev_dbg(dev, "set pin %d active %d\n", pin, arg);
1576 if (arg)
1577 setbits_le32(base + NPCM7XX_GP_N_POL, BIT(gpio));
1578 else
1579 clrbits_le32(base + NPCM7XX_GP_N_POL, BIT(gpio));
1580 break;
1581 case PIN_CONFIG_DRIVE_STRENGTH:
1582 dev_dbg(dev, "set pin %d driver strength %d\n", pin, arg);
1583 err = npcm7xx_set_drive_strength(dev, pin, arg);
1584 break;
1585 case PIN_CONFIG_SLEW_RATE:
1586 dev_dbg(dev, "set pin %d slew rate %d\n", pin, arg);
1587 err = npcm7xx_set_slew_rate(dev, pin, arg);
1588 break;
1589 default:
1590 err = -ENOTSUPP;
1591 }
1592 return err;
1593}
1594
1595#endif
1596
1597static struct pinctrl_ops npcm7xx_pinctrl_ops = {
1598 .set_state = pinctrl_generic_set_state,
1599 .get_pins_count = npcm7xx_get_pins_count,
1600 .get_pin_name = npcm7xx_get_pin_name,
1601 .get_groups_count = npcm7xx_get_groups_count,
1602 .get_group_name = npcm7xx_get_group_name,
1603 .get_functions_count = npcm7xx_get_functions_count,
1604 .get_function_name = npcm7xx_get_function_name,
1605 .pinmux_set = npcm7xx_pinmux_set,
1606 .pinmux_group_set = npcm7xx_pinmux_set,
1607#if CONFIG_IS_ENABLED(PINCONF)
1608 .pinconf_num_params = ARRAY_SIZE(npcm7xx_conf_params),
1609 .pinconf_params = npcm7xx_conf_params,
1610 .pinconf_set = npcm7xx_pinconf_set,
1611 .pinconf_group_set = npcm7xx_pinconf_set,
1612#endif
1613};
1614
1615static const struct udevice_id npcm7xx_pinctrl_ids[] = {
1616 { .compatible = "nuvoton,npcm750-pinctrl" },
1617 { }
1618};
1619
1620U_BOOT_DRIVER(pinctrl_npcm7xx) = {
1621 .name = "nuvoton_npcm7xx_pinctrl",
1622 .id = UCLASS_PINCTRL,
1623 .of_match = npcm7xx_pinctrl_ids,
1624 .priv_auto = sizeof(struct npcm7xx_pinctrl_priv),
1625 .ops = &npcm7xx_pinctrl_ops,
1626 .probe = npcm7xx_pinctrl_probe,
1627};