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robert lazarskib964e932007-12-21 10:39:27 -05001/*
2 * Copyright 2007
3 * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
4 *
5 * Copyright 2007 Freescale Semiconductor, Inc.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <command.h>
28#include <pci.h>
29#include <asm/processor.h>
30#include <asm/immap_85xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050031#include <asm/fsl_pci.h>
Kumar Galaa947e4c2008-08-26 23:14:14 -050032#include <asm/fsl_ddr_sdram.h>
robert lazarskib964e932007-12-21 10:39:27 -050033#include <asm/io.h>
Kumar Galaa947e4c2008-08-26 23:14:14 -050034#include <asm/mmu.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060035#include <spd_sdram.h>
robert lazarskib964e932007-12-21 10:39:27 -050036#include <miiphy.h>
37#include <libfdt.h>
38#include <fdt_support.h>
39
robert lazarskib964e932007-12-21 10:39:27 -050040long int fixed_sdram(void);
41
42int board_early_init_f (void)
43{
44 return 0;
45}
46
47int checkboard (void)
48{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
50 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
51 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
robert lazarskib964e932007-12-21 10:39:27 -050052
53 if ((uint)&gur->porpllsr != 0xe00e0000) {
Wolfgang Denk9b55a252008-07-11 01:16:00 +020054 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
robert lazarskib964e932007-12-21 10:39:27 -050055 }
56 printf ("Board: ATUM8548\n");
57
58 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
59 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
60 ecm->eedr = 0xffffffff; /* Clear ecm errors */
61 ecm->eeer = 0xffffffff; /* Enable ecm errors */
62
63 return 0;
64}
65
66#if !defined(CONFIG_SPD_EEPROM)
67/*************************************************************************
68 * fixed sdram init -- doesn't use serial presence detect.
69 ************************************************************************/
70long int fixed_sdram (void)
71{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072 volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
robert lazarskib964e932007-12-21 10:39:27 -050073
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
75 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
76 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
77 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
78 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
79 ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
80 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
robert lazarskib964e932007-12-21 10:39:27 -050081 #if defined (CONFIG_DDR_ECC)
82 ddr->err_disable = 0x0000000D;
83 ddr->err_sbe = 0x00ff0000;
84 #endif
85 asm("sync;isync;msync");
86 udelay(500);
87 #if defined (CONFIG_DDR_ECC)
88 /* Enable ECC checking */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
robert lazarskib964e932007-12-21 10:39:27 -050090 #else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
robert lazarskib964e932007-12-21 10:39:27 -050092 #endif
93 asm("sync; isync; msync");
94 udelay(500);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
robert lazarskib964e932007-12-21 10:39:27 -050096}
97#endif /* !defined(CONFIG_SPD_EEPROM) */
98
Becky Bruce9973e3c2008-06-09 16:03:40 -050099phys_size_t
robert lazarskib964e932007-12-21 10:39:27 -0500100initdram(int board_type)
101{
102 long dram_size = 0;
103
104 puts("Initializing\n");
105
106#if defined(CONFIG_SPD_EEPROM)
Kumar Galaa947e4c2008-08-26 23:14:14 -0500107 puts("fsl_ddr_sdram\n");
108 dram_size = fsl_ddr_sdram();
109 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
110 dram_size *= 0x100000;
robert lazarskib964e932007-12-21 10:39:27 -0500111#else
112 puts("fixed_sdram\n");
113 dram_size = fixed_sdram ();
114#endif
115
robert lazarskib964e932007-12-21 10:39:27 -0500116 puts(" DDR: ");
117 return dram_size;
118}
119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#if defined(CONFIG_SYS_DRAM_TEST)
robert lazarskib964e932007-12-21 10:39:27 -0500121int
122testdram(void)
123{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
125 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
robert lazarskib964e932007-12-21 10:39:27 -0500126 uint *p;
127
128 printf("Testing DRAM from 0x%08x to 0x%08x\n",
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129 CONFIG_SYS_MEMTEST_START,
130 CONFIG_SYS_MEMTEST_END);
robert lazarskib964e932007-12-21 10:39:27 -0500131
132 printf("DRAM test phase 1:\n");
133 for (p = pstart; p < pend; p++) {
134 printf ("DRAM test attempting to write 0xaaaaaaaa at: %08x\n", (uint) p);
135 *p = 0xaaaaaaaa;
Wolfgang Denkd3a65322008-01-10 00:55:14 +0100136 }
robert lazarskib964e932007-12-21 10:39:27 -0500137
138 for (p = pstart; p < pend; p++) {
139 if (*p != 0xaaaaaaaa) {
140 printf ("DRAM test fails at: %08x\n", (uint) p);
141 return 1;
142 }
143 }
144
145 printf("DRAM test phase 2:\n");
146 for (p = pstart; p < pend; p++)
147 *p = 0x55555555;
148
149 for (p = pstart; p < pend; p++) {
150 if (*p != 0x55555555) {
151 printf ("DRAM test fails at: %08x\n", (uint) p);
152 return 1;
153 }
154 }
155
156 printf("DRAM test passed.\n");
157 return 0;
158}
159#endif
160
161#ifdef CONFIG_PCI1
162static struct pci_controller pci1_hose;
163#endif
164
165#ifdef CONFIG_PCI2
166static struct pci_controller pci2_hose;
167#endif
168
169#ifdef CONFIG_PCIE1
170static struct pci_controller pcie1_hose;
171#endif
172
Kumar Galafeadd5d2009-11-04 11:05:02 -0600173void pci_init_board(void)
robert lazarskib964e932007-12-21 10:39:27 -0500174{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Kumar Galafeadd5d2009-11-04 11:05:02 -0600176 struct fsl_pci_info pci_info[3];
177 u32 devdisr, pordevsr, io_sel;
178 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
179 int first_free_busno = 0;
180 int num = 0;
robert lazarskib964e932007-12-21 10:39:27 -0500181
Kumar Galafeadd5d2009-11-04 11:05:02 -0600182 int pcie_ep, pcie_configured;
robert lazarskib964e932007-12-21 10:39:27 -0500183
Kumar Galafeadd5d2009-11-04 11:05:02 -0600184 devdisr = in_be32(&gur->devdisr);
185 pordevsr = in_be32(&gur->pordevsr);
186 porpllsr = in_be32(&gur->porpllsr);
187 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
188
189 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
robert lazarskib964e932007-12-21 10:39:27 -0500190
Wolfgang Denkd3a65322008-01-10 00:55:14 +0100191 /* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */
Kumar Galafeadd5d2009-11-04 11:05:02 -0600192 setbits_be32(&gur->clkocr, MPC85xx_ATUM_CLKOCR);
robert lazarskib964e932007-12-21 10:39:27 -0500193
194 if (io_sel & 1) {
195 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
196 printf (" eTSEC1 is in sgmii mode.\n");
197 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
198 printf (" eTSEC2 is in sgmii mode.\n");
199 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
200 printf (" eTSEC3 is in sgmii mode.\n");
201 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
202 printf (" eTSEC4 is in sgmii mode.\n");
203 }
204
205#ifdef CONFIG_PCIE1
Kumar Galafeadd5d2009-11-04 11:05:02 -0600206 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
robert lazarskib964e932007-12-21 10:39:27 -0500207
208 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
Kumar Galafeadd5d2009-11-04 11:05:02 -0600209 SET_STD_PCIE_INFO(pci_info[num], 1);
210 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
211#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
robert lazarskib964e932007-12-21 10:39:27 -0500212 /* outbound memory */
Kumar Galafeadd5d2009-11-04 11:05:02 -0600213 pci_set_region(&pcie1_hose.regions[0],
214 CONFIG_SYS_PCIE1_MEM_BUS2,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215 CONFIG_SYS_PCIE1_MEM_PHYS2,
216 CONFIG_SYS_PCIE1_MEM_SIZE2,
robert lazarskib964e932007-12-21 10:39:27 -0500217 PCI_REGION_MEM);
Kumar Galafeadd5d2009-11-04 11:05:02 -0600218
219 pcie1_hose.region_count = 1;
robert lazarskib964e932007-12-21 10:39:27 -0500220#endif
Kumar Galafeadd5d2009-11-04 11:05:02 -0600221 printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
Peter Tyser64917ca2010-01-17 15:38:26 -0600222 pcie_ep ? "Endpoint" : "Root Complex",
Kumar Galafeadd5d2009-11-04 11:05:02 -0600223 pci_info[num].regs);
robert lazarskib964e932007-12-21 10:39:27 -0500224
Kumar Galafeadd5d2009-11-04 11:05:02 -0600225 first_free_busno = fsl_pci_init_port(&pci_info[num++],
226 &pcie1_hose, first_free_busno);
robert lazarskib964e932007-12-21 10:39:27 -0500227 } else {
228 printf (" PCIE1: disabled\n");
229 }
230
Kumar Galafeadd5d2009-11-04 11:05:02 -0600231 puts("\n");
robert lazarskib964e932007-12-21 10:39:27 -0500232#else
Kumar Galafeadd5d2009-11-04 11:05:02 -0600233 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
robert lazarskib964e932007-12-21 10:39:27 -0500234#endif
235
236#ifdef CONFIG_PCI1
Kumar Galafeadd5d2009-11-04 11:05:02 -0600237 pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
238 pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
239 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
240 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
robert lazarskib964e932007-12-21 10:39:27 -0500241
242 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
Kumar Galafeadd5d2009-11-04 11:05:02 -0600243 SET_STD_PCI_INFO(pci_info[num], 1);
244 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
245 printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
robert lazarskib964e932007-12-21 10:39:27 -0500246 (pci_32) ? 32 : 64,
247 (pci_speed == 33333000) ? "33" :
248 (pci_speed == 66666000) ? "66" : "unknown",
249 pci_clk_sel ? "sync" : "async",
250 pci_agent ? "agent" : "host",
251 pci_arb ? "arbiter" : "external-arbiter",
Kumar Galafeadd5d2009-11-04 11:05:02 -0600252 pci_info[num].regs);
robert lazarskib964e932007-12-21 10:39:27 -0500253
Kumar Galafeadd5d2009-11-04 11:05:02 -0600254 first_free_busno = fsl_pci_init_port(&pci_info[num++],
255 &pci1_hose, first_free_busno);
robert lazarskib964e932007-12-21 10:39:27 -0500256 } else {
Kumar Galafeadd5d2009-11-04 11:05:02 -0600257 printf (" PCI: disabled\n");
robert lazarskib964e932007-12-21 10:39:27 -0500258 }
Kumar Galafeadd5d2009-11-04 11:05:02 -0600259
260 puts("\n");
robert lazarskib964e932007-12-21 10:39:27 -0500261#else
Kumar Galafeadd5d2009-11-04 11:05:02 -0600262 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
robert lazarskib964e932007-12-21 10:39:27 -0500263#endif
264
265#ifdef CONFIG_PCI2
robert lazarskib964e932007-12-21 10:39:27 -0500266 if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
Kumar Galafeadd5d2009-11-04 11:05:02 -0600267 SET_STD_PCI_INFO(pci_info[num], 2);
268 pci_agent = fsl_setup_hose(&pci2_hose, pci_info[num].regs);
robert lazarskib964e932007-12-21 10:39:27 -0500269
Kumar Galafeadd5d2009-11-04 11:05:02 -0600270 puts (" PCI2\n");
271 first_free_busno = fsl_pci_init_port(&pci_info[num++],
272 &pci1_hose, first_free_busno);
robert lazarskib964e932007-12-21 10:39:27 -0500273 } else {
274 printf (" PCI2: disabled\n");
275 }
Kumar Galafeadd5d2009-11-04 11:05:02 -0600276 puts("\n");
robert lazarskib964e932007-12-21 10:39:27 -0500277#else
Kumar Galafeadd5d2009-11-04 11:05:02 -0600278 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
robert lazarskib964e932007-12-21 10:39:27 -0500279#endif
280}
281
282
283int last_stage_init(void)
284{
Wolfgang Denkd3a65322008-01-10 00:55:14 +0100285 int ic = icache_status ();
robert lazarskib964e932007-12-21 10:39:27 -0500286 printf ("icache_status: %d\n", ic);
287 return 0;
288}
289
290#if defined(CONFIG_OF_BOARD_SETUP)
Kumar Gala2dba0de2008-10-21 08:28:33 -0500291void ft_board_setup(void *blob, bd_t *bd)
robert lazarskib964e932007-12-21 10:39:27 -0500292{
robert lazarskib964e932007-12-21 10:39:27 -0500293 ft_cpu_setup(blob, bd);
294
robert lazarskib964e932007-12-21 10:39:27 -0500295#ifdef CONFIG_PCI1
Kumar Gala2dba0de2008-10-21 08:28:33 -0500296 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
robert lazarskib964e932007-12-21 10:39:27 -0500297#endif
298#ifdef CONFIG_PCI2
Kumar Gala2dba0de2008-10-21 08:28:33 -0500299 ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
robert lazarskib964e932007-12-21 10:39:27 -0500300#endif
301#ifdef CONFIG_PCIE1
Kumar Gala2dba0de2008-10-21 08:28:33 -0500302 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
robert lazarskib964e932007-12-21 10:39:27 -0500303#endif
robert lazarskib964e932007-12-21 10:39:27 -0500304}
305#endif