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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +02002/*
3 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
4 *
5 * Derived from linux/arch/mips/bcm63xx/cpu.c:
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +02008 */
9
10#include <common.h>
Simon Glass9d922452017-05-17 17:18:03 -060011#include <dm.h>
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +020012#include <errno.h>
13#include <ram.h>
14#include <asm/io.h>
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +020015
Álvaro Fernández Rojas5a0efcf2017-05-16 18:39:02 +020016#define SDRAM_CFG_REG 0x0
17#define SDRAM_CFG_COL_SHIFT 4
18#define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
19#define SDRAM_CFG_ROW_SHIFT 6
20#define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
21#define SDRAM_CFG_32B_SHIFT 10
22#define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
23#define SDRAM_CFG_BANK_SHIFT 13
24#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
Álvaro Fernández Rojasa80bf5e2018-01-20 19:16:03 +010025#define SDRAM_6318_SPACE_SHIFT 4
26#define SDRAM_6318_SPACE_MASK (0xf << SDRAM_6318_SPACE_SHIFT)
Álvaro Fernández Rojas5a0efcf2017-05-16 18:39:02 +020027
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +020028#define MEMC_CFG_REG 0x4
29#define MEMC_CFG_32B_SHIFT 1
30#define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
31#define MEMC_CFG_COL_SHIFT 3
32#define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
33#define MEMC_CFG_ROW_SHIFT 6
34#define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
35
36#define DDR_CSEND_REG 0x8
37
38struct bmips_ram_priv;
39
40struct bmips_ram_hw {
41 ulong (*get_ram_size)(struct bmips_ram_priv *);
42};
43
44struct bmips_ram_priv {
45 void __iomem *regs;
Philippe Reynes3e4a68d2018-07-16 19:06:13 +020046 u32 force_size;
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +020047 const struct bmips_ram_hw *hw;
48};
49
Álvaro Fernández Rojasa80bf5e2018-01-20 19:16:03 +010050static ulong bcm6318_get_ram_size(struct bmips_ram_priv *priv)
51{
52 u32 val;
53
54 val = readl_be(priv->regs + SDRAM_CFG_REG);
55 val = (val & SDRAM_6318_SPACE_MASK) >> SDRAM_6318_SPACE_SHIFT;
56
57 return (1 << (val + 20));
58}
59
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +020060static ulong bcm6328_get_ram_size(struct bmips_ram_priv *priv)
61{
62 return readl_be(priv->regs + DDR_CSEND_REG) << 24;
63}
64
Álvaro Fernández Rojas21659612017-05-16 18:39:01 +020065static ulong bmips_dram_size(unsigned int cols, unsigned int rows,
66 unsigned int is_32b, unsigned int banks)
67{
68 rows += 11; /* 0 => 11 address bits ... 2 => 13 address bits */
69 cols += 8; /* 0 => 8 address bits ... 2 => 10 address bits */
70 is_32b += 1;
71
72 return 1 << (cols + rows + is_32b + banks);
73}
74
Álvaro Fernández Rojas5a0efcf2017-05-16 18:39:02 +020075static ulong bcm6338_get_ram_size(struct bmips_ram_priv *priv)
76{
77 unsigned int cols = 0, rows = 0, is_32b = 0, banks = 0;
78 u32 val;
79
80 val = readl_be(priv->regs + SDRAM_CFG_REG);
81 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
82 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
83 is_32b = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
84 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
85
86 return bmips_dram_size(cols, rows, is_32b, banks);
87}
88
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +020089static ulong bcm6358_get_ram_size(struct bmips_ram_priv *priv)
90{
Álvaro Fernández Rojas21659612017-05-16 18:39:01 +020091 unsigned int cols = 0, rows = 0, is_32b = 0;
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +020092 u32 val;
93
94 val = readl_be(priv->regs + MEMC_CFG_REG);
95 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
96 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
Álvaro Fernández Rojas21659612017-05-16 18:39:01 +020097 is_32b = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +020098
Álvaro Fernández Rojas21659612017-05-16 18:39:01 +020099 return bmips_dram_size(cols, rows, is_32b, 2);
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +0200100}
101
102static int bmips_ram_get_info(struct udevice *dev, struct ram_info *info)
103{
104 struct bmips_ram_priv *priv = dev_get_priv(dev);
105 const struct bmips_ram_hw *hw = priv->hw;
106
107 info->base = 0x80000000;
Philippe Reynes3e4a68d2018-07-16 19:06:13 +0200108 if (priv->force_size)
109 info->size = priv->force_size;
110 else
111 info->size = hw->get_ram_size(priv);
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +0200112
113 return 0;
114}
115
116static const struct ram_ops bmips_ram_ops = {
117 .get_info = bmips_ram_get_info,
118};
119
Álvaro Fernández Rojasa80bf5e2018-01-20 19:16:03 +0100120static const struct bmips_ram_hw bmips_ram_bcm6318 = {
121 .get_ram_size = bcm6318_get_ram_size,
122};
123
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +0200124static const struct bmips_ram_hw bmips_ram_bcm6328 = {
125 .get_ram_size = bcm6328_get_ram_size,
126};
127
Álvaro Fernández Rojas5a0efcf2017-05-16 18:39:02 +0200128static const struct bmips_ram_hw bmips_ram_bcm6338 = {
129 .get_ram_size = bcm6338_get_ram_size,
130};
131
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +0200132static const struct bmips_ram_hw bmips_ram_bcm6358 = {
133 .get_ram_size = bcm6358_get_ram_size,
134};
135
136static const struct udevice_id bmips_ram_ids[] = {
137 {
Álvaro Fernández Rojasa80bf5e2018-01-20 19:16:03 +0100138 .compatible = "brcm,bcm6318-mc",
139 .data = (ulong)&bmips_ram_bcm6318,
140 }, {
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +0200141 .compatible = "brcm,bcm6328-mc",
142 .data = (ulong)&bmips_ram_bcm6328,
143 }, {
Álvaro Fernández Rojas5a0efcf2017-05-16 18:39:02 +0200144 .compatible = "brcm,bcm6338-mc",
145 .data = (ulong)&bmips_ram_bcm6338,
146 }, {
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +0200147 .compatible = "brcm,bcm6358-mc",
148 .data = (ulong)&bmips_ram_bcm6358,
Álvaro Fernández Rojasb493a352017-05-11 11:01:29 +0200149 }, { /* sentinel */ }
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +0200150};
151
152static int bmips_ram_probe(struct udevice *dev)
153{
154 struct bmips_ram_priv *priv = dev_get_priv(dev);
155 const struct bmips_ram_hw *hw =
156 (const struct bmips_ram_hw *)dev_get_driver_data(dev);
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +0200157
Álvaro Fernández Rojas13a7bfe2018-03-22 19:39:38 +0100158 priv->regs = dev_remap_addr(dev);
159 if (!priv->regs)
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +0200160 return -EINVAL;
161
Philippe Reynes3e4a68d2018-07-16 19:06:13 +0200162 dev_read_u32(dev, "force-size", &priv->force_size);
163
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +0200164 priv->hw = hw;
165
166 return 0;
167}
168
169U_BOOT_DRIVER(bmips_ram) = {
170 .name = "bmips-mc",
171 .id = UCLASS_RAM,
172 .of_match = bmips_ram_ids,
173 .probe = bmips_ram_probe,
174 .priv_auto_alloc_size = sizeof(struct bmips_ram_priv),
175 .ops = &bmips_ram_ops,
Álvaro Fernández Rojas193030e2017-04-25 00:39:19 +0200176};