blob: 24acdcb2e6f47c1d54df207c6907095147c322ae [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wills Wang6a7b52b2016-03-16 16:59:59 +08002/*
3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
Wills Wang6a7b52b2016-03-16 16:59:59 +08004 */
5
6#include <common.h>
7#include <asm/io.h>
8#include <asm/addrspace.h>
9#include <asm/types.h>
10#include <mach/ar71xx_regs.h>
11#include <mach/ddr.h>
Wills Wang04583c62016-05-30 22:54:51 +080012#include <mach/ath79.h>
Wills Wang6a7b52b2016-03-16 16:59:59 +080013#include <debug_uart.h>
14
Wills Wang6a7b52b2016-03-16 16:59:59 +080015#ifdef CONFIG_DEBUG_UART_BOARD_INIT
16void board_debug_uart_init(void)
17{
18 void __iomem *regs;
19 u32 val;
20
21 regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
22 MAP_NOCACHE);
23
24 /*
25 * GPIO9 as input, GPIO10 as output
26 */
27 val = readl(regs + AR71XX_GPIO_REG_OE);
28 val &= ~AR933X_GPIO(9);
29 val |= AR933X_GPIO(10);
30 writel(val, regs + AR71XX_GPIO_REG_OE);
31
32 /*
33 * Enable UART, GPIO9 as UART_SI, GPIO10 as UART_SO
34 */
35 val = readl(regs + AR71XX_GPIO_REG_FUNC);
36 val |= AR933X_GPIO_FUNC_UART_EN | AR933X_GPIO_FUNC_RES_TRUE;
37 writel(val, regs + AR71XX_GPIO_REG_FUNC);
38}
39#endif
40
41int board_early_init_f(void)
42{
Wills Wang6a7b52b2016-03-16 16:59:59 +080043 ddr_init();
Wills Wang04583c62016-05-30 22:54:51 +080044 ath79_eth_reset();
Wills Wang6a7b52b2016-03-16 16:59:59 +080045 return 0;
46}