blob: 6d098d1fa2f5023e3b4cd3f77efe3283ef78def8 [file] [log] [blame]
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001/*
York Sun34e026f2014-03-27 17:54:47 -07002 * Copyright 2008, 2010-2014 Freescale Semiconductor, Inc.
Kumar Gala58e5e9a2008-08-26 15:01:29 -05003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala58e5e9a2008-08-26 15:01:29 -05005 */
6
7#include <common.h>
Kumar Gala79e4e642010-07-14 10:04:21 -05008#include <hwconfig.h>
York Sun5614e712013-09-30 09:22:09 -07009#include <fsl_ddr_sdram.h>
Kumar Gala58e5e9a2008-08-26 15:01:29 -050010
York Sun5614e712013-09-30 09:22:09 -070011#include <fsl_ddr.h>
Kumar Gala58e5e9a2008-08-26 15:01:29 -050012
Kumar Galadd50af22011-01-09 11:37:00 -060013/*
14 * Use our own stack based buffer before relocation to allow accessing longer
15 * hwconfig strings that might be in the environment before we've relocated.
16 * This is pretty fragile on both the use of stack and if the buffer is big
17 * enough. However we will get a warning from getenv_f for the later.
18 */
Kumar Galadd50af22011-01-09 11:37:00 -060019
Kumar Gala58e5e9a2008-08-26 15:01:29 -050020/* Board-specific functions defined in each board's ddr.c */
21extern void fsl_ddr_board_options(memctl_options_t *popts,
Haiying Wangdfb49102008-10-03 12:36:55 -040022 dimm_params_t *pdimm,
Kumar Gala58e5e9a2008-08-26 15:01:29 -050023 unsigned int ctrl_num);
24
York Sun4e573822011-08-26 11:32:43 -070025struct dynamic_odt {
York Sune1fd16b2011-01-10 12:03:00 +000026 unsigned int odt_rd_cfg;
27 unsigned int odt_wr_cfg;
28 unsigned int odt_rtt_norm;
29 unsigned int odt_rtt_wr;
York Sun4e573822011-08-26 11:32:43 -070030};
York Sune1fd16b2011-01-10 12:03:00 +000031
York Sun34e026f2014-03-27 17:54:47 -070032#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
York Sun4e573822011-08-26 11:32:43 -070033static const struct dynamic_odt single_Q[4] = {
York Sune1fd16b2011-01-10 12:03:00 +000034 { /* cs0 */
35 FSL_DDR_ODT_NEVER,
36 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
37 DDR3_RTT_20_OHM,
38 DDR3_RTT_120_OHM
39 },
40 { /* cs1 */
41 FSL_DDR_ODT_NEVER,
42 FSL_DDR_ODT_NEVER, /* tied high */
43 DDR3_RTT_OFF,
44 DDR3_RTT_120_OHM
45 },
46 { /* cs2 */
47 FSL_DDR_ODT_NEVER,
48 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
49 DDR3_RTT_20_OHM,
50 DDR3_RTT_120_OHM
51 },
52 { /* cs3 */
53 FSL_DDR_ODT_NEVER,
54 FSL_DDR_ODT_NEVER, /* tied high */
55 DDR3_RTT_OFF,
56 DDR3_RTT_120_OHM
57 }
58};
59
York Sun4e573822011-08-26 11:32:43 -070060static const struct dynamic_odt single_D[4] = {
York Sune1fd16b2011-01-10 12:03:00 +000061 { /* cs0 */
62 FSL_DDR_ODT_NEVER,
63 FSL_DDR_ODT_ALL,
64 DDR3_RTT_40_OHM,
65 DDR3_RTT_OFF
66 },
67 { /* cs1 */
68 FSL_DDR_ODT_NEVER,
69 FSL_DDR_ODT_NEVER,
70 DDR3_RTT_OFF,
71 DDR3_RTT_OFF
72 },
73 {0, 0, 0, 0},
74 {0, 0, 0, 0}
75};
76
York Sun4e573822011-08-26 11:32:43 -070077static const struct dynamic_odt single_S[4] = {
York Sune1fd16b2011-01-10 12:03:00 +000078 { /* cs0 */
79 FSL_DDR_ODT_NEVER,
80 FSL_DDR_ODT_ALL,
81 DDR3_RTT_40_OHM,
82 DDR3_RTT_OFF
83 },
84 {0, 0, 0, 0},
85 {0, 0, 0, 0},
86 {0, 0, 0, 0},
87};
88
York Sun4e573822011-08-26 11:32:43 -070089static const struct dynamic_odt dual_DD[4] = {
York Sune1fd16b2011-01-10 12:03:00 +000090 { /* cs0 */
91 FSL_DDR_ODT_NEVER,
92 FSL_DDR_ODT_SAME_DIMM,
93 DDR3_RTT_120_OHM,
94 DDR3_RTT_OFF
95 },
96 { /* cs1 */
97 FSL_DDR_ODT_OTHER_DIMM,
98 FSL_DDR_ODT_OTHER_DIMM,
99 DDR3_RTT_30_OHM,
100 DDR3_RTT_OFF
101 },
102 { /* cs2 */
103 FSL_DDR_ODT_NEVER,
104 FSL_DDR_ODT_SAME_DIMM,
105 DDR3_RTT_120_OHM,
106 DDR3_RTT_OFF
107 },
108 { /* cs3 */
109 FSL_DDR_ODT_OTHER_DIMM,
110 FSL_DDR_ODT_OTHER_DIMM,
111 DDR3_RTT_30_OHM,
112 DDR3_RTT_OFF
113 }
114};
115
York Sun4e573822011-08-26 11:32:43 -0700116static const struct dynamic_odt dual_DS[4] = {
York Sune1fd16b2011-01-10 12:03:00 +0000117 { /* cs0 */
118 FSL_DDR_ODT_NEVER,
119 FSL_DDR_ODT_SAME_DIMM,
120 DDR3_RTT_120_OHM,
121 DDR3_RTT_OFF
122 },
123 { /* cs1 */
124 FSL_DDR_ODT_OTHER_DIMM,
125 FSL_DDR_ODT_OTHER_DIMM,
126 DDR3_RTT_30_OHM,
127 DDR3_RTT_OFF
128 },
129 { /* cs2 */
130 FSL_DDR_ODT_OTHER_DIMM,
131 FSL_DDR_ODT_ALL,
132 DDR3_RTT_20_OHM,
133 DDR3_RTT_120_OHM
134 },
135 {0, 0, 0, 0}
136};
York Sun4e573822011-08-26 11:32:43 -0700137static const struct dynamic_odt dual_SD[4] = {
York Sune1fd16b2011-01-10 12:03:00 +0000138 { /* cs0 */
139 FSL_DDR_ODT_OTHER_DIMM,
140 FSL_DDR_ODT_ALL,
141 DDR3_RTT_20_OHM,
142 DDR3_RTT_120_OHM
143 },
144 {0, 0, 0, 0},
145 { /* cs2 */
146 FSL_DDR_ODT_NEVER,
147 FSL_DDR_ODT_SAME_DIMM,
148 DDR3_RTT_120_OHM,
149 DDR3_RTT_OFF
150 },
151 { /* cs3 */
152 FSL_DDR_ODT_OTHER_DIMM,
153 FSL_DDR_ODT_OTHER_DIMM,
154 DDR3_RTT_20_OHM,
155 DDR3_RTT_OFF
156 }
157};
158
York Sun4e573822011-08-26 11:32:43 -0700159static const struct dynamic_odt dual_SS[4] = {
York Sune1fd16b2011-01-10 12:03:00 +0000160 { /* cs0 */
161 FSL_DDR_ODT_OTHER_DIMM,
162 FSL_DDR_ODT_ALL,
163 DDR3_RTT_30_OHM,
164 DDR3_RTT_120_OHM
165 },
166 {0, 0, 0, 0},
167 { /* cs2 */
168 FSL_DDR_ODT_OTHER_DIMM,
169 FSL_DDR_ODT_ALL,
170 DDR3_RTT_30_OHM,
171 DDR3_RTT_120_OHM
172 },
173 {0, 0, 0, 0}
174};
175
York Sun4e573822011-08-26 11:32:43 -0700176static const struct dynamic_odt dual_D0[4] = {
York Sune1fd16b2011-01-10 12:03:00 +0000177 { /* cs0 */
178 FSL_DDR_ODT_NEVER,
179 FSL_DDR_ODT_SAME_DIMM,
180 DDR3_RTT_40_OHM,
181 DDR3_RTT_OFF
182 },
183 { /* cs1 */
184 FSL_DDR_ODT_NEVER,
185 FSL_DDR_ODT_NEVER,
186 DDR3_RTT_OFF,
187 DDR3_RTT_OFF
188 },
189 {0, 0, 0, 0},
190 {0, 0, 0, 0}
191};
192
York Sun4e573822011-08-26 11:32:43 -0700193static const struct dynamic_odt dual_0D[4] = {
York Sune1fd16b2011-01-10 12:03:00 +0000194 {0, 0, 0, 0},
195 {0, 0, 0, 0},
196 { /* cs2 */
197 FSL_DDR_ODT_NEVER,
198 FSL_DDR_ODT_SAME_DIMM,
199 DDR3_RTT_40_OHM,
200 DDR3_RTT_OFF
201 },
202 { /* cs3 */
203 FSL_DDR_ODT_NEVER,
204 FSL_DDR_ODT_NEVER,
205 DDR3_RTT_OFF,
206 DDR3_RTT_OFF
207 }
208};
209
York Sun4e573822011-08-26 11:32:43 -0700210static const struct dynamic_odt dual_S0[4] = {
York Sune1fd16b2011-01-10 12:03:00 +0000211 { /* cs0 */
212 FSL_DDR_ODT_NEVER,
213 FSL_DDR_ODT_CS,
214 DDR3_RTT_40_OHM,
215 DDR3_RTT_OFF
216 },
217 {0, 0, 0, 0},
218 {0, 0, 0, 0},
219 {0, 0, 0, 0}
220
221};
222
York Sun4e573822011-08-26 11:32:43 -0700223static const struct dynamic_odt dual_0S[4] = {
York Sune1fd16b2011-01-10 12:03:00 +0000224 {0, 0, 0, 0},
225 {0, 0, 0, 0},
226 { /* cs2 */
227 FSL_DDR_ODT_NEVER,
228 FSL_DDR_ODT_CS,
229 DDR3_RTT_40_OHM,
230 DDR3_RTT_OFF
231 },
232 {0, 0, 0, 0}
233
234};
235
York Sun4e573822011-08-26 11:32:43 -0700236static const struct dynamic_odt odt_unknown[4] = {
York Sune1fd16b2011-01-10 12:03:00 +0000237 { /* cs0 */
238 FSL_DDR_ODT_NEVER,
239 FSL_DDR_ODT_CS,
240 DDR3_RTT_120_OHM,
241 DDR3_RTT_OFF
242 },
243 { /* cs1 */
244 FSL_DDR_ODT_NEVER,
245 FSL_DDR_ODT_CS,
246 DDR3_RTT_120_OHM,
247 DDR3_RTT_OFF
248 },
249 { /* cs2 */
250 FSL_DDR_ODT_NEVER,
251 FSL_DDR_ODT_CS,
252 DDR3_RTT_120_OHM,
253 DDR3_RTT_OFF
254 },
255 { /* cs3 */
256 FSL_DDR_ODT_NEVER,
257 FSL_DDR_ODT_CS,
258 DDR3_RTT_120_OHM,
259 DDR3_RTT_OFF
260 }
261};
York Sun34e026f2014-03-27 17:54:47 -0700262#else /* CONFIG_SYS_FSL_DDR3 || CONFIG_SYS_FSL_DDR4 */
York Sun4e573822011-08-26 11:32:43 -0700263static const struct dynamic_odt single_Q[4] = {
264 {0, 0, 0, 0},
265 {0, 0, 0, 0},
266 {0, 0, 0, 0},
267 {0, 0, 0, 0}
268};
York Sune1fd16b2011-01-10 12:03:00 +0000269
York Sun4e573822011-08-26 11:32:43 -0700270static const struct dynamic_odt single_D[4] = {
271 { /* cs0 */
272 FSL_DDR_ODT_NEVER,
273 FSL_DDR_ODT_ALL,
274 DDR2_RTT_150_OHM,
275 DDR2_RTT_OFF
276 },
277 { /* cs1 */
278 FSL_DDR_ODT_NEVER,
279 FSL_DDR_ODT_NEVER,
280 DDR2_RTT_OFF,
281 DDR2_RTT_OFF
282 },
283 {0, 0, 0, 0},
284 {0, 0, 0, 0}
285};
286
287static const struct dynamic_odt single_S[4] = {
288 { /* cs0 */
289 FSL_DDR_ODT_NEVER,
290 FSL_DDR_ODT_ALL,
291 DDR2_RTT_150_OHM,
292 DDR2_RTT_OFF
293 },
294 {0, 0, 0, 0},
295 {0, 0, 0, 0},
296 {0, 0, 0, 0},
297};
298
299static const struct dynamic_odt dual_DD[4] = {
300 { /* cs0 */
301 FSL_DDR_ODT_OTHER_DIMM,
302 FSL_DDR_ODT_OTHER_DIMM,
303 DDR2_RTT_75_OHM,
304 DDR2_RTT_OFF
305 },
306 { /* cs1 */
307 FSL_DDR_ODT_NEVER,
308 FSL_DDR_ODT_NEVER,
309 DDR2_RTT_OFF,
310 DDR2_RTT_OFF
311 },
312 { /* cs2 */
313 FSL_DDR_ODT_OTHER_DIMM,
314 FSL_DDR_ODT_OTHER_DIMM,
315 DDR2_RTT_75_OHM,
316 DDR2_RTT_OFF
317 },
318 { /* cs3 */
319 FSL_DDR_ODT_NEVER,
320 FSL_DDR_ODT_NEVER,
321 DDR2_RTT_OFF,
322 DDR2_RTT_OFF
323 }
324};
325
326static const struct dynamic_odt dual_DS[4] = {
327 { /* cs0 */
328 FSL_DDR_ODT_OTHER_DIMM,
329 FSL_DDR_ODT_OTHER_DIMM,
330 DDR2_RTT_75_OHM,
331 DDR2_RTT_OFF
332 },
333 { /* cs1 */
334 FSL_DDR_ODT_NEVER,
335 FSL_DDR_ODT_NEVER,
336 DDR2_RTT_OFF,
337 DDR2_RTT_OFF
338 },
339 { /* cs2 */
340 FSL_DDR_ODT_OTHER_DIMM,
341 FSL_DDR_ODT_OTHER_DIMM,
342 DDR2_RTT_75_OHM,
343 DDR2_RTT_OFF
344 },
345 {0, 0, 0, 0}
346};
347
348static const struct dynamic_odt dual_SD[4] = {
349 { /* cs0 */
350 FSL_DDR_ODT_OTHER_DIMM,
351 FSL_DDR_ODT_OTHER_DIMM,
352 DDR2_RTT_75_OHM,
353 DDR2_RTT_OFF
354 },
355 {0, 0, 0, 0},
356 { /* cs2 */
357 FSL_DDR_ODT_OTHER_DIMM,
358 FSL_DDR_ODT_OTHER_DIMM,
359 DDR2_RTT_75_OHM,
360 DDR2_RTT_OFF
361 },
362 { /* cs3 */
363 FSL_DDR_ODT_NEVER,
364 FSL_DDR_ODT_NEVER,
365 DDR2_RTT_OFF,
366 DDR2_RTT_OFF
367 }
368};
369
370static const struct dynamic_odt dual_SS[4] = {
371 { /* cs0 */
372 FSL_DDR_ODT_OTHER_DIMM,
373 FSL_DDR_ODT_OTHER_DIMM,
374 DDR2_RTT_75_OHM,
375 DDR2_RTT_OFF
376 },
377 {0, 0, 0, 0},
378 { /* cs2 */
379 FSL_DDR_ODT_OTHER_DIMM,
380 FSL_DDR_ODT_OTHER_DIMM,
381 DDR2_RTT_75_OHM,
382 DDR2_RTT_OFF
383 },
384 {0, 0, 0, 0}
385};
386
387static const struct dynamic_odt dual_D0[4] = {
388 { /* cs0 */
389 FSL_DDR_ODT_NEVER,
390 FSL_DDR_ODT_ALL,
391 DDR2_RTT_150_OHM,
392 DDR2_RTT_OFF
393 },
394 { /* cs1 */
395 FSL_DDR_ODT_NEVER,
396 FSL_DDR_ODT_NEVER,
397 DDR2_RTT_OFF,
398 DDR2_RTT_OFF
399 },
400 {0, 0, 0, 0},
401 {0, 0, 0, 0}
402};
403
404static const struct dynamic_odt dual_0D[4] = {
405 {0, 0, 0, 0},
406 {0, 0, 0, 0},
407 { /* cs2 */
408 FSL_DDR_ODT_NEVER,
409 FSL_DDR_ODT_ALL,
410 DDR2_RTT_150_OHM,
411 DDR2_RTT_OFF
412 },
413 { /* cs3 */
414 FSL_DDR_ODT_NEVER,
415 FSL_DDR_ODT_NEVER,
416 DDR2_RTT_OFF,
417 DDR2_RTT_OFF
418 }
419};
420
421static const struct dynamic_odt dual_S0[4] = {
422 { /* cs0 */
423 FSL_DDR_ODT_NEVER,
424 FSL_DDR_ODT_CS,
425 DDR2_RTT_150_OHM,
426 DDR2_RTT_OFF
427 },
428 {0, 0, 0, 0},
429 {0, 0, 0, 0},
430 {0, 0, 0, 0}
431
432};
433
434static const struct dynamic_odt dual_0S[4] = {
435 {0, 0, 0, 0},
436 {0, 0, 0, 0},
437 { /* cs2 */
438 FSL_DDR_ODT_NEVER,
439 FSL_DDR_ODT_CS,
440 DDR2_RTT_150_OHM,
441 DDR2_RTT_OFF
442 },
443 {0, 0, 0, 0}
444
445};
446
447static const struct dynamic_odt odt_unknown[4] = {
448 { /* cs0 */
449 FSL_DDR_ODT_NEVER,
450 FSL_DDR_ODT_CS,
451 DDR2_RTT_75_OHM,
452 DDR2_RTT_OFF
453 },
454 { /* cs1 */
455 FSL_DDR_ODT_NEVER,
456 FSL_DDR_ODT_NEVER,
457 DDR2_RTT_OFF,
458 DDR2_RTT_OFF
459 },
460 { /* cs2 */
461 FSL_DDR_ODT_NEVER,
462 FSL_DDR_ODT_CS,
463 DDR2_RTT_75_OHM,
464 DDR2_RTT_OFF
465 },
466 { /* cs3 */
467 FSL_DDR_ODT_NEVER,
468 FSL_DDR_ODT_NEVER,
469 DDR2_RTT_OFF,
470 DDR2_RTT_OFF
471 }
472};
473#endif
York Sun89b78092012-10-08 07:44:27 +0000474
475/*
476 * Automatically seleect bank interleaving mode based on DIMMs
477 * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
478 * This function only deal with one or two slots per controller.
479 */
480static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
481{
482#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
483 if (pdimm[0].n_ranks == 4)
484 return FSL_DDR_CS0_CS1_CS2_CS3;
485 else if (pdimm[0].n_ranks == 2)
486 return FSL_DDR_CS0_CS1;
487#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
488#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
489 if (pdimm[0].n_ranks == 4)
490 return FSL_DDR_CS0_CS1_CS2_CS3;
491#endif
492 if (pdimm[0].n_ranks == 2) {
493 if (pdimm[1].n_ranks == 2)
494 return FSL_DDR_CS0_CS1_CS2_CS3;
495 else
496 return FSL_DDR_CS0_CS1;
497 }
498#endif
499 return 0;
500}
501
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530502unsigned int populate_memctl_options(int all_dimms_registered,
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500503 memctl_options_t *popts,
Haiying Wangdfb49102008-10-03 12:36:55 -0400504 dimm_params_t *pdimm,
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500505 unsigned int ctrl_num)
506{
507 unsigned int i;
Kumar Galadd50af22011-01-09 11:37:00 -0600508 char buffer[HWCONFIG_BUFFER_SIZE];
509 char *buf = NULL;
York Sun34e026f2014-03-27 17:54:47 -0700510#if defined(CONFIG_SYS_FSL_DDR3) || \
511 defined(CONFIG_SYS_FSL_DDR2) || \
512 defined(CONFIG_SYS_FSL_DDR4)
York Sun4e573822011-08-26 11:32:43 -0700513 const struct dynamic_odt *pdodt = odt_unknown;
Kumar Gala667bc172011-11-09 10:05:21 -0600514#endif
York Suncda1de22011-08-24 09:40:26 -0700515 ulong ddr_freq;
Kumar Galadd50af22011-01-09 11:37:00 -0600516
517 /*
518 * Extract hwconfig from environment since we have not properly setup
519 * the environment but need it for ddr config params
520 */
521 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
522 buf = buffer;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500523
York Sun34e026f2014-03-27 17:54:47 -0700524#if defined(CONFIG_SYS_FSL_DDR3) || \
525 defined(CONFIG_SYS_FSL_DDR2) || \
526 defined(CONFIG_SYS_FSL_DDR4)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500527 /* Chip select options. */
York Sun349689b2014-04-01 14:20:49 -0700528#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
529 switch (pdimm[0].n_ranks) {
530 case 1:
531 pdodt = single_S;
532 break;
533 case 2:
534 pdodt = single_D;
535 break;
536 case 4:
537 pdodt = single_Q;
538 break;
539 }
540#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
541 switch (pdimm[0].n_ranks) {
York Sun123922b2012-10-08 07:44:23 +0000542#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
York Sun349689b2014-04-01 14:20:49 -0700543 case 4:
544 pdodt = single_Q;
545 if (pdimm[1].n_ranks)
546 printf("Error: Quad- and Dual-rank DIMMs cannot be used together\n");
547 break;
York Sun123922b2012-10-08 07:44:23 +0000548#endif
York Sun349689b2014-04-01 14:20:49 -0700549 case 2:
550 switch (pdimm[1].n_ranks) {
York Sune1fd16b2011-01-10 12:03:00 +0000551 case 2:
York Sun349689b2014-04-01 14:20:49 -0700552 pdodt = dual_DD;
York Sune1fd16b2011-01-10 12:03:00 +0000553 break;
554 case 1:
York Sun349689b2014-04-01 14:20:49 -0700555 pdodt = dual_DS;
York Sune1fd16b2011-01-10 12:03:00 +0000556 break;
557 case 0:
York Sun349689b2014-04-01 14:20:49 -0700558 pdodt = dual_D0;
York Sune1fd16b2011-01-10 12:03:00 +0000559 break;
560 }
York Sun349689b2014-04-01 14:20:49 -0700561 break;
562 case 1:
563 switch (pdimm[1].n_ranks) {
564 case 2:
565 pdodt = dual_SD;
566 break;
567 case 1:
568 pdodt = dual_SS;
569 break;
570 case 0:
571 pdodt = dual_S0;
572 break;
573 }
574 break;
575 case 0:
576 switch (pdimm[1].n_ranks) {
577 case 2:
578 pdodt = dual_0D;
579 break;
580 case 1:
581 pdodt = dual_0S;
582 break;
583 }
584 break;
York Sune1fd16b2011-01-10 12:03:00 +0000585 }
York Sun349689b2014-04-01 14:20:49 -0700586#endif /* CONFIG_DIMM_SLOTS_PER_CTLR */
587#endif /* CONFIG_SYS_FSL_DDR2, 3, 4 */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500588
589 /* Pick chip-select local options. */
590 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
York Sun34e026f2014-03-27 17:54:47 -0700591#if defined(CONFIG_SYS_FSL_DDR3) || \
592 defined(CONFIG_SYS_FSL_DDR2) || \
593 defined(CONFIG_SYS_FSL_DDR4)
York Sune1fd16b2011-01-10 12:03:00 +0000594 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
595 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
596 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
597 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
598#else
599 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
600 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
601#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500602 popts->cs_local_opts[i].auto_precharge = 0;
603 }
604
605 /* Pick interleaving mode. */
606
607 /*
608 * 0 = no interleaving
609 * 1 = interleaving between 2 controllers
610 */
611 popts->memctl_interleaving = 0;
612
613 /*
614 * 0 = cacheline
615 * 1 = page
616 * 2 = (logical) bank
617 * 3 = superbank (only if CS interleaving is enabled)
618 */
619 popts->memctl_interleaving_mode = 0;
620
621 /*
622 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
623 * 1: page: bit to the left of the column bits selects the memctl
624 * 2: bank: bit to the left of the bank bits selects the memctl
625 * 3: superbank: bit to the left of the chip select selects the memctl
626 *
627 * NOTE: ba_intlv (rank interleaving) is independent of memory
628 * controller interleaving; it is only within a memory controller.
629 * Must use superbank interleaving if rank interleaving is used and
630 * memory controller interleaving is enabled.
631 */
632
633 /*
634 * 0 = no
635 * 0x40 = CS0,CS1
636 * 0x20 = CS2,CS3
637 * 0x60 = CS0,CS1 + CS2,CS3
638 * 0x04 = CS0,CS1,CS2,CS3
639 */
640 popts->ba_intlv_ctl = 0;
641
642 /* Memory Organization Parameters */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530643 popts->registered_dimm_en = all_dimms_registered;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500644
645 /* Operational Mode Paramters */
646
647 /* Pick ECC modes */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530648 popts->ecc_mode = 0; /* 0 = disabled, 1 = enabled */
York Sun47df8f02011-01-10 12:02:57 +0000649#ifdef CONFIG_DDR_ECC
650 if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
651 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530652 popts->ecc_mode = 1;
York Sun47df8f02011-01-10 12:02:57 +0000653 } else
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530654 popts->ecc_mode = 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500655#endif
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530656 popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500657
658 /*
659 * Choose DQS config
660 * 0 for DDR1
661 * 1 for DDR2
662 */
York Sun5614e712013-09-30 09:22:09 -0700663#if defined(CONFIG_SYS_FSL_DDR1)
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530664 popts->dqs_config = 0;
York Sun5614e712013-09-30 09:22:09 -0700665#elif defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530666 popts->dqs_config = 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500667#endif
668
669 /* Choose self-refresh during sleep. */
670 popts->self_refresh_in_sleep = 1;
671
672 /* Choose dynamic power management mode. */
673 popts->dynamic_power = 0;
674
York Sune090aa72011-05-27 07:25:48 +0800675 /*
676 * check first dimm for primary sdram width
677 * presuming all dimms are similar
678 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
679 */
York Sun5614e712013-09-30 09:22:09 -0700680#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
York Sun4c99cb92011-06-27 13:35:25 -0700681 if (pdimm[0].n_ranks != 0) {
682 if ((pdimm[0].data_width >= 64) && \
683 (pdimm[0].data_width <= 72))
684 popts->data_bus_width = 0;
685 else if ((pdimm[0].data_width >= 32) || \
686 (pdimm[0].data_width <= 40))
687 popts->data_bus_width = 1;
688 else {
689 panic("Error: data width %u is invalid!\n",
690 pdimm[0].data_width);
691 }
692 }
693#else
694 if (pdimm[0].n_ranks != 0) {
695 if (pdimm[0].primary_sdram_width == 64)
696 popts->data_bus_width = 0;
697 else if (pdimm[0].primary_sdram_width == 32)
698 popts->data_bus_width = 1;
699 else if (pdimm[0].primary_sdram_width == 16)
700 popts->data_bus_width = 2;
701 else {
702 panic("Error: primary sdram width %u is invalid!\n",
703 pdimm[0].primary_sdram_width);
704 }
705 }
706#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500707
York Sunb61e0612013-06-25 11:37:47 -0700708 popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0;
709
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500710 /* Choose burst length. */
York Sun34e026f2014-03-27 17:54:47 -0700711#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
Dave Liu22c9de02010-03-05 12:22:00 +0800712#if defined(CONFIG_E500MC)
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530713 popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */
Dave Liu22c9de02010-03-05 12:22:00 +0800714 popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
715#else
York Sun51d498f2011-05-27 07:25:51 +0800716 if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
717 /* 32-bit or 16-bit bus */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530718 popts->otf_burst_chop_en = 0;
York Sune090aa72011-05-27 07:25:48 +0800719 popts->burst_length = DDR_BL8;
720 } else {
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530721 popts->otf_burst_chop_en = 1; /* on-the-fly burst chop */
York Sune090aa72011-05-27 07:25:48 +0800722 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
723 }
Dave Liu22c9de02010-03-05 12:22:00 +0800724#endif
Dave Liuc360cea2009-03-14 12:48:30 +0800725#else
726 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
727#endif
728
729 /* Choose ddr controller address mirror mode */
York Sun34e026f2014-03-27 17:54:47 -0700730#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
Dave Liuc360cea2009-03-14 12:48:30 +0800731 popts->mirrored_dimm = pdimm[0].mirrored_dimm;
732#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500733
734 /* Global Timing Parameters. */
735 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
736
737 /* Pick a caslat override. */
738 popts->cas_latency_override = 0;
739 popts->cas_latency_override_value = 3;
740 if (popts->cas_latency_override) {
741 debug("using caslat override value = %u\n",
742 popts->cas_latency_override_value);
743 }
744
745 /* Decide whether to use the computed derated latency */
746 popts->use_derated_caslat = 0;
747
748 /* Choose an additive latency. */
749 popts->additive_latency_override = 0;
750 popts->additive_latency_override_value = 3;
751 if (popts->additive_latency_override) {
752 debug("using additive latency override value = %u\n",
753 popts->additive_latency_override_value);
754 }
755
756 /*
757 * 2T_EN setting
758 *
759 * Factors to consider for 2T_EN:
760 * - number of DIMMs installed
761 * - number of components, number of active ranks
762 * - how much time you want to spend playing around
763 */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530764 popts->twot_en = 0;
765 popts->threet_en = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500766
York Sune1fd16b2011-01-10 12:03:00 +0000767 /* for RDIMM, address parity enable */
768 popts->ap_en = 1;
769
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500770 /*
771 * BSTTOPRE precharge interval
772 *
773 * Set this to 0 for global auto precharge
York Sun34e026f2014-03-27 17:54:47 -0700774 * The value of 0x100 has been used for DDR1, DDR2, DDR3.
775 * It is not wrong. Any value should be OK. The performance depends on
776 * applications. There is no one good value for all.
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500777 */
778 popts->bstopre = 0x100;
779
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500780 /*
781 * Window for four activates -- tFAW
782 *
783 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
784 * FIXME: varies depending upon number of column addresses or data
785 * FIXME: width, was considering looking at pdimm->primary_sdram_width
786 */
York Sun5614e712013-09-30 09:22:09 -0700787#if defined(CONFIG_SYS_FSL_DDR1)
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530788 popts->tfaw_window_four_activates_ps = mclk_to_picos(1);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500789
York Sun5614e712013-09-30 09:22:09 -0700790#elif defined(CONFIG_SYS_FSL_DDR2)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500791 /*
792 * x4/x8; some datasheets have 35000
793 * x16 wide columns only? Use 50000?
794 */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530795 popts->tfaw_window_four_activates_ps = 37500;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500796
York Sun34e026f2014-03-27 17:54:47 -0700797#else
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530798 popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps;
Dave Liuc360cea2009-03-14 12:48:30 +0800799#endif
800 popts->zq_en = 0;
801 popts->wrlvl_en = 0;
York Sun34e026f2014-03-27 17:54:47 -0700802#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
Dave Liuc360cea2009-03-14 12:48:30 +0800803 /*
804 * due to ddr3 dimm is fly-by topology
805 * we suggest to enable write leveling to
806 * meet the tQDSS under different loading.
807 */
808 popts->wrlvl_en = 1;
york5fb8a8a2010-07-02 22:25:56 +0000809 popts->zq_en = 1;
Dave Liubdc9f7b2009-12-16 10:24:37 -0600810 popts->wrlvl_override = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500811#endif
812
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500813 /*
Haiying Wangc9ffd832008-10-03 12:37:10 -0400814 * Check interleaving configuration from environment.
815 * Please refer to doc/README.fsl-ddr for the detail.
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500816 *
817 * If memory controller interleaving is enabled, then the data
york076bff82010-07-02 22:25:52 +0000818 * bus widths must be programmed identically for all memory controllers.
Haiying Wangc9ffd832008-10-03 12:37:10 -0400819 *
York Sun6b1e1252014-02-10 13:59:44 -0800820 * Attempt to set all controllers to the same chip select
Haiying Wangc9ffd832008-10-03 12:37:10 -0400821 * interleaving mode. It will do a best effort to get the
822 * requested ranks interleaved together such that the result
823 * should be a subset of the requested configuration.
York Sun6b1e1252014-02-10 13:59:44 -0800824 *
825 * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
826 * with 256 Byte is enabled.
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500827 */
Kumar Gala1542fbd2009-02-06 09:56:34 -0600828#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
York Suna4c66502012-08-17 08:22:39 +0000829 if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
York Sun6b1e1252014-02-10 13:59:44 -0800830#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
831 ;
832#else
York Suna4c66502012-08-17 08:22:39 +0000833 goto done;
York Sun6b1e1252014-02-10 13:59:44 -0800834#endif
York Suna4c66502012-08-17 08:22:39 +0000835 if (pdimm[0].n_ranks == 0) {
836 printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
837 popts->memctl_interleaving = 0;
838 goto done;
Haiying Wangc9ffd832008-10-03 12:37:10 -0400839 }
York Suna4c66502012-08-17 08:22:39 +0000840 popts->memctl_interleaving = 1;
York Sun6b1e1252014-02-10 13:59:44 -0800841#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
842 popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING;
843 popts->memctl_interleaving = 1;
844 debug("256 Byte interleaving\n");
York Sun349689b2014-04-01 14:20:49 -0700845#else
York Suna4c66502012-08-17 08:22:39 +0000846 /*
847 * test null first. if CONFIG_HWCONFIG is not defined
848 * hwconfig_arg_cmp returns non-zero
849 */
850 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
851 "null", buf)) {
852 popts->memctl_interleaving = 0;
853 debug("memory controller interleaving disabled.\n");
854 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
855 "ctlr_intlv",
856 "cacheline", buf)) {
857 popts->memctl_interleaving_mode =
858 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
859 0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
860 popts->memctl_interleaving =
861 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
862 0 : 1;
863 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
864 "ctlr_intlv",
865 "page", buf)) {
866 popts->memctl_interleaving_mode =
867 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
868 0 : FSL_DDR_PAGE_INTERLEAVING;
869 popts->memctl_interleaving =
870 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
871 0 : 1;
872 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
873 "ctlr_intlv",
874 "bank", buf)) {
875 popts->memctl_interleaving_mode =
876 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
877 0 : FSL_DDR_BANK_INTERLEAVING;
878 popts->memctl_interleaving =
879 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
880 0 : 1;
881 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
882 "ctlr_intlv",
883 "superbank", buf)) {
884 popts->memctl_interleaving_mode =
885 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
886 0 : FSL_DDR_SUPERBANK_INTERLEAVING;
887 popts->memctl_interleaving =
888 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
889 0 : 1;
890#if (CONFIG_NUM_DDR_CONTROLLERS == 3)
891 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
892 "ctlr_intlv",
893 "3way_1KB", buf)) {
894 popts->memctl_interleaving_mode =
895 FSL_DDR_3WAY_1KB_INTERLEAVING;
896 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
897 "ctlr_intlv",
898 "3way_4KB", buf)) {
899 popts->memctl_interleaving_mode =
900 FSL_DDR_3WAY_4KB_INTERLEAVING;
901 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
902 "ctlr_intlv",
903 "3way_8KB", buf)) {
904 popts->memctl_interleaving_mode =
905 FSL_DDR_3WAY_8KB_INTERLEAVING;
906#elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
907 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
908 "ctlr_intlv",
909 "4way_1KB", buf)) {
910 popts->memctl_interleaving_mode =
911 FSL_DDR_4WAY_1KB_INTERLEAVING;
912 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
913 "ctlr_intlv",
914 "4way_4KB", buf)) {
915 popts->memctl_interleaving_mode =
916 FSL_DDR_4WAY_4KB_INTERLEAVING;
917 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
918 "ctlr_intlv",
919 "4way_8KB", buf)) {
920 popts->memctl_interleaving_mode =
921 FSL_DDR_4WAY_8KB_INTERLEAVING;
922#endif
923 } else {
924 popts->memctl_interleaving = 0;
925 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
926 }
York Sun349689b2014-04-01 14:20:49 -0700927#endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */
York Suna4c66502012-08-17 08:22:39 +0000928done:
York Sun349689b2014-04-01 14:20:49 -0700929#endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
Kumar Galadd50af22011-01-09 11:37:00 -0600930 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
Dave Liu3ad95de2009-11-12 07:26:37 +0800931 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
Kumar Gala79e4e642010-07-14 10:04:21 -0500932 /* test null first. if CONFIG_HWCONFIG is not defined,
Kumar Galadd50af22011-01-09 11:37:00 -0600933 * hwconfig_subarg_cmp_f returns non-zero */
934 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
935 "null", buf))
york076bff82010-07-02 22:25:52 +0000936 debug("bank interleaving disabled.\n");
Kumar Galadd50af22011-01-09 11:37:00 -0600937 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
938 "cs0_cs1", buf))
Haiying Wangc9ffd832008-10-03 12:37:10 -0400939 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
Kumar Galadd50af22011-01-09 11:37:00 -0600940 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
941 "cs2_cs3", buf))
Haiying Wangc9ffd832008-10-03 12:37:10 -0400942 popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
Kumar Galadd50af22011-01-09 11:37:00 -0600943 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
944 "cs0_cs1_and_cs2_cs3", buf))
Haiying Wangc9ffd832008-10-03 12:37:10 -0400945 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
Kumar Galadd50af22011-01-09 11:37:00 -0600946 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
947 "cs0_cs1_cs2_cs3", buf))
Haiying Wangc9ffd832008-10-03 12:37:10 -0400948 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
York Sun89b78092012-10-08 07:44:27 +0000949 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
950 "auto", buf))
951 popts->ba_intlv_ctl = auto_bank_intlv(pdimm);
Haiying Wangc9ffd832008-10-03 12:37:10 -0400952 else
york076bff82010-07-02 22:25:52 +0000953 printf("hwconfig has unrecognized parameter for bank_intlv.\n");
Haiying Wangc9ffd832008-10-03 12:37:10 -0400954 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
955 case FSL_DDR_CS0_CS1_CS2_CS3:
york076bff82010-07-02 22:25:52 +0000956#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
york5800e7a2010-07-02 22:25:53 +0000957 if (pdimm[0].n_ranks < 4) {
york076bff82010-07-02 22:25:52 +0000958 popts->ba_intlv_ctl = 0;
959 printf("Not enough bank(chip-select) for "
960 "CS0+CS1+CS2+CS3 on controller %d, "
York Suna4c66502012-08-17 08:22:39 +0000961 "interleaving disabled!\n", ctrl_num);
york076bff82010-07-02 22:25:52 +0000962 }
963#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
York Sun123922b2012-10-08 07:44:23 +0000964#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
965 if (pdimm[0].n_ranks == 4)
966 break;
967#endif
york5800e7a2010-07-02 22:25:53 +0000968 if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
york076bff82010-07-02 22:25:52 +0000969 popts->ba_intlv_ctl = 0;
970 printf("Not enough bank(chip-select) for "
971 "CS0+CS1+CS2+CS3 on controller %d, "
York Suna4c66502012-08-17 08:22:39 +0000972 "interleaving disabled!\n", ctrl_num);
york076bff82010-07-02 22:25:52 +0000973 }
974 if (pdimm[0].capacity != pdimm[1].capacity) {
975 popts->ba_intlv_ctl = 0;
976 printf("Not identical DIMM size for "
977 "CS0+CS1+CS2+CS3 on controller %d, "
York Suna4c66502012-08-17 08:22:39 +0000978 "interleaving disabled!\n", ctrl_num);
york076bff82010-07-02 22:25:52 +0000979 }
980#endif
981 break;
Haiying Wangc9ffd832008-10-03 12:37:10 -0400982 case FSL_DDR_CS0_CS1:
york5800e7a2010-07-02 22:25:53 +0000983 if (pdimm[0].n_ranks < 2) {
Haiying Wangc9ffd832008-10-03 12:37:10 -0400984 popts->ba_intlv_ctl = 0;
Ed Swarthout7008d262008-10-29 09:21:44 -0500985 printf("Not enough bank(chip-select) for "
york076bff82010-07-02 22:25:52 +0000986 "CS0+CS1 on controller %d, "
York Suna4c66502012-08-17 08:22:39 +0000987 "interleaving disabled!\n", ctrl_num);
Haiying Wangc9ffd832008-10-03 12:37:10 -0400988 }
989 break;
990 case FSL_DDR_CS2_CS3:
york076bff82010-07-02 22:25:52 +0000991#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
york5800e7a2010-07-02 22:25:53 +0000992 if (pdimm[0].n_ranks < 4) {
Haiying Wangc9ffd832008-10-03 12:37:10 -0400993 popts->ba_intlv_ctl = 0;
york076bff82010-07-02 22:25:52 +0000994 printf("Not enough bank(chip-select) for CS2+CS3 "
York Suna4c66502012-08-17 08:22:39 +0000995 "on controller %d, interleaving disabled!\n", ctrl_num);
Haiying Wangc9ffd832008-10-03 12:37:10 -0400996 }
york076bff82010-07-02 22:25:52 +0000997#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
york5800e7a2010-07-02 22:25:53 +0000998 if (pdimm[1].n_ranks < 2) {
york076bff82010-07-02 22:25:52 +0000999 popts->ba_intlv_ctl = 0;
1000 printf("Not enough bank(chip-select) for CS2+CS3 "
York Suna4c66502012-08-17 08:22:39 +00001001 "on controller %d, interleaving disabled!\n", ctrl_num);
york076bff82010-07-02 22:25:52 +00001002 }
1003#endif
Haiying Wangc9ffd832008-10-03 12:37:10 -04001004 break;
1005 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
york076bff82010-07-02 22:25:52 +00001006#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
york5800e7a2010-07-02 22:25:53 +00001007 if (pdimm[0].n_ranks < 4) {
york076bff82010-07-02 22:25:52 +00001008 popts->ba_intlv_ctl = 0;
1009 printf("Not enough bank(CS) for CS0+CS1 and "
1010 "CS2+CS3 on controller %d, "
York Suna4c66502012-08-17 08:22:39 +00001011 "interleaving disabled!\n", ctrl_num);
york076bff82010-07-02 22:25:52 +00001012 }
1013#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
york5800e7a2010-07-02 22:25:53 +00001014 if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
Haiying Wangc9ffd832008-10-03 12:37:10 -04001015 popts->ba_intlv_ctl = 0;
york076bff82010-07-02 22:25:52 +00001016 printf("Not enough bank(CS) for CS0+CS1 and "
1017 "CS2+CS3 on controller %d, "
York Suna4c66502012-08-17 08:22:39 +00001018 "interleaving disabled!\n", ctrl_num);
Haiying Wangc9ffd832008-10-03 12:37:10 -04001019 }
york076bff82010-07-02 22:25:52 +00001020#endif
Haiying Wangc9ffd832008-10-03 12:37:10 -04001021 break;
1022 default:
1023 popts->ba_intlv_ctl = 0;
1024 break;
1025 }
1026 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001027
Kumar Galadd50af22011-01-09 11:37:00 -06001028 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
1029 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
york7fd101c2010-07-02 22:25:54 +00001030 popts->addr_hash = 0;
Kumar Galadd50af22011-01-09 11:37:00 -06001031 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
1032 "true", buf))
york7fd101c2010-07-02 22:25:54 +00001033 popts->addr_hash = 1;
1034 }
1035
york5800e7a2010-07-02 22:25:53 +00001036 if (pdimm[0].n_ranks == 4)
1037 popts->quad_rank_present = 1;
1038
York Suncda1de22011-08-24 09:40:26 -07001039 ddr_freq = get_ddr_freq(0) / 1000000;
1040 if (popts->registered_dimm_en) {
1041 popts->rcw_override = 1;
1042 popts->rcw_1 = 0x000a5a00;
1043 if (ddr_freq <= 800)
1044 popts->rcw_2 = 0x00000000;
1045 else if (ddr_freq <= 1066)
1046 popts->rcw_2 = 0x00100000;
1047 else if (ddr_freq <= 1333)
1048 popts->rcw_2 = 0x00200000;
1049 else
1050 popts->rcw_2 = 0x00300000;
1051 }
1052
Haiying Wangdfb49102008-10-03 12:36:55 -04001053 fsl_ddr_board_options(popts, pdimm, ctrl_num);
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001054
1055 return 0;
1056}
york076bff82010-07-02 22:25:52 +00001057
1058void check_interleaving_options(fsl_ddr_info_t *pinfo)
1059{
York Suna4c66502012-08-17 08:22:39 +00001060 int i, j, k, check_n_ranks, intlv_invalid = 0;
1061 unsigned int check_intlv, check_n_row_addr, check_n_col_addr;
york076bff82010-07-02 22:25:52 +00001062 unsigned long long check_rank_density;
York Suna4c66502012-08-17 08:22:39 +00001063 struct dimm_params_s *dimm;
York Sun1d71efb2014-08-01 15:51:00 -07001064 int first_ctrl = pinfo->first_ctrl;
1065 int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
1066
york076bff82010-07-02 22:25:52 +00001067 /*
1068 * Check if all controllers are configured for memory
1069 * controller interleaving. Identical dimms are recommended. At least
York Suna4c66502012-08-17 08:22:39 +00001070 * the size, row and col address should be checked.
york076bff82010-07-02 22:25:52 +00001071 */
1072 j = 0;
York Sun1d71efb2014-08-01 15:51:00 -07001073 check_n_ranks = pinfo->dimm_params[first_ctrl][0].n_ranks;
1074 check_rank_density = pinfo->dimm_params[first_ctrl][0].rank_density;
1075 check_n_row_addr = pinfo->dimm_params[first_ctrl][0].n_row_addr;
1076 check_n_col_addr = pinfo->dimm_params[first_ctrl][0].n_col_addr;
1077 check_intlv = pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode;
1078 for (i = first_ctrl; i <= last_ctrl; i++) {
York Suna4c66502012-08-17 08:22:39 +00001079 dimm = &pinfo->dimm_params[i][0];
1080 if (!pinfo->memctl_opts[i].memctl_interleaving) {
1081 continue;
1082 } else if (((check_rank_density != dimm->rank_density) ||
1083 (check_n_ranks != dimm->n_ranks) ||
1084 (check_n_row_addr != dimm->n_row_addr) ||
1085 (check_n_col_addr != dimm->n_col_addr) ||
1086 (check_intlv !=
1087 pinfo->memctl_opts[i].memctl_interleaving_mode))){
1088 intlv_invalid = 1;
1089 break;
1090 } else {
york076bff82010-07-02 22:25:52 +00001091 j++;
1092 }
York Suna4c66502012-08-17 08:22:39 +00001093
york076bff82010-07-02 22:25:52 +00001094 }
York Suna4c66502012-08-17 08:22:39 +00001095 if (intlv_invalid) {
York Sun1d71efb2014-08-01 15:51:00 -07001096 for (i = first_ctrl; i <= last_ctrl; i++)
York Suna4c66502012-08-17 08:22:39 +00001097 pinfo->memctl_opts[i].memctl_interleaving = 0;
1098 printf("Not all DIMMs are identical. "
1099 "Memory controller interleaving disabled.\n");
1100 } else {
1101 switch (check_intlv) {
York Sun6b1e1252014-02-10 13:59:44 -08001102 case FSL_DDR_256B_INTERLEAVING:
York Suna4c66502012-08-17 08:22:39 +00001103 case FSL_DDR_CACHE_LINE_INTERLEAVING:
1104 case FSL_DDR_PAGE_INTERLEAVING:
1105 case FSL_DDR_BANK_INTERLEAVING:
1106 case FSL_DDR_SUPERBANK_INTERLEAVING:
York Sun349689b2014-04-01 14:20:49 -07001107#if (3 == CONFIG_NUM_DDR_CONTROLLERS)
York Suna4c66502012-08-17 08:22:39 +00001108 k = 2;
York Sun349689b2014-04-01 14:20:49 -07001109#else
York Suna4c66502012-08-17 08:22:39 +00001110 k = CONFIG_NUM_DDR_CONTROLLERS;
York Sun349689b2014-04-01 14:20:49 -07001111#endif
York Suna4c66502012-08-17 08:22:39 +00001112 break;
1113 case FSL_DDR_3WAY_1KB_INTERLEAVING:
1114 case FSL_DDR_3WAY_4KB_INTERLEAVING:
1115 case FSL_DDR_3WAY_8KB_INTERLEAVING:
1116 case FSL_DDR_4WAY_1KB_INTERLEAVING:
1117 case FSL_DDR_4WAY_4KB_INTERLEAVING:
1118 case FSL_DDR_4WAY_8KB_INTERLEAVING:
1119 default:
1120 k = CONFIG_NUM_DDR_CONTROLLERS;
1121 break;
1122 }
1123 debug("%d of %d controllers are interleaving.\n", j, k);
York Sun89b78092012-10-08 07:44:27 +00001124 if (j && (j != k)) {
York Sun1d71efb2014-08-01 15:51:00 -07001125 for (i = first_ctrl; i <= last_ctrl; i++)
york076bff82010-07-02 22:25:52 +00001126 pinfo->memctl_opts[i].memctl_interleaving = 0;
York Sun1d71efb2014-08-01 15:51:00 -07001127 if ((last_ctrl - first_ctrl) > 1)
1128 puts("Not all controllers have compatible interleaving mode. All disabled.\n");
York Suna4c66502012-08-17 08:22:39 +00001129 }
york076bff82010-07-02 22:25:52 +00001130 }
York Suna4c66502012-08-17 08:22:39 +00001131 debug("Checking interleaving options completed\n");
york076bff82010-07-02 22:25:52 +00001132}
Kumar Gala3dbd5d72011-01-09 14:06:28 -06001133
1134int fsl_use_spd(void)
1135{
1136 int use_spd = 0;
1137
1138#ifdef CONFIG_DDR_SPD
Kumar Galadd50af22011-01-09 11:37:00 -06001139 char buffer[HWCONFIG_BUFFER_SIZE];
1140 char *buf = NULL;
1141
1142 /*
1143 * Extract hwconfig from environment since we have not properly setup
1144 * the environment but need it for ddr config params
1145 */
1146 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
1147 buf = buffer;
1148
Kumar Gala3dbd5d72011-01-09 14:06:28 -06001149 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
Kumar Galadd50af22011-01-09 11:37:00 -06001150 if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
1151 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
Kumar Gala3dbd5d72011-01-09 14:06:28 -06001152 use_spd = 1;
Kumar Galadd50af22011-01-09 11:37:00 -06001153 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",
1154 "fixed", buf))
Kumar Gala3dbd5d72011-01-09 14:06:28 -06001155 use_spd = 0;
1156 else
1157 use_spd = 1;
1158 } else
1159 use_spd = 1;
1160#endif
1161
1162 return use_spd;
1163}