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Tom Warren9112ef82011-11-05 09:48:11 +00001/*
Allen Martin6b3a03e2013-03-16 18:58:06 +00002 * Copyright (c) 2010-2013 NVIDIA Corporation
Tom Warren9112ef82011-11-05 09:48:11 +00003 * With help from the mpc8xxx SPI driver
4 * With more help from omap3_spi SPI driver
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Tom Warren9112ef82011-11-05 09:48:11 +00007 */
8
9#include <common.h>
Simon Glassfda6fac2014-10-13 23:42:13 -060010#include <dm.h>
11#include <errno.h>
Tom Warren9112ef82011-11-05 09:48:11 +000012#include <asm/io.h>
13#include <asm/gpio.h>
Tom Warren9112ef82011-11-05 09:48:11 +000014#include <asm/arch/clock.h>
15#include <asm/arch/pinmux.h>
Tom Warren150c2492012-09-19 15:50:56 -070016#include <asm/arch-tegra/clk_rst.h>
Tom Warren150c2492012-09-19 15:50:56 -070017#include <spi.h>
Allen Martin8f1b46b2013-01-29 13:51:24 +000018#include <fdtdec.h>
Simon Glassfda6fac2014-10-13 23:42:13 -060019#include "tegra_spi.h"
Allen Martin8f1b46b2013-01-29 13:51:24 +000020
21DECLARE_GLOBAL_DATA_PTR;
Tom Warren9112ef82011-11-05 09:48:11 +000022
Allen Martin7a49ba62013-03-16 18:58:05 +000023#define SPI_CMD_GO (1 << 30)
24#define SPI_CMD_ACTIVE_SCLK_SHIFT 26
25#define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
26#define SPI_CMD_CK_SDA (1 << 21)
27#define SPI_CMD_ACTIVE_SDA_SHIFT 18
28#define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
29#define SPI_CMD_CS_POL (1 << 16)
30#define SPI_CMD_TXEN (1 << 15)
31#define SPI_CMD_RXEN (1 << 14)
32#define SPI_CMD_CS_VAL (1 << 13)
33#define SPI_CMD_CS_SOFT (1 << 12)
34#define SPI_CMD_CS_DELAY (1 << 9)
35#define SPI_CMD_CS3_EN (1 << 8)
36#define SPI_CMD_CS2_EN (1 << 7)
37#define SPI_CMD_CS1_EN (1 << 6)
38#define SPI_CMD_CS0_EN (1 << 5)
39#define SPI_CMD_BIT_LENGTH (1 << 4)
40#define SPI_CMD_BIT_LENGTH_MASK 0x0000001F
41
42#define SPI_STAT_BSY (1 << 31)
43#define SPI_STAT_RDY (1 << 30)
44#define SPI_STAT_RXF_FLUSH (1 << 29)
45#define SPI_STAT_TXF_FLUSH (1 << 28)
46#define SPI_STAT_RXF_UNR (1 << 27)
47#define SPI_STAT_TXF_OVF (1 << 26)
48#define SPI_STAT_RXF_EMPTY (1 << 25)
49#define SPI_STAT_RXF_FULL (1 << 24)
50#define SPI_STAT_TXF_EMPTY (1 << 23)
51#define SPI_STAT_TXF_FULL (1 << 22)
52#define SPI_STAT_SEL_TXRX_N (1 << 16)
53#define SPI_STAT_CUR_BLKCNT (1 << 15)
54
55#define SPI_TIMEOUT 1000
56#define TEGRA_SPI_MAX_FREQ 52000000
57
58struct spi_regs {
59 u32 command; /* SPI_COMMAND_0 register */
60 u32 status; /* SPI_STATUS_0 register */
61 u32 rx_cmp; /* SPI_RX_CMP_0 register */
62 u32 dma_ctl; /* SPI_DMA_CTL_0 register */
63 u32 tx_fifo; /* SPI_TX_FIFO_0 register */
64 u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */
65 u32 rx_fifo; /* SPI_RX_FIFO_0 register */
66};
67
Simon Glassfda6fac2014-10-13 23:42:13 -060068struct tegra20_sflash_priv {
Allen Martin7a49ba62013-03-16 18:58:05 +000069 struct spi_regs *regs;
Tom Warren9112ef82011-11-05 09:48:11 +000070 unsigned int freq;
71 unsigned int mode;
Allen Martin8f1b46b2013-01-29 13:51:24 +000072 int periph_id;
Allen Martin6b3a03e2013-03-16 18:58:06 +000073 int valid;
Simon Glassfda6fac2014-10-13 23:42:13 -060074 int last_transaction_us;
Tom Warren9112ef82011-11-05 09:48:11 +000075};
76
Simon Glassfda6fac2014-10-13 23:42:13 -060077int tegra20_sflash_cs_info(struct udevice *bus, unsigned int cs,
78 struct spi_cs_info *info)
Tom Warren9112ef82011-11-05 09:48:11 +000079{
Allen Martin00a27492012-08-31 08:30:00 +000080 /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
Simon Glassfda6fac2014-10-13 23:42:13 -060081 if (cs != 0)
82 return -ENODEV;
Tom Warren9112ef82011-11-05 09:48:11 +000083 else
Simon Glassfda6fac2014-10-13 23:42:13 -060084 return 0;
Tom Warren9112ef82011-11-05 09:48:11 +000085}
86
Simon Glassfda6fac2014-10-13 23:42:13 -060087static int tegra20_sflash_ofdata_to_platdata(struct udevice *bus)
Tom Warren9112ef82011-11-05 09:48:11 +000088{
Simon Glassfda6fac2014-10-13 23:42:13 -060089 struct tegra_spi_platdata *plat = bus->platdata;
90 const void *blob = gd->fdt_blob;
91 int node = bus->of_offset;
Tom Warren9112ef82011-11-05 09:48:11 +000092
Simon Glassfda6fac2014-10-13 23:42:13 -060093 plat->base = fdtdec_get_addr(blob, node, "reg");
94 plat->periph_id = clock_decode_periph_id(blob, node);
95
96 if (plat->periph_id == PERIPH_ID_NONE) {
97 debug("%s: could not decode periph id %d\n", __func__,
98 plat->periph_id);
99 return -FDT_ERR_NOTFOUND;
Tom Warren9112ef82011-11-05 09:48:11 +0000100 }
101
Simon Glassfda6fac2014-10-13 23:42:13 -0600102 /* Use 500KHz as a suitable default */
103 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
104 500000);
105 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
106 "spi-deactivate-delay", 0);
107 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
108 __func__, plat->base, plat->periph_id, plat->frequency,
109 plat->deactivate_delay_us);
Tom Warren9112ef82011-11-05 09:48:11 +0000110
Simon Glassfda6fac2014-10-13 23:42:13 -0600111 return 0;
Tom Warren9112ef82011-11-05 09:48:11 +0000112}
113
Simon Glassfda6fac2014-10-13 23:42:13 -0600114static int tegra20_sflash_probe(struct udevice *bus)
Tom Warren9112ef82011-11-05 09:48:11 +0000115{
Simon Glassfda6fac2014-10-13 23:42:13 -0600116 struct tegra_spi_platdata *plat = dev_get_platdata(bus);
117 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
Tom Warren9112ef82011-11-05 09:48:11 +0000118
Simon Glassfda6fac2014-10-13 23:42:13 -0600119 priv->regs = (struct spi_regs *)plat->base;
120
121 priv->last_transaction_us = timer_get_us();
122 priv->freq = plat->frequency;
123 priv->periph_id = plat->periph_id;
124
125 return 0;
Tom Warren9112ef82011-11-05 09:48:11 +0000126}
127
Simon Glassfda6fac2014-10-13 23:42:13 -0600128static int tegra20_sflash_claim_bus(struct udevice *bus)
Tom Warren9112ef82011-11-05 09:48:11 +0000129{
Simon Glassfda6fac2014-10-13 23:42:13 -0600130 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
131 struct spi_regs *regs = priv->regs;
Tom Warren9112ef82011-11-05 09:48:11 +0000132 u32 reg;
133
134 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
Simon Glassfda6fac2014-10-13 23:42:13 -0600135 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
136 priv->freq);
Tom Warren9112ef82011-11-05 09:48:11 +0000137
138 /* Clear stale status here */
139 reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
140 SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
141 writel(reg, &regs->status);
Allen Martin78f47b72013-03-16 18:58:07 +0000142 debug("%s: STATUS = %08x\n", __func__, readl(&regs->status));
Tom Warren9112ef82011-11-05 09:48:11 +0000143
144 /*
145 * Use sw-controlled CS, so we can clock in data after ReadID, etc.
146 */
Simon Glassfda6fac2014-10-13 23:42:13 -0600147 reg = (priv->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
148 if (priv->mode & 2)
Tom Warren9112ef82011-11-05 09:48:11 +0000149 reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
150 clrsetbits_le32(&regs->command, SPI_CMD_ACTIVE_SCLK_MASK |
151 SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
Allen Martin78f47b72013-03-16 18:58:07 +0000152 debug("%s: COMMAND = %08x\n", __func__, readl(&regs->command));
Tom Warren9112ef82011-11-05 09:48:11 +0000153
154 /*
Allen Martin00a27492012-08-31 08:30:00 +0000155 * SPI pins on Tegra20 are muxed - change pinmux later due to UART
Tom Warren9112ef82011-11-05 09:48:11 +0000156 * issue.
157 */
Stephen Warren70ad3752014-03-21 12:28:58 -0600158 pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
159 pinmux_tristate_disable(PMUX_PINGRP_LSPI);
160 pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
Simon Glass4560c7d2011-11-05 04:46:50 +0000161
Tom Warren9112ef82011-11-05 09:48:11 +0000162 return 0;
163}
164
Simon Glassfda6fac2014-10-13 23:42:13 -0600165static void spi_cs_activate(struct udevice *dev)
Tom Warren9112ef82011-11-05 09:48:11 +0000166{
Simon Glassfda6fac2014-10-13 23:42:13 -0600167 struct udevice *bus = dev->parent;
168 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
169 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
170
171 /* If it's too soon to do another transaction, wait */
172 if (pdata->deactivate_delay_us &&
173 priv->last_transaction_us) {
174 ulong delay_us; /* The delay completed so far */
175 delay_us = timer_get_us() - priv->last_transaction_us;
176 if (delay_us < pdata->deactivate_delay_us)
177 udelay(pdata->deactivate_delay_us - delay_us);
178 }
Tom Warren9112ef82011-11-05 09:48:11 +0000179
Tom Warren9112ef82011-11-05 09:48:11 +0000180 /* CS is negated on Tegra, so drive a 1 to get a 0 */
Simon Glassfda6fac2014-10-13 23:42:13 -0600181 setbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
Tom Warren9112ef82011-11-05 09:48:11 +0000182}
183
Simon Glassfda6fac2014-10-13 23:42:13 -0600184static void spi_cs_deactivate(struct udevice *dev)
Tom Warren9112ef82011-11-05 09:48:11 +0000185{
Simon Glassfda6fac2014-10-13 23:42:13 -0600186 struct udevice *bus = dev->parent;
187 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
188 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
Tom Warren9112ef82011-11-05 09:48:11 +0000189
190 /* CS is negated on Tegra, so drive a 0 to get a 1 */
Simon Glassfda6fac2014-10-13 23:42:13 -0600191 clrbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
192
193 /* Remember time of this transaction so we can honour the bus delay */
194 if (pdata->deactivate_delay_us)
195 priv->last_transaction_us = timer_get_us();
Tom Warren9112ef82011-11-05 09:48:11 +0000196}
197
Simon Glassfda6fac2014-10-13 23:42:13 -0600198static int tegra20_sflash_xfer(struct udevice *dev, unsigned int bitlen,
199 const void *data_out, void *data_in,
200 unsigned long flags)
Tom Warren9112ef82011-11-05 09:48:11 +0000201{
Simon Glassfda6fac2014-10-13 23:42:13 -0600202 struct udevice *bus = dev->parent;
203 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
204 struct spi_regs *regs = priv->regs;
Tom Warren9112ef82011-11-05 09:48:11 +0000205 u32 reg, tmpdout, tmpdin = 0;
206 const u8 *dout = data_out;
207 u8 *din = data_in;
208 int num_bytes;
209 int ret;
210
Simon Glassfda6fac2014-10-13 23:42:13 -0600211 debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
212 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
Tom Warren9112ef82011-11-05 09:48:11 +0000213 if (bitlen % 8)
214 return -1;
215 num_bytes = bitlen / 8;
216
217 ret = 0;
218
219 reg = readl(&regs->status);
220 writel(reg, &regs->status); /* Clear all SPI events via R/W */
221 debug("spi_xfer entry: STATUS = %08x\n", reg);
222
223 reg = readl(&regs->command);
224 reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
225 writel(reg, &regs->command);
226 debug("spi_xfer: COMMAND = %08x\n", readl(&regs->command));
227
228 if (flags & SPI_XFER_BEGIN)
Simon Glassfda6fac2014-10-13 23:42:13 -0600229 spi_cs_activate(dev);
Tom Warren9112ef82011-11-05 09:48:11 +0000230
231 /* handle data in 32-bit chunks */
232 while (num_bytes > 0) {
233 int bytes;
234 int is_read = 0;
235 int tm, i;
236
237 tmpdout = 0;
238 bytes = (num_bytes > 4) ? 4 : num_bytes;
239
240 if (dout != NULL) {
241 for (i = 0; i < bytes; ++i)
242 tmpdout = (tmpdout << 8) | dout[i];
243 }
244
245 num_bytes -= bytes;
246 if (dout)
247 dout += bytes;
248
249 clrsetbits_le32(&regs->command, SPI_CMD_BIT_LENGTH_MASK,
250 bytes * 8 - 1);
251 writel(tmpdout, &regs->tx_fifo);
252 setbits_le32(&regs->command, SPI_CMD_GO);
253
254 /*
255 * Wait for SPI transmit FIFO to empty, or to time out.
256 * The RX FIFO status will be read and cleared last
257 */
258 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
259 u32 status;
260
261 status = readl(&regs->status);
262
263 /* We can exit when we've had both RX and TX activity */
264 if (is_read && (status & SPI_STAT_TXF_EMPTY))
265 break;
266
267 if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
268 SPI_STAT_RDY)
269 tm++;
270
271 else if (!(status & SPI_STAT_RXF_EMPTY)) {
272 tmpdin = readl(&regs->rx_fifo);
273 is_read = 1;
274
275 /* swap bytes read in */
276 if (din != NULL) {
277 for (i = bytes - 1; i >= 0; --i) {
278 din[i] = tmpdin & 0xff;
279 tmpdin >>= 8;
280 }
281 din += bytes;
282 }
283 }
284 }
285
286 if (tm >= SPI_TIMEOUT)
287 ret = tm;
288
289 /* clear ACK RDY, etc. bits */
290 writel(readl(&regs->status), &regs->status);
291 }
292
293 if (flags & SPI_XFER_END)
Simon Glassfda6fac2014-10-13 23:42:13 -0600294 spi_cs_deactivate(dev);
Tom Warren9112ef82011-11-05 09:48:11 +0000295
296 debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
297 tmpdin, readl(&regs->status));
298
299 if (ret) {
300 printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);
301 return -1;
302 }
303
304 return 0;
305}
Simon Glassfda6fac2014-10-13 23:42:13 -0600306
307static int tegra20_sflash_set_speed(struct udevice *bus, uint speed)
308{
309 struct tegra_spi_platdata *plat = bus->platdata;
310 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
311
312 if (speed > plat->frequency)
313 speed = plat->frequency;
314 priv->freq = speed;
315 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
316
317 return 0;
318}
319
320static int tegra20_sflash_set_mode(struct udevice *bus, uint mode)
321{
322 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
323
324 priv->mode = mode;
325 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
326
327 return 0;
328}
329
330static const struct dm_spi_ops tegra20_sflash_ops = {
331 .claim_bus = tegra20_sflash_claim_bus,
332 .xfer = tegra20_sflash_xfer,
333 .set_speed = tegra20_sflash_set_speed,
334 .set_mode = tegra20_sflash_set_mode,
335 .cs_info = tegra20_sflash_cs_info,
336};
337
338static const struct udevice_id tegra20_sflash_ids[] = {
339 { .compatible = "nvidia,tegra20-sflash" },
340 { }
341};
342
343U_BOOT_DRIVER(tegra20_sflash) = {
344 .name = "tegra20_sflash",
345 .id = UCLASS_SPI,
346 .of_match = tegra20_sflash_ids,
347 .ops = &tegra20_sflash_ops,
348 .ofdata_to_platdata = tegra20_sflash_ofdata_to_platdata,
349 .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
350 .priv_auto_alloc_size = sizeof(struct tegra20_sflash_priv),
351 .per_child_auto_alloc_size = sizeof(struct spi_slave),
352 .probe = tegra20_sflash_probe,
353};