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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / fd671802b67a0ef37a06124fa2ce85f00aa22c6f / . / board / amcc / kilauea / kilauea.c
blob: 8767f758810165396573374888307e2e1a0ec6e7 [file] [log] [blame]
Stefan Roese566806c2007-10-05 17:11:30 +0200[diff] [blame]1/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <ppc4xx.h>
26#include <ppc405.h>
27#include <libfdt.h>
28#include <asm/processor.h>
29#include <asm-ppc/io.h>
30
31#if defined(CONFIG_PCI)
32#include <pci.h>
33#include <asm/4xx_pcie.h>
34#endif
35
36DECLARE_GLOBAL_DATA_PTR;
37
38extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
39
40void fpga_init(void)
41{
42 /*
43 * Set FPGA regs
44 */
45 out32(CFG_FPGA_BASE, 0xff570cc0);
46}
47
48/*
49 * Board early initialization function
50 */
51int board_early_init_f (void)
52{
53 u32 val;
54
55 /*--------------------------------------------------------------------+
56 | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
57 +--------------------------------------------------------------------+
58 +---------------------------------------------------------------------+
59 |Interrupt| Source | Pol. | Sensi.| Crit. |
60 +---------+-----------------------------------+-------+-------+-------+
61 | IRQ 00 | UART0 | High | Level | Non |
62 | IRQ 01 | UART1 | High | Level | Non |
63 | IRQ 02 | IIC0 | High | Level | Non |
64 | IRQ 03 | TBD | High | Level | Non |
65 | IRQ 04 | TBD | High | Level | Non |
66 | IRQ 05 | EBM | High | Level | Non |
67 | IRQ 06 | BGI | High | Level | Non |
68 | IRQ 07 | IIC1 | Rising| Edge | Non |
69 | IRQ 08 | SPI | High | Lvl/ed| Non |
70 | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
71 | IRQ 10 | MAL TX EOB | High | Level | Non |
72 | IRQ 11 | MAL RX EOB | High | Level | Non |
73 | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
74 | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
75 | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
76 | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
77 | IRQ 16 | PCIE0 AL | high | Level | Non |
78 | IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
79 | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
80 | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
81 | IRQ 20 | PCIE0 TCR | High | Level | Non |
82 | IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
83 | IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
84 | IRQ 23 | Security EIP-94 | High | Level | Non |
85 | IRQ 24 | EMAC0 interrupt | High | Level | Non |
86 | IRQ 25 | EMAC1 interrupt | High | Level | Non |
87 | IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
88 | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
89 | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
90 | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
91 | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
92 | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
93 |----------------------------------------------------------------------
94 | IRQ 32 | MAL Serr | High | Level | Non |
95 | IRQ 33 | MAL Txde | High | Level | Non |
96 | IRQ 34 | MAL Rxde | High | Level | Non |
97 | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
98 | IRQ 36 | PCIE0 DCR Error | High | Level | Non |
99 | IRQ 37 | EBC | High |Lvl Edg| Non |
100 | IRQ 38 | NDFC | High | Level | Non |
101 | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
102 | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
103 | IRQ 41 | PCIE1 AL | high | Level | Non |
104 | IRQ 42 | PCIE1 VPD access | rising| edge | Non |
105 | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
106 | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
107 | IRQ 45 | PCIE1 TCR | High | Level | Non |
108 | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
109 | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
110 | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
111 | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
112 | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
113 | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
114 | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
115 | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
116 | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
117 | IRQ 55 | Serial ROM | High | Level | Non |
118 | IRQ 56 | GPT Decrement Pulse | High | Level | Non |
119 | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
120 | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
121 | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
122 | IRQ 60 | EMAC0 Wake-up | High | Level | Non |
123 | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
124 | IRQ 62 | EMAC1 Wake-up | High | Level | Non |
125 |----------------------------------------------------------------------
126 | IRQ 64 | PE0 AL | High | Level | Non |
127 | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
128 | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
129 | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
130 | IRQ 68 | PE0 TCR | High | Level | Non |
131 | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
132 | IRQ 70 | PE0 DCR Error | High | Level | Non |
133 | IRQ 71 | Reserved | N/A | N/A | Non |
134 | IRQ 72 | PE1 AL | High | Level | Non |
135 | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
136 | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
137 | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
138 | IRQ 76 | PE1 TCR | High | Level | Non |
139 | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
140 | IRQ 78 | PE1 DCR Error | High | Level | Non |
141 | IRQ 79 | Reserved | N/A | N/A | Non |
142 | IRQ 80 | PE2 AL | High | Level | Non |
143 | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
144 | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
145 | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
146 | IRQ 84 | PE2 TCR | High | Level | Non |
147 | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
148 | IRQ 86 | PE2 DCR Error | High | Level | Non |
149 | IRQ 87 | Reserved | N/A | N/A | Non |
150 | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
151 | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
152 | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
153 | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
154 | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
155 | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
156 | IRQ 94 | Reserved | N/A | N/A | Non |
157 | IRQ 95 | Reserved | N/A | N/A | Non |
158 |---------------------------------------------------------------------
159 +---------+-----------------------------------+-------+-------+------*/
160 /*--------------------------------------------------------------------+
161 | Initialise UIC registers. Clear all interrupts. Disable all
162 | interrupts.
163 | Set critical interrupt values. Set interrupt polarities. Set
164 | interrupt trigger levels. Make bit 0 High priority. Clear all
165 | interrupts again.
166 +-------------------------------------------------------------------*/
167
168 mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
169 mtdcr (uic2er, 0x00000000); /* disable all interrupts */
170 mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
171 mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
172 mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
173 mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
174 mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
175 mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
176
177 mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
178 mtdcr (uic1er, 0x00000000); /* disable all interrupts */
179 mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
180 mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
181 mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
182 mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
183 mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
184 mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
185
186 mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
187 mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
188 /* Except cascade UIC0 and UIC1 */
189 mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
190 mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
191 mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
192 mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
193 mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
194 mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
195
196 /*
197 * Note: Some cores are still in reset when the chip starts, so
198 * take them out of reset
199 */
200 mtsdr(SDR0_SRST, 0);
201
202 fpga_init();
203
204 /* Configure 405EX for NAND usage */
205 val = SDR0_CUST0_MUX_NDFC_SEL |
206 SDR0_CUST0_NDFC_ENABLE |
207 SDR0_CUST0_NDFC_BW_8_BIT |
208 SDR0_CUST0_NRB_BUSY |
209 (0x80000000 >> (28 + CFG_NAND_CS));
210 mtsdr(SDR0_CUST0, val);
211
212 return 0;
213}
214
215int misc_init_r(void)
216{
217#ifdef CFG_ENV_IS_IN_FLASH
218 /* Monitor protection ON by default */
219 flash_protect(FLAG_PROTECT_SET,
220 -CFG_MONITOR_LEN,
221 0xffffffff,
222 &flash_info[0]);
223#endif
224
225 return 0;
226}
227
228int checkboard (void)
229{
230 char *s = getenv("serial#");
231
232 printf("Board: Kilauea - AMCC PPC405EX Evaluation Board");
233
234 if (s != NULL) {
235 puts(", serial# ");
236 puts(s);
237 }
238 putc('\n');
239
240 return (0);
241}
242
243/*************************************************************************
244 * pci_pre_init
245 *
246 * This routine is called just prior to registering the hose and gives
247 * the board the opportunity to check things. Returning a value of zero
248 * indicates that things are bad & PCI initialization should be aborted.
249 *
250 * Different boards may wish to customize the pci controller structure
251 * (add regions, override default access routines, etc) or perform
252 * certain pre-initialization actions.
253 *
254 ************************************************************************/
255#if defined(CONFIG_PCI)
256int pci_pre_init(struct pci_controller * hose )
257{
258 return 0;
259}
260#endif /* defined(CONFIG_PCI) */
261
262/*************************************************************************
263 * pci_target_init
264 *
265 * The bootstrap configuration provides default settings for the pci
266 * inbound map (PIM). But the bootstrap config choices are limited and
267 * may not be sufficient for a given board.
268 *
269 ************************************************************************/
270#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
271void pci_target_init(struct pci_controller * hose )
272{
273 /*-------------------------------------------------------------------+
274 * Disable everything
275 *-------------------------------------------------------------------*/
276 out32r( PCIX0_PIM0SA, 0 ); /* disable */
277 out32r( PCIX0_PIM1SA, 0 ); /* disable */
278 out32r( PCIX0_PIM2SA, 0 ); /* disable */
279 out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
280
281 /*-------------------------------------------------------------------+
282 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
283 * strapping options to not support sizes such as 128/256 MB.
284 *-------------------------------------------------------------------*/
285 out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
286 out32r( PCIX0_PIM0LAH, 0 );
287 out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
288
289 out32r( PCIX0_BAR0, 0 );
290
291 /*-------------------------------------------------------------------+
292 * Program the board's subsystem id/vendor id
293 *-------------------------------------------------------------------*/
294 out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
295 out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
296
297 out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
298}
299#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
300
301#ifdef CONFIG_PCI
302static int pcie_port_is_rootpoint(int port)
303{
304 return 1;
305}
306
307static struct pci_controller pcie_hose[2] = {{0},{0}};
308
309void pcie_setup_hoses(int busno)
310{
311 struct pci_controller *hose;
312 int i, bus;
313 bus = busno;
314 char *env;
315 unsigned int delay;
316
317 for (i = 0; i < 2; i++) {
318
319 if (pcie_port_is_rootpoint(i)) {
320 printf("PORT%d will be configured as root-complex\n", i);
321 if (ppc4xx_init_pcie_rootport(i)) {
322 printf("PCIE%d: initialization failed\n", i);
323 continue;
324 }
325 } else {
326 printf("PORT%d will be configured as endpoint\n", i);
327 if (ppc4xx_init_pcie_endport(i)) {
328 printf("PCIE%d: initialization failed\n", i);
329 continue;
330 }
331 }
332
333 hose = &pcie_hose[i];
334 hose->first_busno = bus;
335 hose->last_busno = bus;
336 hose->current_busno = bus;
337
338 /* setup mem resource */
339 pci_set_region(hose->regions + 0,
340 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
341 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
342 CFG_PCIE_MEMSIZE,
343 PCI_REGION_MEM);
344 hose->region_count = 1;
345 pci_register_hose(hose);
346
347 if (pcie_port_is_rootpoint(i))
348 ppc4xx_setup_pcie_rootpoint(hose, i);
349 else
350 ppc4xx_setup_pcie_endpoint(hose, i);
351
352 env = getenv("pciscandelay");
353 if (env != NULL) {
354 delay = simple_strtoul(env, NULL, 10);
355 if (delay > 5)
356 printf("Warning, expect noticable delay before PCIe"
357 "scan due to 'pciscandelay' value!\n");
358 mdelay(delay * 1000);
359 }
360
361 /*
362 * Config access can only go down stream
363 */
364 hose->last_busno = pci_hose_scan(hose);
365 bus = hose->last_busno + 1;
366 }
367}
368#endif
369
370#if defined(CONFIG_POST)
371/*
372 * Returns 1 if keys pressed to start the power-on long-running tests
373 * Called from board_init_f().
374 */
375int post_hotkeys_pressed(void)
376{
377 return 0; /* No hotkeys supported */
378}
379#endif /* CONFIG_POST */
380
381#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
382void ft_board_setup(void *blob, bd_t *bd)
383{
Stefan Roesefd671802007-10-11 11:15:59 +0200[diff] [blame^]384 u32 val[4];
385 int rc;
386
Stefan Roese566806c2007-10-05 17:11:30 +0200[diff] [blame]387 ft_cpu_setup(blob, bd);
Stefan Roesefd671802007-10-11 11:15:59 +0200[diff] [blame^]388
389 /* Fixup NOR mapping */
390 val[0] = 0; /* chip select number */
391 val[1] = 0; /* always 0 */
392 val[2] = gd->bd->bi_flashstart;
393 val[3] = gd->bd->bi_flashsize;
394 rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
395 val, sizeof(val), 1);
396 if (rc)
397 printf("Unable to update property NOR mapping, err=%s\n",
398 fdt_strerror(rc));
Stefan Roese566806c2007-10-05 17:11:30 +0200[diff] [blame]399}
400#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */