blob: 4f9cb5a7e5bbf13331d7e83bef8b41471bced994 [file] [log] [blame]
HeungJun, Kim89f95492012-01-16 21:13:05 +00001/*
2 * Copyright (C) 2011 Samsung Electronics
3 * Heungjun Kim <riverful.kim@samsung.com>
4 * Kyungmin Park <kyungmin.park@samsung.com>
Donghwa Lee51b1cd62012-04-05 19:36:27 +00005 * Donghwa Lee <dh09.lee@samsung.com>
HeungJun, Kim89f95492012-01-16 21:13:05 +00006 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
Donghwa Lee51b1cd62012-04-05 19:36:27 +000027#include <lcd.h>
HeungJun, Kim89f95492012-01-16 21:13:05 +000028#include <asm/io.h>
29#include <asm/arch/cpu.h>
30#include <asm/arch/gpio.h>
31#include <asm/arch/mmc.h>
32#include <asm/arch/clock.h>
Donghwa Lee51b1cd62012-04-05 19:36:27 +000033#include <asm/arch/clk.h>
34#include <asm/arch/mipi_dsim.h>
HeungJun, Kim89f95492012-01-16 21:13:05 +000035#include <asm/arch/watchdog.h>
36#include <asm/arch/power.h>
37#include <pmic.h>
38#include <usb/s3c_udc.h>
Ɓukasz Majewski04ce68e2012-03-29 01:29:18 +000039#include <max8997_pmic.h>
Donghwa Lee90464972012-05-09 19:23:46 +000040#include <libtizen.h>
HeungJun, Kim89f95492012-01-16 21:13:05 +000041
42#include "setup.h"
43
44DECLARE_GLOBAL_DATA_PTR;
45
46unsigned int board_rev;
47
48#ifdef CONFIG_REVISION_TAG
49u32 get_board_rev(void)
50{
51 return board_rev;
52}
53#endif
54
55static void check_hw_revision(void);
56
Donghwa Lee3d024082012-04-26 18:52:26 +000057static int hwrevision(int rev)
58{
59 return (board_rev & 0xf) == rev;
60}
61
Lukasz Majewskia241d6e2012-08-06 14:41:10 +020062struct s3c_plat_otg_data s5pc210_otg_data;
63
HeungJun, Kim89f95492012-01-16 21:13:05 +000064int board_init(void)
65{
66 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
67
68 check_hw_revision();
69 printf("HW Revision:\t0x%x\n", board_rev);
70
71#if defined(CONFIG_PMIC)
72 pmic_init();
73#endif
74
75 return 0;
76}
77
78int dram_init(void)
79{
80 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
81 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
82
83 return 0;
84}
85
86void dram_init_banksize(void)
87{
88 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
89 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
90 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
91 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
92}
93
94static unsigned int get_hw_revision(void)
95{
96 struct exynos4_gpio_part1 *gpio =
97 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
98 int hwrev = 0;
99 int i;
100
101 /* hw_rev[3:0] == GPE1[3:0] */
102 for (i = 0; i < 4; i++) {
103 s5p_gpio_cfg_pin(&gpio->e1, i, GPIO_INPUT);
104 s5p_gpio_set_pull(&gpio->e1, i, GPIO_PULL_NONE);
105 }
106
107 udelay(1);
108
109 for (i = 0; i < 4; i++)
110 hwrev |= (s5p_gpio_get_value(&gpio->e1, i) << i);
111
112 debug("hwrev 0x%x\n", hwrev);
113
114 return hwrev;
115}
116
117static void check_hw_revision(void)
118{
119 int hwrev;
120
121 hwrev = get_hw_revision();
122
123 board_rev |= hwrev;
124}
125
126#ifdef CONFIG_DISPLAY_BOARDINFO
127int checkboard(void)
128{
129 puts("Board:\tTRATS\n");
130 return 0;
131}
132#endif
133
134#ifdef CONFIG_GENERIC_MMC
135int board_mmc_init(bd_t *bis)
136{
137 struct exynos4_gpio_part2 *gpio =
138 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
139 int i, err;
140
141 /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
142 s5p_gpio_direction_output(&gpio->k0, 2, 1);
143 s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
144
145 /*
146 * eMMC GPIO:
147 * SDR 8-bit@48MHz at MMC0
148 * GPK0[0] SD_0_CLK(2)
149 * GPK0[1] SD_0_CMD(2)
150 * GPK0[2] SD_0_CDn -> Not used
151 * GPK0[3:6] SD_0_DATA[0:3](2)
152 * GPK1[3:6] SD_0_DATA[0:3](3)
153 *
154 * DDR 4-bit@26MHz at MMC4
155 * GPK0[0] SD_4_CLK(3)
156 * GPK0[1] SD_4_CMD(3)
157 * GPK0[2] SD_4_CDn -> Not used
158 * GPK0[3:6] SD_4_DATA[0:3](3)
159 * GPK1[3:6] SD_4_DATA[4:7](4)
160 */
161 for (i = 0; i < 7; i++) {
162 if (i == 2)
163 continue;
164 /* GPK0[0:6] special function 2 */
165 s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
166 /* GPK0[0:6] pull disable */
167 s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
168 /* GPK0[0:6] drv 4x */
169 s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
170 }
171
172 for (i = 3; i < 7; i++) {
173 /* GPK1[3:6] special function 3 */
174 s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
175 /* GPK1[3:6] pull disable */
176 s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
177 /* GPK1[3:6] drv 4x */
178 s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
179 }
180
181 /*
182 * MMC device init
183 * mmc0 : eMMC (8-bit buswidth)
184 * mmc2 : SD card (4-bit buswidth)
185 */
186 err = s5p_mmc_init(0, 8);
187
188 /* T-flash detect */
189 s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
190 s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
191
192 /*
193 * Check the T-flash detect pin
194 * GPX3[4] T-flash detect pin
195 */
196 if (!s5p_gpio_get_value(&gpio->x3, 4)) {
197 /*
198 * SD card GPIO:
199 * GPK2[0] SD_2_CLK(2)
200 * GPK2[1] SD_2_CMD(2)
201 * GPK2[2] SD_2_CDn -> Not used
202 * GPK2[3:6] SD_2_DATA[0:3](2)
203 */
204 for (i = 0; i < 7; i++) {
205 if (i == 2)
206 continue;
207 /* GPK2[0:6] special function 2 */
208 s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
209 /* GPK2[0:6] pull disable */
210 s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
211 /* GPK2[0:6] drv 4x */
212 s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
213 }
214 err = s5p_mmc_init(2, 4);
215 }
216
217 return err;
218}
219#endif
220
221#ifdef CONFIG_USB_GADGET
222static int s5pc210_phy_control(int on)
223{
224 int ret = 0;
Ɓukasz Majewskia0f5b5a2012-04-25 23:30:18 +0000225 u32 val = 0;
HeungJun, Kim89f95492012-01-16 21:13:05 +0000226 struct pmic *p = get_pmic();
227
228 if (pmic_probe(p))
229 return -1;
230
231 if (on) {
Ɓukasz Majewski04ce68e2012-03-29 01:29:18 +0000232 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
233 ENSAFEOUT1, LDO_ON);
Ɓukasz Majewskia0f5b5a2012-04-25 23:30:18 +0000234 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
235 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
236
237 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
238 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
HeungJun, Kim89f95492012-01-16 21:13:05 +0000239 } else {
Ɓukasz Majewskia0f5b5a2012-04-25 23:30:18 +0000240 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
241 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
242
243 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
244 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
Ɓukasz Majewski04ce68e2012-03-29 01:29:18 +0000245 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
246 ENSAFEOUT1, LDO_OFF);
HeungJun, Kim89f95492012-01-16 21:13:05 +0000247 }
248
249 if (ret) {
Ɓukasz Majewski04ce68e2012-03-29 01:29:18 +0000250 puts("MAX8997 LDO setting error!\n");
HeungJun, Kim89f95492012-01-16 21:13:05 +0000251 return -1;
252 }
253
254 return 0;
255}
256
257struct s3c_plat_otg_data s5pc210_otg_data = {
258 .phy_control = s5pc210_phy_control,
259 .regs_phy = EXYNOS4_USBPHY_BASE,
260 .regs_otg = EXYNOS4_USBOTG_BASE,
261 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
262 .usb_flags = PHY0_SLEEP,
263};
Lukasz Majewskia241d6e2012-08-06 14:41:10 +0200264
265void board_usb_init(void)
266{
267 debug("USB_udc_probe\n");
268 s3c_udc_probe(&s5pc210_otg_data);
269}
HeungJun, Kim89f95492012-01-16 21:13:05 +0000270#endif
271
272static void pmic_reset(void)
273{
274 struct exynos4_gpio_part2 *gpio =
275 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
276
277 s5p_gpio_direction_output(&gpio->x0, 7, 1);
278 s5p_gpio_set_pull(&gpio->x2, 7, GPIO_PULL_NONE);
279}
280
281static void board_clock_init(void)
282{
283 struct exynos4_clock *clk =
284 (struct exynos4_clock *)samsung_get_base_clock();
285
286 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
287 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
288 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
289 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
290
291 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
292 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
293 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
294 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
295 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
296 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
297 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
298 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
299 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
300 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
301 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
302 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
303
304 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
305 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
306 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
307 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
308 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
309 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
310 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
311 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
312 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
313 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
314 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
315 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
316
317 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
318 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
319 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
320 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
321 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
322 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
323 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
324 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
325 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
326 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
327 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
328 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
329}
330
HeungJun, Kim89f95492012-01-16 21:13:05 +0000331static void board_power_init(void)
332{
333 struct exynos4_power *pwr =
334 (struct exynos4_power *)samsung_get_base_power();
335
336 /* PS HOLD */
337 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
338
339 /* Set power down */
340 writel(0, (unsigned int)&pwr->cam_configuration);
341 writel(0, (unsigned int)&pwr->tv_configuration);
342 writel(0, (unsigned int)&pwr->mfc_configuration);
343 writel(0, (unsigned int)&pwr->g3d_configuration);
344 writel(0, (unsigned int)&pwr->lcd1_configuration);
345 writel(0, (unsigned int)&pwr->gps_configuration);
346 writel(0, (unsigned int)&pwr->gps_alive_configuration);
347}
348
349static void board_uart_init(void)
350{
351 struct exynos4_gpio_part1 *gpio1 =
352 (struct exynos4_gpio_part1 *)samsung_get_base_gpio_part1();
353 struct exynos4_gpio_part2 *gpio2 =
354 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
355 int i;
356
HeungJun, Kim89f95492012-01-16 21:13:05 +0000357 /*
Minkyu Kang8aca4d62012-01-26 19:51:54 +0900358 * UART2 GPIOs
359 * GPA1CON[0] = UART_2_RXD(2)
360 * GPA1CON[1] = UART_2_TXD(2)
HeungJun, Kim89f95492012-01-16 21:13:05 +0000361 * GPA1CON[2] = I2C_3_SDA (3)
Minkyu Kang8aca4d62012-01-26 19:51:54 +0900362 * GPA1CON[3] = I2C_3_SCL (3)
HeungJun, Kim89f95492012-01-16 21:13:05 +0000363 */
Minkyu Kang8aca4d62012-01-26 19:51:54 +0900364
365 for (i = 0; i < 4; i++) {
HeungJun, Kim89f95492012-01-16 21:13:05 +0000366 s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
Minkyu Kang8aca4d62012-01-26 19:51:54 +0900367 s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2));
HeungJun, Kim89f95492012-01-16 21:13:05 +0000368 }
369
370 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
371 s5p_gpio_set_pull(&gpio2->y4, 7, GPIO_PULL_UP);
372 s5p_gpio_direction_output(&gpio2->y4, 7, 1);
373}
374
375int board_early_init_f(void)
376{
Minkyu Kang85948a82012-01-18 15:56:47 +0900377 wdt_stop();
HeungJun, Kim89f95492012-01-16 21:13:05 +0000378 pmic_reset();
379 board_clock_init();
380 board_uart_init();
381 board_power_init();
382
383 return 0;
384}
Donghwa Lee51b1cd62012-04-05 19:36:27 +0000385
386static void lcd_reset(void)
387{
388 struct exynos4_gpio_part2 *gpio2 =
389 (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
390
391 s5p_gpio_direction_output(&gpio2->y4, 5, 1);
392 udelay(10000);
393 s5p_gpio_direction_output(&gpio2->y4, 5, 0);
394 udelay(10000);
395 s5p_gpio_direction_output(&gpio2->y4, 5, 1);
396}
397
398static int lcd_power(void)
399{
400 int ret = 0;
401 struct pmic *p = get_pmic();
402
403 if (pmic_probe(p))
404 return 0;
405
406 /* LDO15 voltage: 2.2v */
407 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
408 /* LDO13 voltage: 3.0v */
409 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
410
411 if (ret) {
412 puts("MAX8997 LDO setting error!\n");
413 return -1;
414 }
415
416 return 0;
417}
418
419static struct mipi_dsim_config dsim_config = {
420 .e_interface = DSIM_VIDEO,
421 .e_virtual_ch = DSIM_VIRTUAL_CH_0,
422 .e_pixel_format = DSIM_24BPP_888,
423 .e_burst_mode = DSIM_BURST_SYNC_EVENT,
424 .e_no_data_lane = DSIM_DATA_LANE_4,
425 .e_byte_clk = DSIM_PLL_OUT_DIV8,
426 .hfp = 1,
427
428 .p = 3,
429 .m = 120,
430 .s = 1,
431
432 /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
433 .pll_stable_time = 500,
434
435 /* escape clk : 10MHz */
436 .esc_clk = 20 * 1000000,
437
438 /* stop state holding counter after bta change count 0 ~ 0xfff */
439 .stop_holding_cnt = 0x7ff,
440 /* bta timeout 0 ~ 0xff */
441 .bta_timeout = 0xff,
442 /* lp rx timeout 0 ~ 0xffff */
443 .rx_timeout = 0xffff,
444};
445
446static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = {
447 .lcd_panel_info = NULL,
448 .dsim_config = &dsim_config,
449};
450
451static struct mipi_dsim_lcd_device mipi_lcd_device = {
452 .name = "s6e8ax0",
453 .id = -1,
454 .bus_id = 0,
455 .platform_data = (void *)&s6e8ax0_platform_data,
456};
457
458static int mipi_power(void)
459{
460 int ret = 0;
461 struct pmic *p = get_pmic();
462
463 if (pmic_probe(p))
464 return 0;
465
466 /* LDO3 voltage: 1.1v */
467 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
468 /* LDO4 voltage: 1.8v */
469 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
470
471 if (ret) {
472 puts("MAX8997 LDO setting error!\n");
473 return -1;
474 }
475
476 return 0;
477}
478
Donghwa Leec2054562012-04-25 13:29:39 +0000479vidinfo_t panel_info = {
480 .vl_freq = 60,
481 .vl_col = 720,
482 .vl_row = 1280,
483 .vl_width = 720,
484 .vl_height = 1280,
485 .vl_clkp = CONFIG_SYS_HIGH,
486 .vl_hsp = CONFIG_SYS_LOW,
487 .vl_vsp = CONFIG_SYS_LOW,
488 .vl_dp = CONFIG_SYS_LOW,
489 .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */
490
491 /* s6e8ax0 Panel infomation */
492 .vl_hspw = 5,
493 .vl_hbpd = 10,
494 .vl_hfpd = 10,
495
496 .vl_vspw = 2,
497 .vl_vbpd = 1,
498 .vl_vfpd = 13,
499 .vl_cmd_allow_len = 0xf,
500
501 .win_id = 3,
502 .cfg_gpio = NULL,
503 .backlight_on = NULL,
504 .lcd_power_on = NULL, /* lcd_power_on in mipi dsi driver */
505 .reset_lcd = lcd_reset,
506 .dual_lcd_enabled = 0,
507
508 .init_delay = 0,
509 .power_on_delay = 0,
510 .reset_delay = 0,
511 .interface_mode = FIMD_RGB_INTERFACE,
512 .mipi_enabled = 1,
513};
514
Donghwa Lee51b1cd62012-04-05 19:36:27 +0000515void init_panel_info(vidinfo_t *vid)
516{
Donghwa Lee90464972012-05-09 19:23:46 +0000517 vid->logo_on = 1,
518 vid->resolution = HD_RESOLUTION,
519 vid->rgb_mode = MODE_RGB_P,
520
521#ifdef CONFIG_TIZEN
522 get_tizen_logo_info(vid);
523#endif
Donghwa Lee51b1cd62012-04-05 19:36:27 +0000524
Donghwa Lee3d024082012-04-26 18:52:26 +0000525 if (hwrevision(2))
526 mipi_lcd_device.reverse_panel = 1;
527
Donghwa Lee51b1cd62012-04-05 19:36:27 +0000528 strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
529 s6e8ax0_platform_data.lcd_power = lcd_power;
530 s6e8ax0_platform_data.mipi_power = mipi_power;
531 s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl;
532 s6e8ax0_platform_data.lcd_panel_info = (void *)vid;
533 exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
534 s6e8ax0_init();
535 exynos_set_dsim_platform_data(&s6e8ax0_platform_data);
536
537 setenv("lcdinfo", "lcd=s6e8ax0");
538}