wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2000 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <common.h> |
| 25 | #include <config.h> |
| 26 | #include <mpc8xx.h> |
| 27 | #include "fads.h" |
| 28 | |
| 29 | /* ------------------------------------------------------------------------- */ |
| 30 | |
| 31 | #define _NOT_USED_ 0xFFFFFFFF |
| 32 | |
| 33 | #if defined(CONFIG_DRAM_50MHZ) |
| 34 | /* 50MHz tables */ |
| 35 | const uint dram_60ns[] = |
| 36 | { 0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04, |
| 37 | 0x00ffec00, 0x37ffec47, 0xffffffff, 0xffffffff, |
| 38 | 0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c, |
| 39 | 0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44, |
| 40 | 0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00, |
| 41 | 0x3fffc847, 0xffffffff, 0xffffffff, 0xffffffff, |
| 42 | 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47, |
| 43 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 44 | 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c, |
| 45 | 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, |
| 46 | 0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff, |
| 47 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 48 | 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06, |
| 49 | 0xffffcc85, 0xffffcc05, 0xffffffff, 0xffffffff, |
| 50 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 51 | 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff }; |
| 52 | |
| 53 | const uint dram_70ns[] = |
| 54 | { 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04, |
| 55 | 0x00ffcc00, 0x37ffcc47, 0xffffffff, 0xffffffff, |
| 56 | 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04, |
| 57 | 0x00ffcc08, 0x0cffcc44, 0x00ffec0c, 0x03ffec00, |
| 58 | 0x00ffec44, 0x00ffcc08, 0x0cffcc44, 0x00ffec04, |
| 59 | 0x00ffec00, 0x3fffec47, 0xffffffff, 0xffffffff, |
| 60 | 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47, |
| 61 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 62 | 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c, |
| 63 | 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, |
| 64 | 0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff, |
| 65 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 66 | 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04, |
| 67 | 0x7fffcc06, 0xffffcc85, 0xffffcc05, 0xffffffff, |
| 68 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 69 | 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff }; |
| 70 | |
| 71 | const uint edo_60ns[] = |
| 72 | { 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04, |
| 73 | 0x00f3ec00, 0x37f7ec47, 0xffffffff, 0xffffffff, |
| 74 | 0x8fffec24, 0x0ffbec04, 0x0cf3ec04, 0x00f3ec0c, |
| 75 | 0x0cf3ec00, 0x00f3ec4c, 0x0cf3ec00, 0x00f3ec4c, |
| 76 | 0x0cf3ec00, 0x00f3ec44, 0x03f3ec00, 0x3ff7ec47, |
| 77 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 78 | 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47, |
| 79 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 80 | 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c, |
| 81 | 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, |
| 82 | 0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff, |
| 83 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 84 | 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06, |
| 85 | 0xffffcc85, 0xffffcc05, 0xffffffff, 0xffffffff, |
| 86 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 87 | 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff }; |
| 88 | |
| 89 | const uint edo_70ns[] = |
| 90 | { 0x8ffbcc24, 0x0ff3cc04, 0x0cf3cc04, 0x00f3cc04, |
| 91 | 0x00f3cc00, 0x37f7cc47, 0xffffffff, 0xffffffff, |
| 92 | 0x8fffcc24, 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc0c, |
| 93 | 0x03f3cc00, 0x00f3cc44, 0x00f3ec0c, 0x0cf3ec00, |
| 94 | 0x00f3ec4c, 0x03f3ec00, 0x00f3ec44, 0x00f3cc00, |
| 95 | 0x33f7cc47, 0xffffffff, 0xffffffff, 0xffffffff, |
| 96 | 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47, |
| 97 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 98 | 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c, |
| 99 | 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c, |
| 100 | 0x0cafcc00, 0x33bfcc47, 0xffffffff, 0xffffffff, |
| 101 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 102 | 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04, |
| 103 | 0x7fffcc04, 0xffffcc86, 0xffffcc05, 0xffffffff, |
| 104 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 105 | 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff }; |
| 106 | |
| 107 | #elif defined(CONFIG_DRAM_25MHZ) |
| 108 | |
| 109 | /* 25MHz tables */ |
| 110 | |
| 111 | const uint dram_60ns[] = |
| 112 | { 0x0fffcc04, 0x08ffcc00, 0x33ffcc47, 0xffffffff, |
| 113 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 114 | 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c, |
| 115 | 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c, |
| 116 | 0x08ffcc00, 0x33ffcc47, 0xffffffff, 0xffffffff, |
| 117 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 118 | 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, 0xffffffff, |
| 119 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 120 | 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, |
| 121 | 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, |
| 122 | 0x31bfcc43, 0xffffffff, 0xffffffff, 0xffffffff, |
| 123 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 124 | 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05, |
| 125 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 126 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 127 | 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff }; |
| 128 | |
| 129 | const uint dram_70ns[] = |
| 130 | { 0x0fffec04, 0x08ffec04, 0x00ffec00, 0x3fffcc47, |
| 131 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 132 | 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c, |
| 133 | 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c, |
| 134 | 0x08ffcc00, 0x33ffcc47, 0xffffffff, 0xffffffff, |
| 135 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 136 | 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, 0xffffffff, |
| 137 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 138 | 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, |
| 139 | 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00, |
| 140 | 0x31bfcc43, 0xffffffff, 0xffffffff, 0xffffffff, |
| 141 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 142 | 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05, |
| 143 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 144 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 145 | 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff }; |
| 146 | |
| 147 | const uint edo_60ns[] = |
| 148 | { 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47, |
| 149 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 150 | 0x0ffbcc04, 0x09f3cc0c, 0x09f3cc0c, 0x09f3cc0c, |
| 151 | 0x08f3cc00, 0x3ff7cc47, 0xffffffff, 0xffffffff, |
| 152 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 153 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 154 | 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47, |
| 155 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 156 | 0x0fefcc04, 0x08afcc00, 0x07afcc48, 0x08afcc48, |
| 157 | 0x08afcc48, 0x39bfcc47, 0xffffffff, 0xffffffff, |
| 158 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 159 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 160 | 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05, |
| 161 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 162 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 163 | 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff }; |
| 164 | |
| 165 | const uint edo_70ns[] = |
| 166 | { 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47, |
| 167 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 168 | 0x0ffbec04, 0x08f3ec04, 0x03f3ec48, 0x08f3cc00, |
| 169 | 0x0ff3cc4c, 0x08f3cc00, 0x0ff3cc4c, 0x08f3cc00, |
| 170 | 0x3ff7cc47, 0xffffffff, 0xffffffff, 0xffffffff, |
| 171 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 172 | 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47, |
| 173 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 174 | 0x0fefcc04, 0x08afcc00, 0x07afcc4c, 0x08afcc00, |
| 175 | 0x07afcc4c, 0x08afcc00, 0x07afcc4c, 0x08afcc00, |
| 176 | 0x37bfcc47, 0xffffffff, 0xffffffff, 0xffffffff, |
| 177 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 178 | 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05, |
| 179 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 180 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 181 | 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff }; |
| 182 | |
| 183 | |
| 184 | #else |
| 185 | #error dram not correct defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ |
| 186 | #endif |
| 187 | |
| 188 | /* ------------------------------------------------------------------------- */ |
| 189 | |
| 190 | |
| 191 | /* |
| 192 | * Check Board Identity: |
| 193 | */ |
| 194 | |
| 195 | int checkboard (void) |
| 196 | { |
| 197 | uint k; |
| 198 | |
| 199 | puts ("Board: "); |
| 200 | |
| 201 | #ifdef CONFIG_FADS |
| 202 | k = (*((uint *)BCSR3) >> 24) & 0x3f; |
| 203 | |
| 204 | switch(k) { |
| 205 | case 0x03 : |
| 206 | case 0x20 : |
| 207 | case 0x21 : |
| 208 | case 0x22 : |
| 209 | case 0x23 : |
| 210 | case 0x24 : |
| 211 | case 0x3f : |
| 212 | puts ("FADS"); |
| 213 | break; |
| 214 | |
| 215 | default : |
| 216 | printf("unknown board (0x%02x)\n", k); |
| 217 | return -1; |
| 218 | } |
| 219 | |
| 220 | printf(" with db "); |
| 221 | |
| 222 | switch(k) { |
| 223 | case 0x03 : |
| 224 | puts ("MPC823"); |
| 225 | break; |
| 226 | case 0x20 : |
| 227 | puts ("MPC801"); |
| 228 | break; |
| 229 | case 0x21 : |
| 230 | puts ("MPC850"); |
| 231 | break; |
| 232 | case 0x22 : |
| 233 | puts ("MPC821, MPC860 / MPC860SAR / MPC860T"); |
| 234 | break; |
| 235 | case 0x23 : |
| 236 | puts ("MPC860SAR"); |
| 237 | break; |
| 238 | case 0x24 : |
| 239 | puts ("MPC860T"); |
| 240 | break; |
| 241 | case 0x3f : |
| 242 | puts ("MPC850SAR"); |
| 243 | break; |
| 244 | } |
| 245 | |
| 246 | printf(" rev "); |
| 247 | |
| 248 | k = (((*((uint *)BCSR3) >> 23) & 1) << 3) |
| 249 | | (((*((uint *)BCSR3) >> 19) & 1) << 2) |
| 250 | | (((*((uint *)BCSR3) >> 16) & 3)); |
| 251 | |
| 252 | switch(k) { |
| 253 | case 0x01 : |
| 254 | puts ("ENG or PILOT\n"); |
| 255 | break; |
| 256 | |
| 257 | default: |
| 258 | printf("unknown (0x%x)\n", k); |
| 259 | return -1; |
| 260 | } |
| 261 | |
| 262 | return 0; |
| 263 | #endif /* CONFIG_FADS */ |
| 264 | |
| 265 | #ifdef CONFIG_ADS |
| 266 | printf("ADS rev "); |
| 267 | |
| 268 | k = (((*((uint *)BCSR3) >> 23) & 1) << 3) |
| 269 | | (((*((uint *)BCSR3) >> 19) & 1) << 2) |
| 270 | | (((*((uint *)BCSR3) >> 16) & 3)); |
| 271 | |
| 272 | switch(k) { |
| 273 | case 0x00 : puts ("ENG - this board sucks, check the errata, not supported\n"); |
| 274 | return -1; |
| 275 | case 0x01 : puts ("PILOT - warning, read errata \n"); break; |
| 276 | case 0x02 : puts ("A - warning, read errata \n"); break; |
| 277 | case 0x03 : puts ("B \n"); break; |
| 278 | default : printf ("unknown revision (0x%x)\n", k); return -1; |
| 279 | } |
| 280 | |
| 281 | return 0; |
| 282 | #endif /* CONFIG_ADS */ |
| 283 | |
| 284 | } |
| 285 | |
| 286 | /* ------------------------------------------------------------------------- */ |
| 287 | int _draminit(uint base, uint noMbytes, uint edo, uint delay) |
| 288 | { |
| 289 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
| 290 | volatile memctl8xx_t *memctl = &immap->im_memctl; |
| 291 | |
| 292 | /* init upm */ |
| 293 | |
| 294 | switch(delay) |
| 295 | { |
| 296 | case 70: |
| 297 | { |
| 298 | if(edo) |
| 299 | { |
| 300 | upmconfig(UPMA, (uint *) edo_70ns, sizeof(edo_70ns)/sizeof(uint)); |
| 301 | } |
| 302 | else |
| 303 | { |
| 304 | upmconfig(UPMA, (uint *) dram_70ns, sizeof(dram_70ns)/sizeof(uint)); |
| 305 | } |
| 306 | |
| 307 | break; |
| 308 | } |
| 309 | |
| 310 | case 60: |
| 311 | { |
| 312 | if(edo) |
| 313 | { |
| 314 | upmconfig(UPMA, (uint *) edo_60ns, sizeof(edo_60ns)/sizeof(uint)); |
| 315 | } |
| 316 | else |
| 317 | { |
| 318 | upmconfig(UPMA, (uint *) dram_60ns, sizeof(dram_60ns)/sizeof(uint)); |
| 319 | } |
| 320 | |
| 321 | break; |
| 322 | } |
| 323 | |
| 324 | default : |
| 325 | return -1; |
| 326 | } |
| 327 | |
| 328 | memctl->memc_mptpr = 0x0400; /* divide by 16 */ |
| 329 | |
| 330 | switch(noMbytes) |
| 331 | { |
| 332 | |
| 333 | case 8: /* 8 Mbyte uses both CS3 and CS2 */ |
| 334 | { |
| 335 | memctl->memc_mamr = 0x13a01114; |
| 336 | memctl->memc_or3 = 0xffc00800; |
| 337 | memctl->memc_br3 = 0x00400081 + base; |
| 338 | memctl->memc_or2 = 0xffc00800; |
| 339 | break; |
| 340 | } |
| 341 | |
| 342 | case 4: /* 4 Mbyte uses only CS2 */ |
| 343 | { |
| 344 | memctl->memc_mamr = 0x13a01114; |
| 345 | memctl->memc_or2 = 0xffc00800; |
| 346 | break; |
| 347 | } |
| 348 | |
| 349 | case 32: /* 32 Mbyte uses both CS3 and CS2 */ |
| 350 | { |
| 351 | memctl->memc_mamr = 0x13b01114; |
| 352 | memctl->memc_or3 = 0xff000800; |
| 353 | memctl->memc_br3 = 0x01000081 + base; |
| 354 | memctl->memc_or2 = 0xff000800; |
| 355 | break; |
| 356 | } |
| 357 | |
| 358 | case 16: /* 16 Mbyte uses only CS2 */ |
| 359 | { |
| 360 | #ifdef CONFIG_ADS |
| 361 | memctl->memc_mamr = 0x60b21114; |
| 362 | #else |
| 363 | memctl->memc_mamr = 0x13b01114; |
| 364 | #endif |
| 365 | memctl->memc_or2 = 0xff000800; |
| 366 | break; |
| 367 | } |
| 368 | |
| 369 | default: |
| 370 | return -1; |
| 371 | } |
| 372 | |
| 373 | memctl->memc_br2 = 0x81 + base; /* use upma */ |
| 374 | return 0; |
| 375 | } |
| 376 | |
| 377 | /* ------------------------------------------------------------------------- */ |
| 378 | |
| 379 | void _dramdisable(void) |
| 380 | { |
| 381 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
| 382 | volatile memctl8xx_t *memctl = &immap->im_memctl; |
| 383 | |
| 384 | memctl->memc_br2 = 0x00000000; |
| 385 | memctl->memc_br3 = 0x00000000; |
| 386 | |
| 387 | /* maybe we should turn off upma here or something */ |
| 388 | } |
| 389 | |
| 390 | #if defined(CONFIG_SDRAM_100MHZ) |
| 391 | |
| 392 | /* ------------------------------------------------------------------------- */ |
| 393 | /* sdram table by Dan Malek */ |
| 394 | |
| 395 | /* This has the stretched early timing so the 50 MHz |
| 396 | * processor can make the 100 MHz timing. This will |
| 397 | * work at all processor speeds. |
| 398 | */ |
| 399 | |
| 400 | #define SDRAM_MPTPRVALUE 0x0400 |
| 401 | |
| 402 | #define SDRAM_MBMRVALUE0 0xc3802114 /* (16-14) 50 MHz */ |
| 403 | #define SDRAM_MBMRVALUE1 SDRAM_MBMRVALUE0 |
| 404 | |
| 405 | #define SDRAM_OR4VALUE 0xffc00a00 |
| 406 | #define SDRAM_BR4VALUE 0x000000c1 /* base address will be or:ed on */ |
| 407 | |
| 408 | #define SDRAM_MARVALUE 0x88 |
| 409 | |
| 410 | #define SDRAM_MCRVALUE0 0x80808111 /* run pattern 0x11 */ |
| 411 | #define SDRAM_MCRVALUE1 SDRAM_MCRVALUE0 |
| 412 | |
| 413 | |
| 414 | const uint sdram_table[] = |
| 415 | { |
| 416 | /* single read. (offset 0 in upm RAM) */ |
| 417 | 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x11adfc04, |
| 418 | 0xefbbbc00, 0x1ff77c45, 0xffffffff, 0xffffffff, |
| 419 | |
| 420 | /* burst read. (offset 8 in upm RAM) */ |
| 421 | 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x10adfc04, |
| 422 | 0xf0affc00, 0xf0affc00, 0xf1affc00, 0xefbbbc00, |
| 423 | 0x1ff77c45, 0xeffbbc04, 0x1ff77c34, 0xefeabc34, |
| 424 | 0x1fb57c35, 0xffffffff, 0xffffffff, 0xffffffff, |
| 425 | |
| 426 | /* single write. (offset 18 in upm RAM) */ |
| 427 | 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x01b93c04, |
| 428 | 0x1ff77c45, 0xffffffff, 0xffffffff, 0xffffffff, |
| 429 | |
| 430 | /* burst write. (offset 20 in upm RAM) */ |
| 431 | 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, |
| 432 | 0xf0affc00, 0xf0affc00, 0xe1bbbc04, 0x1ff77c45, |
| 433 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 434 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 435 | |
| 436 | /* refresh. (offset 30 in upm RAM) */ |
| 437 | 0xeffafc84, 0x1ff5fc04, 0xfffffc04, 0xfffffc04, |
| 438 | 0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff, |
| 439 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 440 | |
| 441 | /* exception. (offset 3c in upm RAM) */ |
| 442 | 0xeffffc06, 0x1ffffc07, 0xffffffff, 0xffffffff }; |
| 443 | |
| 444 | #elif defined(CONFIG_SDRAM_50MHZ) |
| 445 | |
| 446 | /* ------------------------------------------------------------------------- */ |
| 447 | /* sdram table stolen from the fads manual */ |
| 448 | /* for chip MB811171622A-100 */ |
| 449 | |
| 450 | /* this table is for 32-50MHz operation */ |
| 451 | |
| 452 | #define _not_used_ 0xffffffff |
| 453 | |
| 454 | #define SDRAM_MPTPRVALUE 0x0400 |
| 455 | |
| 456 | #define SDRAM_MBMRVALUE0 0x80802114 /* refresh at 32MHz */ |
| 457 | #define SDRAM_MBMRVALUE1 0x80802118 |
| 458 | |
| 459 | #define SDRAM_OR4VALUE 0xffc00a00 |
| 460 | #define SDRAM_BR4VALUE 0x000000c1 /* base address will be or:ed on */ |
| 461 | |
| 462 | #define SDRAM_MARVALUE 0x88 |
| 463 | |
| 464 | #define SDRAM_MCRVALUE0 0x80808105 |
| 465 | #define SDRAM_MCRVALUE1 0x80808130 |
| 466 | |
| 467 | const uint sdram_table[] = |
| 468 | { |
| 469 | /* single read. (offset 0 in upm RAM) */ |
| 470 | 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00, |
| 471 | 0x1ff77c47, |
| 472 | |
| 473 | /* MRS initialization (offset 5) */ |
| 474 | |
| 475 | 0x1ff77c34, 0xefeabc34, 0x1fb57c35, |
| 476 | |
| 477 | /* burst read. (offset 8 in upm RAM) */ |
| 478 | 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, |
| 479 | 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, |
| 480 | _not_used_, _not_used_, _not_used_, _not_used_, |
| 481 | _not_used_, _not_used_, _not_used_, _not_used_, |
| 482 | |
| 483 | /* single write. (offset 18 in upm RAM) */ |
| 484 | 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, |
| 485 | _not_used_, _not_used_, _not_used_, _not_used_, |
| 486 | |
| 487 | /* burst write. (offset 20 in upm RAM) */ |
| 488 | 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, |
| 489 | 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_, |
| 490 | _not_used_, _not_used_, _not_used_, _not_used_, |
| 491 | _not_used_, _not_used_, _not_used_, _not_used_, |
| 492 | |
| 493 | /* refresh. (offset 30 in upm RAM) */ |
| 494 | 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, |
| 495 | 0xfffffc84, 0xfffffc07, _not_used_, _not_used_, |
| 496 | _not_used_, _not_used_, _not_used_, _not_used_, |
| 497 | |
| 498 | /* exception. (offset 3c in upm RAM) */ |
| 499 | 0x7ffffc07, _not_used_, _not_used_, _not_used_ }; |
| 500 | |
| 501 | /* ------------------------------------------------------------------------- */ |
| 502 | #else |
| 503 | #error SDRAM not correctly configured |
| 504 | #endif |
| 505 | |
| 506 | int _initsdram(uint base, uint noMbytes) |
| 507 | { |
| 508 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
| 509 | volatile memctl8xx_t *memctl = &immap->im_memctl; |
| 510 | |
| 511 | if(noMbytes != 4) |
| 512 | { |
| 513 | return -1; |
| 514 | } |
| 515 | |
| 516 | upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint)); |
| 517 | |
| 518 | memctl->memc_mptpr = SDRAM_MPTPRVALUE; |
| 519 | |
| 520 | /* Configure the refresh (mostly). This needs to be |
| 521 | * based upon processor clock speed and optimized to provide |
| 522 | * the highest level of performance. For multiple banks, |
| 523 | * this time has to be divided by the number of banks. |
| 524 | * Although it is not clear anywhere, it appears the |
| 525 | * refresh steps through the chip selects for this UPM |
| 526 | * on each refresh cycle. |
| 527 | * We have to be careful changing |
| 528 | * UPM registers after we ask it to run these commands. |
| 529 | */ |
| 530 | |
| 531 | memctl->memc_mbmr = SDRAM_MBMRVALUE0; |
| 532 | memctl->memc_mar = SDRAM_MARVALUE; /* MRS code */ |
| 533 | |
| 534 | udelay(200); |
| 535 | |
| 536 | /* Now run the precharge/nop/mrs commands. |
| 537 | */ |
| 538 | |
| 539 | memctl->memc_mcr = 0x80808111; /* run pattern 0x11 */ |
| 540 | |
| 541 | udelay(200); |
| 542 | |
| 543 | /* Run 8 refresh cycles */ |
| 544 | |
| 545 | memctl->memc_mcr = SDRAM_MCRVALUE0; |
| 546 | |
| 547 | udelay(200); |
| 548 | |
| 549 | memctl->memc_mbmr = SDRAM_MBMRVALUE1; |
| 550 | memctl->memc_mcr = SDRAM_MCRVALUE1; |
| 551 | |
| 552 | udelay(200); |
| 553 | |
| 554 | memctl->memc_mbmr = SDRAM_MBMRVALUE0; |
| 555 | |
| 556 | memctl->memc_or4 = SDRAM_OR4VALUE; |
| 557 | memctl->memc_br4 = SDRAM_BR4VALUE | base; |
| 558 | |
| 559 | return 0; |
| 560 | } |
| 561 | |
| 562 | /* ------------------------------------------------------------------------- */ |
| 563 | |
| 564 | void _sdramdisable(void) |
| 565 | { |
| 566 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
| 567 | volatile memctl8xx_t *memctl = &immap->im_memctl; |
| 568 | |
| 569 | memctl->memc_br4 = 0x00000000; |
| 570 | |
| 571 | /* maybe we should turn off upmb here or something */ |
| 572 | } |
| 573 | |
| 574 | /* ------------------------------------------------------------------------- */ |
| 575 | |
| 576 | int initsdram(uint base, uint *noMbytes) |
| 577 | { |
| 578 | uint m = 4; |
| 579 | |
| 580 | *((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */ |
| 581 | /* _fads_sdraminit needs access to sdram */ |
| 582 | *noMbytes = m; |
| 583 | |
| 584 | if(!_initsdram(base, m)) |
| 585 | { |
| 586 | |
| 587 | return 0; |
| 588 | } |
| 589 | else |
| 590 | { |
| 591 | *((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */ |
| 592 | |
| 593 | _sdramdisable(); |
| 594 | |
| 595 | return -1; |
| 596 | } |
| 597 | } |
| 598 | |
| 599 | long int initdram (int board_type) |
| 600 | { |
| 601 | #ifdef CONFIG_ADS |
| 602 | /* ADS: has no SDRAM, so start DRAM at 0 */ |
| 603 | uint base = (unsigned long)0x0; |
| 604 | #else |
| 605 | /* FADS: has 4MB SDRAM, put DRAM above it */ |
| 606 | uint base = (unsigned long)0x00400000; |
| 607 | #endif |
| 608 | uint k, m, s; |
| 609 | |
| 610 | k = (*((uint *)BCSR2) >> 23) & 0x0f; |
| 611 | |
| 612 | m = 0; |
| 613 | |
| 614 | switch(k & 0x3) |
| 615 | { |
| 616 | /* "MCM36100 / MT8D132X" */ |
| 617 | case 0x00 : |
| 618 | m = 4; |
| 619 | break; |
| 620 | |
| 621 | /* "MCM36800 / MT16D832X" */ |
| 622 | case 0x01 : |
| 623 | m = 32; |
| 624 | break; |
| 625 | /* "MCM36400 / MT8D432X" */ |
| 626 | case 0x02 : |
| 627 | m = 16; |
| 628 | break; |
| 629 | /* "MCM36200 / MT16D832X ?" */ |
| 630 | case 0x03 : |
| 631 | m = 8; |
| 632 | break; |
| 633 | |
| 634 | } |
| 635 | |
| 636 | switch(k >> 2) |
| 637 | { |
| 638 | case 0x02 : |
| 639 | k = 70; |
| 640 | break; |
| 641 | |
| 642 | case 0x03 : |
| 643 | k = 60; |
| 644 | break; |
| 645 | |
| 646 | default : |
| 647 | printf("unknown dramdelay (0x%x) - defaulting to 70 ns", k); |
| 648 | k = 70; |
| 649 | } |
| 650 | |
| 651 | #ifdef CONFIG_FADS |
| 652 | /* the FADS is missing this bit, all rams treated as non-edo */ |
| 653 | s = 0; |
| 654 | #else |
| 655 | s = (*((uint *)BCSR2) >> 27) & 0x01; |
| 656 | #endif |
| 657 | |
| 658 | if(!_draminit(base, m, s, k)) |
| 659 | { |
| 660 | #ifdef CONFIG_FADS |
| 661 | uint sdramsz; |
| 662 | #endif |
| 663 | *((uint *)BCSR1) &= ~BCSR1_DRAM_EN; /* enable dram */ |
| 664 | |
| 665 | #ifdef CONFIG_FADS |
| 666 | if (!initsdram(0x00000000, &sdramsz)) { |
| 667 | m += sdramsz; |
| 668 | printf("(%u MB SDRAM) ", sdramsz); |
| 669 | } else { |
| 670 | _dramdisable(); |
| 671 | |
| 672 | /******************************** |
| 673 | *DRAM ERROR, HALT PROCESSOR |
| 674 | *********************************/ |
| 675 | while(1); |
| 676 | |
| 677 | return -1; |
| 678 | } |
| 679 | #endif |
| 680 | |
| 681 | return (m << 20); |
| 682 | } |
| 683 | else |
| 684 | { |
| 685 | _dramdisable(); |
| 686 | |
| 687 | /******************************** |
| 688 | *DRAM ERROR, HALT PROCESSOR |
| 689 | *********************************/ |
| 690 | while(1); |
| 691 | |
| 692 | return -1; |
| 693 | } |
| 694 | } |
| 695 | |
| 696 | /* ------------------------------------------------------------------------- */ |
| 697 | |
| 698 | int testdram (void) |
| 699 | { |
| 700 | /* TODO: XXX XXX XXX */ |
| 701 | printf ("test: 16 MB - ok\n"); |
| 702 | |
| 703 | return (0); |
| 704 | } |
| 705 | |
| 706 | |
| 707 | #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) |
| 708 | |
| 709 | #ifdef CFG_PCMCIA_MEM_ADDR |
| 710 | volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR; |
| 711 | #endif |
| 712 | |
| 713 | int pcmcia_init(void) |
| 714 | { |
| 715 | volatile pcmconf8xx_t *pcmp; |
| 716 | uint v, slota, slotb; |
| 717 | |
| 718 | /* |
| 719 | ** Enable the PCMCIA for a Flash card. |
| 720 | */ |
| 721 | pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); |
| 722 | |
| 723 | #if 0 |
| 724 | pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR; |
| 725 | pcmp->pcmc_por0 = 0xc00ff05d; |
| 726 | #endif |
| 727 | |
| 728 | /* Set all slots to zero by default. */ |
| 729 | pcmp->pcmc_pgcra = 0; |
| 730 | pcmp->pcmc_pgcrb = 0; |
| 731 | #ifdef PCMCIA_SLOT_A |
| 732 | pcmp->pcmc_pgcra = 0x40; |
| 733 | #endif |
| 734 | #ifdef PCMCIA_SLOT_B |
| 735 | pcmp->pcmc_pgcrb = 0x40; |
| 736 | #endif |
| 737 | |
| 738 | /* enable PCMCIA buffers */ |
| 739 | *((uint *)BCSR1) &= ~BCSR1_PCCEN; |
| 740 | |
| 741 | /* Check if any PCMCIA card is plugged in. */ |
| 742 | |
| 743 | slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ; |
| 744 | slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ; |
| 745 | |
| 746 | if (!(slota || slotb)) |
| 747 | { |
| 748 | printf("No card present\n"); |
| 749 | #ifdef PCMCIA_SLOT_A |
| 750 | pcmp->pcmc_pgcra = 0; |
| 751 | #endif |
| 752 | #ifdef PCMCIA_SLOT_B |
| 753 | pcmp->pcmc_pgcrb = 0; |
| 754 | #endif |
| 755 | return -1; |
| 756 | } |
| 757 | else |
| 758 | printf("Card present ("); |
| 759 | |
| 760 | v = 0; |
| 761 | |
| 762 | /* both the ADS and the FADS have a 5V keyed pcmcia connector (?) |
| 763 | ** |
| 764 | ** Paolo - Yes, but i have to insert some 3.3V card in that slot on |
| 765 | ** my FADS... :-) |
| 766 | */ |
| 767 | |
| 768 | #if defined(CONFIG_MPC860) |
| 769 | switch( (pcmp->pcmc_pipr >> 30) & 3 ) |
| 770 | #elif defined(CONFIG_MPC823) || defined(CONFIG_MPC850) |
| 771 | switch( (pcmp->pcmc_pipr >> 14) & 3 ) |
| 772 | #endif |
| 773 | { |
| 774 | case 0x00 : |
| 775 | printf("5V"); |
| 776 | v = 5; |
| 777 | break; |
| 778 | case 0x01 : |
| 779 | printf("5V and 3V"); |
| 780 | #ifdef CONFIG_FADS |
| 781 | v = 3; /* User lower voltage if supported! */ |
| 782 | #else |
| 783 | v = 5; |
| 784 | #endif |
| 785 | break; |
| 786 | case 0x03 : |
| 787 | printf("5V, 3V and x.xV"); |
| 788 | #ifdef CONFIG_FADS |
| 789 | v = 3; /* User lower voltage if supported! */ |
| 790 | #else |
| 791 | v = 5; |
| 792 | #endif |
| 793 | break; |
| 794 | } |
| 795 | |
| 796 | switch(v){ |
| 797 | #ifdef CONFIG_FADS |
| 798 | case 3: |
| 799 | printf("; using 3V"); |
| 800 | /* |
| 801 | ** Enable 3 volt Vcc. |
| 802 | */ |
| 803 | *((uint *)BCSR1) &= ~BCSR1_PCCVCC1; |
| 804 | *((uint *)BCSR1) |= BCSR1_PCCVCC0; |
| 805 | break; |
| 806 | #endif |
| 807 | case 5: |
| 808 | printf("; using 5V"); |
| 809 | #ifdef CONFIG_ADS |
| 810 | /* |
| 811 | ** Enable 5 volt Vcc. |
| 812 | */ |
| 813 | *((uint *)BCSR1) &= ~BCSR1_PCCVCCON; |
| 814 | #endif |
| 815 | #ifdef CONFIG_FADS |
| 816 | /* |
| 817 | ** Enable 5 volt Vcc. |
| 818 | */ |
| 819 | *((uint *)BCSR1) &= ~BCSR1_PCCVCC0; |
| 820 | *((uint *)BCSR1) |= BCSR1_PCCVCC1; |
| 821 | #endif |
| 822 | break; |
| 823 | |
| 824 | default: |
| 825 | *((uint *)BCSR1) |= BCSR1_PCCEN; /* disable pcmcia */ |
| 826 | |
| 827 | printf("; unknown voltage"); |
| 828 | return -1; |
| 829 | } |
| 830 | printf(")\n"); |
| 831 | /* disable pcmcia reset after a while */ |
| 832 | |
| 833 | udelay(20); |
| 834 | |
| 835 | #ifdef MPC860 |
| 836 | pcmp->pcmc_pgcra = 0; |
| 837 | #elif MPC823 |
| 838 | pcmp->pcmc_pgcrb = 0; |
| 839 | #endif |
| 840 | |
| 841 | /* If you using a real hd you should give a short |
| 842 | * spin-up time. */ |
| 843 | #ifdef CONFIG_DISK_SPINUP_TIME |
| 844 | udelay(CONFIG_DISK_SPINUP_TIME); |
| 845 | #endif |
| 846 | |
| 847 | return 0; |
| 848 | } |
| 849 | |
| 850 | #endif /* CFG_CMD_PCMCIA */ |
| 851 | |
| 852 | /* ------------------------------------------------------------------------- */ |
| 853 | |
| 854 | #ifdef CFG_PC_IDE_RESET |
| 855 | |
| 856 | void ide_set_reset(int on) |
| 857 | { |
| 858 | volatile immap_t *immr = (immap_t *)CFG_IMMR; |
| 859 | |
| 860 | /* |
| 861 | * Configure PC for IDE Reset Pin |
| 862 | */ |
| 863 | if (on) { /* assert RESET */ |
| 864 | immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET); |
| 865 | } else { /* release RESET */ |
| 866 | immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET; |
| 867 | } |
| 868 | |
| 869 | /* program port pin as GPIO output */ |
| 870 | immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET); |
| 871 | immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET); |
| 872 | immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET; |
| 873 | } |
| 874 | |
| 875 | #endif /* CFG_PC_IDE_RESET */ |
| 876 | /* ------------------------------------------------------------------------- */ |