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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * armboot - Startup Code for ARM720 CPU-core
3 *
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26
27
28#include <config.h>
29#include <version.h>
30
31
32/*
33 *************************************************************************
34 *
35 * Jump vector table as in table 3.1 in [1]
36 *
37 *************************************************************************
38 */
39
40
41.globl _start
42_start: b reset
43 ldr pc, _undefined_instruction
44 ldr pc, _software_interrupt
45 ldr pc, _prefetch_abort
46 ldr pc, _data_abort
47 ldr pc, _not_used
48 ldr pc, _irq
49 ldr pc, _fiq
50
51_undefined_instruction: .word undefined_instruction
52_software_interrupt: .word software_interrupt
53_prefetch_abort: .word prefetch_abort
54_data_abort: .word data_abort
55_not_used: .word not_used
56_irq: .word irq
57_fiq: .word fiq
58
59 .balignl 16,0xdeadbeef
60
61
62/*
63 *************************************************************************
64 *
65 * Startup Code (reset vector)
66 *
67 * do important init only if we don't start from memory!
68 * relocate armboot to ram
69 * setup stack
70 * jump to second stage
71 *
72 *************************************************************************
73 */
74
75/*
76 * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
77 */
78_TEXT_BASE:
79 .word TEXT_BASE
80
81.globl _armboot_start
82_armboot_start:
83 .word _start
84
85/*
86 * Note: _armboot_end_data and _armboot_end are defined
87 * by the (board-dependent) linker script.
88 * _armboot_end_data is the first usable FLASH address after armboot
89 */
90.globl _armboot_end_data
91_armboot_end_data:
92 .word armboot_end_data
93.globl _armboot_end
94_armboot_end:
95 .word armboot_end
96
97/*
98 * _armboot_real_end is the first usable RAM address behind armboot
99 * and the various stacks
100 */
101.globl _armboot_real_end
102_armboot_real_end:
103 .word 0x0badc0de
104
105#ifdef CONFIG_USE_IRQ
106/* IRQ stack memory (calculated at run-time) */
107.globl IRQ_STACK_START
108IRQ_STACK_START:
109 .word 0x0badc0de
110
111/* IRQ stack memory (calculated at run-time) */
112.globl FIQ_STACK_START
113FIQ_STACK_START:
114 .word 0x0badc0de
115#endif
116
117
118/*
119 * the actual reset code
120 */
121
122reset:
123 /*
124 * set the cpu to SVC32 mode
125 */
126 mrs r0,cpsr
127 bic r0,r0,#0x1f
128 orr r0,r0,#0x13
129 msr cpsr,r0
130
131 /*
132 * we do sys-critical inits only at reboot,
133 * not when booting from ram!
134 */
135#ifdef CONFIG_INIT_CRITICAL
136 bl cpu_init_crit
137#endif
138
139relocate:
140 /*
141 * relocate armboot to RAM
142 */
143 adr r0, _start /* r0 <- current position of code */
144 ldr r2, _armboot_start
145 ldr r3, _armboot_end
146 sub r2, r3, r2 /* r2 <- size of armboot */
147 ldr r1, _TEXT_BASE /* r1 <- destination address */
148 add r2, r0, r2 /* r2 <- source end address */
149
150 /*
151 * r0 = source address
152 * r1 = target address
153 * r2 = source end address
154 */
155copy_loop:
156 ldmia r0!, {r3-r10}
157 stmia r1!, {r3-r10}
158 cmp r0, r2
159 ble copy_loop
160
161 /* set up the stack */
162 ldr r0, _armboot_end
163 add r0, r0, #CONFIG_STACKSIZE
164 sub sp, r0, #12 /* leave 3 words for abort-stack */
165
166 ldr pc, _start_armboot
167
168_start_armboot: .word start_armboot
169
170
171/*
172 *************************************************************************
173 *
174 * CPU_init_critical registers
175 *
176 * setup important registers
177 * setup memory timing
178 *
179 *************************************************************************
180 */
181
182
183/* Interupt-Controller base addresses */
184INTMR1: .word 0x80000280 @ 32 bit size
185INTMR2: .word 0x80001280 @ 16 bit size
186INTMR3: .word 0x80002280 @ 8 bit size
187
188/* SYSCONs */
189SYSCON1: .word 0x80000100
190SYSCON2: .word 0x80001100
191SYSCON3: .word 0x80002200
192
193#define CLKCTL 0x6 /* mask */
194#define CLKCTL_18 0x0 /* 18.432 MHz */
195#define CLKCTL_36 0x2 /* 36.864 MHz */
196#define CLKCTL_49 0x4 /* 49.152 MHz */
197#define CLKCTL_73 0x6 /* 73.728 MHz */
198
199cpu_init_crit:
200 /*
201 * mask all IRQs by clearing all bits in the INTMRs
202 */
203 mov r1, #0x00
204 ldr r0, INTMR1
205 str r1, [r0]
206 ldr r0, INTMR2
207 str r1, [r0]
208 ldr r0, INTMR3
209 str r1, [r0]
210
211 /*
212 * flush v4 I/D caches
213 */
214 mov r0, #0
215 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
216 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
217
218 /*
219 * disable MMU stuff and caches
220 */
221 mrc p15,0,r0,c1,c0
222 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
223 bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
224 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
225 mcr p15,0,r0,c1,c0
226
227#ifdef CONFIG_ARM7_REVD
228 /* set clock speed */
229 /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
230 /* !!! not doing DRAM refresh properly! */
231 ldr r0, SYSCON3
232 ldr r1, [r0]
233 bic r1, r1, #CLKCTL
234 orr r1, r1, #CLKCTL_36
235 str r1, [r0]
236#endif
237
238 /*
239 * before relocating, we have to setup RAM timing
240 * because memory timing is board-dependend, you will
241 * find a memsetup.S in your board directory.
242 */
243 mov ip, lr
244 bl memsetup
245 mov lr, ip
246
247 mov pc, lr
248
249
250
251
252/*
253 *************************************************************************
254 *
255 * Interrupt handling
256 *
257 *************************************************************************
258 */
259
260@
261@ IRQ stack frame.
262@
263#define S_FRAME_SIZE 72
264
265#define S_OLD_R0 68
266#define S_PSR 64
267#define S_PC 60
268#define S_LR 56
269#define S_SP 52
270
271#define S_IP 48
272#define S_FP 44
273#define S_R10 40
274#define S_R9 36
275#define S_R8 32
276#define S_R7 28
277#define S_R6 24
278#define S_R5 20
279#define S_R4 16
280#define S_R3 12
281#define S_R2 8
282#define S_R1 4
283#define S_R0 0
284
285#define MODE_SVC 0x13
286#define I_BIT 0x80
287
288/*
289 * use bad_save_user_regs for abort/prefetch/undef/swi ...
290 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
291 */
292
293 .macro bad_save_user_regs
294 sub sp, sp, #S_FRAME_SIZE
295 stmia sp, {r0 - r12} @ Calling r0-r12
296 add r8, sp, #S_PC
297
298 ldr r2, _armboot_end
299 add r2, r2, #CONFIG_STACKSIZE
300 sub r2, r2, #8
301 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
302 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
303
304 add r5, sp, #S_SP
305 mov r1, lr
306 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
307 mov r0, sp
308 .endm
309
310 .macro irq_save_user_regs
311 sub sp, sp, #S_FRAME_SIZE
312 stmia sp, {r0 - r12} @ Calling r0-r12
313 add r8, sp, #S_PC
314 stmdb r8, {sp, lr}^ @ Calling SP, LR
315 str lr, [r8, #0] @ Save calling PC
316 mrs r6, spsr
317 str r6, [r8, #4] @ Save CPSR
318 str r0, [r8, #8] @ Save OLD_R0
319 mov r0, sp
320 .endm
321
322 .macro irq_restore_user_regs
323 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
324 mov r0, r0
325 ldr lr, [sp, #S_PC] @ Get PC
326 add sp, sp, #S_FRAME_SIZE
327 subs pc, lr, #4 @ return & move spsr_svc into cpsr
328 .endm
329
330 .macro get_bad_stack
331 ldr r13, _armboot_end @ setup our mode stack
332 add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
333 sub r13, r13, #8
334
335 str lr, [r13] @ save caller lr / spsr
336 mrs lr, spsr
337 str lr, [r13, #4]
338
339 mov r13, #MODE_SVC @ prepare SVC-Mode
340 msr spsr_c, r13
341 mov lr, pc
342 movs pc, lr
343 .endm
344
345 .macro get_irq_stack @ setup IRQ stack
346 ldr sp, IRQ_STACK_START
347 .endm
348
349 .macro get_fiq_stack @ setup FIQ stack
350 ldr sp, FIQ_STACK_START
351 .endm
352
353/*
354 * exception handlers
355 */
356 .align 5
357undefined_instruction:
358 get_bad_stack
359 bad_save_user_regs
360 bl do_undefined_instruction
361
362 .align 5
363software_interrupt:
364 get_bad_stack
365 bad_save_user_regs
366 bl do_software_interrupt
367
368 .align 5
369prefetch_abort:
370 get_bad_stack
371 bad_save_user_regs
372 bl do_prefetch_abort
373
374 .align 5
375data_abort:
376 get_bad_stack
377 bad_save_user_regs
378 bl do_data_abort
379
380 .align 5
381not_used:
382 get_bad_stack
383 bad_save_user_regs
384 bl do_not_used
385
386#ifdef CONFIG_USE_IRQ
387
388 .align 5
389irq:
390 get_irq_stack
391 irq_save_user_regs
392 bl do_irq
393 irq_restore_user_regs
394
395 .align 5
396fiq:
397 get_fiq_stack
398 /* someone ought to write a more effiction fiq_save_user_regs */
399 irq_save_user_regs
400 bl do_fiq
401 irq_restore_user_regs
402
403#else
404
405 .align 5
406irq:
407 get_bad_stack
408 bad_save_user_regs
409 bl do_irq
410
411 .align 5
412fiq:
413 get_bad_stack
414 bad_save_user_regs
415 bl do_fiq
416
417#endif
418
419 .align 5
420.globl reset_cpu
421reset_cpu:
422 mov ip, #0
423 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
424 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
425 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
426 bic ip, ip, #0x000f @ ............wcam
427 bic ip, ip, #0x2100 @ ..v....s........
428 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
429 mov pc, r0