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Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +01001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2005-2007
6 * Modified for InterControl digsyMTC MPC5200 board by
7 * Frank Bodammer, GCD Hard- & Software GmbH,
8 * frank.bodammer@gcd-solutions.de
9 *
10 * (C) Copyright 2009 Semihalf
11 * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
12 *
13 * See file CREDITS for list of people who contributed to this
14 * project.
15 *
16 * This program is free software\; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation\; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY\; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program\; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 */
31
32#ifndef __CONFIG_H
33#define __CONFIG_H
34
35/*
36 * High Level Configuration Options
37 */
38
39#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
40#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
41#define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */
42
43#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
44
45#define BOOTFLAG_COLD 0x01
46#define BOOTFLAG_WARM 0x02
47
48#define CONFIG_SYS_CACHELINE_SIZE 32
49
50/*
51 * Serial console configuration
52 */
53#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */
54#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
55#define CONFIG_SYS_BAUDRATE_TABLE \
56 { 9600, 19200, 38400, 57600, 115200, 230400 }
57
58/*
59 * PCI Mapping:
60 * 0x40000000 - 0x4fffffff - PCI Memory
61 * 0x50000000 - 0x50ffffff - PCI IO Space
62 */
63#define CONFIG_PCI 1
64#define CONFIG_PCI_PNP 1
65#define CONFIG_PCI_SCAN_SHOW 1
66
67#define CONFIG_PCI_MEM_BUS 0x40000000
68#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
69#define CONFIG_PCI_MEM_SIZE 0x10000000
70
71#define CONFIG_PCI_IO_BUS 0x50000000
72#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
73#define CONFIG_PCI_IO_SIZE 0x01000000
74
75/*
76 * Partitions
77 */
78#define CONFIG_DOS_PARTITION
79#define CONFIG_BZIP2
80
81/*
82 * Command line configuration.
83 */
84#include <config_cmd_default.h>
85
86#define CONFIG_CMD_DFL
87#define CONFIG_CMD_CACHE
88#define CONFIG_CMD_DATE
89#define CONFIG_CMD_DHCP
90#define CONFIG_CMD_DIAG
91#define CONFIG_CMD_EEPROM
92#define CONFIG_CMD_ELF
93#define CONFIG_CMD_EXT2
94#define CONFIG_CMD_FAT
95#define CONFIG_CMD_I2C
96#define CONFIG_CMD_IDE
97#define CONFIG_CMD_IRQ
98#define CONFIG_CMD_MII
99#define CONFIG_CMD_PCI
100#define CONFIG_CMD_PING
101#define CONFIG_CMD_REGINFO
102#define CONFIG_CMD_SAVES
Grzegorz Bernackif1f66ed2009-06-12 11:33:53 +0200103#define CONFIG_CMD_SPI
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100104#define CONFIG_CMD_USB
105
106#if (TEXT_BASE == 0xFF000000)
107#define CONFIG_SYS_LOWBOOT 1
108#endif
109
110/*
111 * Autobooting
112 */
113#define CONFIG_BOOTDELAY 1
114
115#undef CONFIG_BOOTARGS
116
Detlev Zundelff276502009-08-05 18:37:45 +0200117#define CONFIG_EXTRA_ENV_SETTINGS \
118 "fw_image=digsyMPC.img\0" \
119 "mtcb_start=mtc led diag orange; run mtcb_1\0" \
120 "mtcb_clearled=for x in user1 user2 usbpwr usbbusy; " \
121 "do mtc led $x; done\0" \
122 "mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; " \
123 "else run mtcb_fw; fi\0" \
124 "mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; " \
125 "else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0" \
126 "mtcb_update=mtc led user1 orange;" \
127 "while mtc key; do ; done; run mtcb_2;\0" \
128 "mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0" \
129 "mtcb_usb1=if fatload usb 0 400000 script.img; " \
130 "then run mtcb_doscript; else run mtcb_usb2; fi\0" \
131 "mtcb_usb2=if fatload usb 0 400000 $fw_image; " \
132 "then run mtcb_dousb; else run mtcb_ide; fi\0" \
133 "mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; " \
134 "run mtcb_wait_flickr mtcb_ds_1;\0" \
135 "mtcb_ds_1=if imi 400000; then mtc led usbbusy; " \
136 "source 400000; else run mtcb_error; fi\0" \
137 "mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0" \
138 "mtcb_du_1=if imi 400000; then run mtcb_du_2; " \
139 "else run mtcb_error; fi\0" \
140 "mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; " \
141 "run mtcb_checkfw\0" \
142 "mtcb_checkfw=if imi ff000000; then run mtcb_success; " \
143 "else run mtcb_error; fi\0" \
144 "mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \
145 "mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0" \
146 "mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
147 "mtcb_uledflckr=mtc led user1 orange 11\0" \
148 "mtcb_error=mtc led user1 red\0" \
149 "mtcb_clear=erase ff000000 ff0fffff\0" \
150 "mtcb_prog=cp.b 400000 ff000000 ${filesize}\0" \
151 "mtcb_success=mtc led user1 green\0" \
152 "mtcb_ide=if fatload ide 0 400000 $fw_image;" \
153 "then run mtcb_doide; else run mtcb_error; fi\0" \
154 "mtcb_doide=mtc led user2 green 1;" \
155 "run mtcb_wait_flickr mtcb_di_1;\0" \
156 "mtcb_di_1=if imi 400000; then run mtcb_di_2;" \
157 "else run mtcb_error; fi\0" \
158 "mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0" \
159 "ramdisk_num_sector=16\0" \
160 "flash_base=ff000000\0" \
161 "flashdisk_size=e00000\0" \
162 "env_sector=fff60000\0" \
163 "flashdisk_start=ff100000\0" \
164 "load_cmd=tftp 400000 digsyMPC.img\0" \
165 "clear_cmd=erase ff000000 ff0fffff\0" \
166 "flash_cmd=cp.b 400000 ff000000 ${filesize}\0" \
167 "update_cmd=run load_cmd; " \
168 "iminfo 400000; " \
169 "run clear_cmd flash_cmd; " \
170 "iminfo ff000000\0" \
171 "spi_driver=yes\0" \
172 "spi_watchdog=no\0" \
173 "ftps_start=yes\0" \
174 "ftps_user1=admin\0" \
175 "ftps_pass1=admin\0" \
176 "ftps_base1=/\0" \
177 "ftps_home1=/\0" \
178 "plc_sio_srv=no\0" \
179 "plc_sio_baud=57600\0" \
180 "plc_sio_parity=no\0" \
181 "plc_sio_stop=1\0" \
182 "plc_sio_com=2\0" \
183 "plc_eth_srv=yes\0" \
184 "plc_eth_port=1200\0" \
185 "plc_root=/ide/\0" \
186 "diag_level=0\0" \
187 "webvisu=no\0" \
188 "plc_can1_routing=no\0" \
189 "plc_can1_baudrate=250\0" \
190 "plc_can2_routing=no\0" \
191 "plc_can2_baudrate=250\0" \
192 "plc_can3_routing=no\0" \
193 "plc_can3_baudrate=250\0" \
194 "plc_can4_routing=no\0" \
195 "plc_can4_baudrate=250\0" \
196 "netdev=eth0\0" \
197 "console=ttyPSC0\0" \
198 "kernel_addr_r=400000\0" \
199 "fdt_addr_r=600000\0" \
200 "nfsargs=setenv bootargs root=/dev/nfs rw " \
201 "nfsroot=${serverip}:${rootpath}\0" \
202 "addip=setenv bootargs ${bootargs} " \
203 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
204 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100205 "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
Detlev Zundelff276502009-08-05 18:37:45 +0200206 "rootpath=/opt/eldk/ppc_6xx\0" \
207 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
208 "tftp ${fdt_addr_r} ${fdt_file};" \
209 "run nfsargs addip addcons;" \
210 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
211 "load=tftp 200000 ${u-boot}\0" \
212 "update=protect off FFF00000 +${filesize};" \
213 "erase FFF00000 +${filesize};" \
214 "cp.b 200000 FFF00000 ${filesize};" \
215 "protect on FFF00000 +${filesize}\0" \
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100216 ""
217
Detlev Zundelff276502009-08-05 18:37:45 +0200218#define CONFIG_BOOTCOMMAND "run mtcb_start"
219
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100220/*
Grzegorz Bernackif1f66ed2009-06-12 11:33:53 +0200221 * SPI configuration
222 */
223#define CONFIG_HARD_SPI 1
224#define CONFIG_MPC52XX_SPI 1
225
226/*
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100227 * I2C configuration
228 */
229#define CONFIG_HARD_I2C 1
230#define CONFIG_SYS_I2C_MODULE 1
231#define CONFIG_SYS_I2C_SPEED 100000
232#define CONFIG_SYS_I2C_SLAVE 0x7F
233
234/*
235 * EEPROM configuration
236 */
237#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
238#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
239#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
240#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
241
242/*
243 * RTC configuration
244 */
245#define CONFIG_RTC_DS1337
246#define CONFIG_SYS_I2C_RTC_ADDR 0x68
247
248/*
249 * Flash configuration
250 */
251#define CONFIG_SYS_FLASH_CFI 1
252#define CONFIG_FLASH_CFI_DRIVER 1
253
254#define CONFIG_SYS_FLASH_BASE 0xFF000000
255#define CONFIG_SYS_FLASH_SIZE 0x01000000
256
257#define CONFIG_SYS_MAX_FLASH_BANKS 1
258#define CONFIG_SYS_MAX_FLASH_SECT 256
259#define CONFIG_FLASH_16BIT
260#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
261#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
262#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
263#define CONFIG_SYS_FLASH_WRITE_TOUT 500
264
265#define CONFIG_OF_LIBFDT 1
266#define CONFIG_OF_BOARD_SETUP 1
267
268#define OF_CPU "PowerPC,5200@0"
269#define OF_SOC "soc5200@f0000000"
270#define OF_TBCLK (bd->bi_busfreq / 4)
271
272#define CONFIG_BOARD_EARLY_INIT_R
273#define CONFIG_MISC_INIT_R
274
275/*
276 * Environment settings
277 */
278#define CONFIG_ENV_IS_IN_FLASH 1
279#if defined(CONFIG_LOWBOOT)
280#define CONFIG_ENV_ADDR 0xFF060000
281#else /* CONFIG_LOWBOOT */
282#define CONFIG_ENV_ADDR 0xFFF60000
283#endif /* CONFIG_LOWBOOT */
284#define CONFIG_ENV_SIZE 0x10000
285#define CONFIG_ENV_SECT_SIZE 0x20000
286#define CONFIG_ENV_OVERWRITE 1
287
288/*
289 * Memory map
290 */
291#define CONFIG_SYS_MBAR 0xF0000000
292#define CONFIG_SYS_SDRAM_BASE 0x00000000
293#if !defined(CONFIG_SYS_LOWBOOT)
294#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
295#else
296#define CONFIG_SYS_DEFAULT_MBAR 0xF0000000
297#endif
298
299/*
300 * Use SRAM until RAM will be available
301 */
302#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
303#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
304
305#define CONFIG_SYS_GBL_DATA_SIZE 4096
306#define CONFIG_SYS_GBL_DATA_OFFSET \
307 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
308#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
309
310#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
311#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
312#define CONFIG_SYS_RAMBOOT 1
313#endif
314
315#define CONFIG_SYS_MONITOR_LEN (256 << 10)
316#define CONFIG_SYS_MALLOC_LEN (4096 << 10)
317#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
318
319/*
320 * Ethernet configuration
321 */
322#define CONFIG_MPC5xxx_FEC 1
323#define CONFIG_MPC5xxx_FEC_MII100
324#define CONFIG_PHY_ADDR 0x00
325#define CONFIG_PHY_RESET_DELAY 1000
326
327#define CONFIG_NETCONSOLE /* include NetConsole support */
328
329/*
330 * GPIO configuration
Grzegorz Bernacki12602332009-06-12 11:33:55 +0200331 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
332 * Bit 0 (mask 0x80000000) : 0x1
333 * SPI on Tmr2/3/4/5 pins
334 * Bit 2:3 (mask 0x30000000) : 0x2
335 * ATA cs0/1 on csb_4/5
336 * Bit 6:7 (mask 0x03000000) : 0x2
337 * Ethernet 100Mbit with MD
338 * Bits 12:15 (mask 0x000f0000): 0x5
339 * USB - Two UARTs
340 * Bits 18:19 (mask 0x00003000) : 0x2
341 * PSC3 - USB2 on PSC3
342 * Bits 20:23 (mask 0x00000f00) : 0x1
343 * PSC2 - CAN1&2 on PSC2 pins
344 * Bits 25:27 (mask 0x00000070) : 0x1
345 * PSC1 - AC97 functionality
346 * Bits 29:31 (mask 0x00000007) : 0x2
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100347 */
348#define CONFIG_SYS_GPS_PORT_CONFIG 0xA2552112
349
350/*
351 * Miscellaneous configurable options
352 */
353#define CONFIG_SYS_LONGHELP
354#define CONFIG_AUTO_COMPLETE 1
Grzegorz Bernackia781de12009-06-17 16:20:14 +0200355#define CONFIG_CMDLINE_EDITING 1
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100356#define CONFIG_SYS_PROMPT "=> "
357#define CONFIG_SYS_HUSH_PARSER
358#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
359
360#define CONFIG_AUTOBOOT_KEYED
361#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
362#define CONFIG_AUTOBOOT_DELAY_STR " "
363
364#define CONFIG_LOOPW 1
365#define CONFIG_MX_CYCLIC 1
366#define CONFIG_ZERO_BOOTDELAY_CHECK
367
368#define CONFIG_SYS_CBSIZE 1024
369#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
370#define CONFIG_SYS_MAXARGS 32
371#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
372
373#define CONFIG_SYS_ALT_MEMTEST
374#define CONFIG_SYS_MEMTEST_SCRATCH 0x00001000
375#define CONFIG_SYS_MEMTEST_START 0x00010000
376#define CONFIG_SYS_MEMTEST_END 0x019fffff
377
378#define CONFIG_SYS_LOAD_ADDR 0x00100000
379
380#define CONFIG_SYS_HZ 1000
381
382/*
383 * Various low-level settings
384 */
385#define CONFIG_SYS_SDRAM_CS1 1
386#define CONFIG_SYS_XLB_PIPELINING 1
387
388#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
389#define CONFIG_SYS_HID0_FINAL HID0_ICE
390
391#if defined(CONFIG_SYS_LOWBOOT)
392#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
393#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
394#define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
395#endif
396
397#define CONFIG_SYS_CS4_START 0x60000000
398#define CONFIG_SYS_CS4_SIZE 0x1000
399#define CONFIG_SYS_CS4_CFG 0x0008FC00
400
401#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
402#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
403#define CONFIG_SYS_CS0_CFG 0x0002DD00
404
405#define CONFIG_SYS_CS_BURST 0x00000000
406#define CONFIG_SYS_CS_DEADCYCLE 0x11111111
407
408#if !defined(CONFIG_SYS_LOWBOOT)
409#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
410#else
411#define CONFIG_SYS_RESET_ADDRESS 0xff000100
412#endif
413
414/*
415 * USB
416 */
417#define CONFIG_USB_OHCI_NEW
418#define CONFIG_SYS_OHCI_BE_CONTROLLER
419#define CONFIG_USB_STORAGE
420
421#define CONFIG_USB_CLOCK 0x00013333
422#define CONFIG_USB_CONFIG 0x00002000
423
424#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
425#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
426#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
427#define CONFIG_SYS_USB_OHCI_CPU_INIT
428
429/*
430 * IDE/ATA
431 */
432#define CONFIG_IDE_RESET
433#define CONFIG_IDE_PREINIT
434
435#define CONFIG_SYS_ATA_CS_ON_I2C2
436#define CONFIG_SYS_IDE_MAXBUS 1
437#define CONFIG_SYS_IDE_MAXDEVICE 1
438
439#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
440#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
441#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
442#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
443#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
444#define CONFIG_SYS_ATA_STRIDE 4
445
446#define CONFIG_ATAPI 1
447#define CONFIG_LBA48 1
448
449#endif /* __CONFIG_H */