blob: fb1208fc5d570bb3e4676c308bf67f56c57f626f [file] [log] [blame]
Tom Rini4549e782018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01002/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01004 */
5
Patrick Delaunayeb653ac2020-11-06 19:01:29 +01006#define LOG_CATEGORY LOGC_ARCH
7
Patrick Delaunay2514c2d2018-03-12 10:46:10 +01008#include <common.h>
9#include <dm.h>
Simon Glass4d72caa2020-05-10 11:40:01 -060010#include <image.h>
11#include <init.h>
Patrick Delaunay4a1b9752020-03-18 09:22:48 +010012#include <lmb.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060013#include <log.h>
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010014#include <ram.h>
Simon Glass401d1c42020-10-30 21:38:53 -060015#include <asm/global_data.h>
Patrick Delaunay1419e5b2021-02-05 13:53:32 +010016#include <asm/system.h>
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010017
18DECLARE_GLOBAL_DATA_PTR;
19
20int dram_init(void)
21{
22 struct ram_info ram;
23 struct udevice *dev;
24 int ret;
25
26 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
Patrice Chotarddba8d922023-10-27 16:42:57 +020027 /* in case there is no RAM driver, retrieve DDR size from DT */
28 if (ret == -ENODEV) {
29 return fdtdec_setup_mem_size_base();
30 } else if (ret) {
31 log_err("RAM init failed: %d\n", ret);
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010032 return ret;
33 }
34 ret = ram_get_info(dev, &ram);
35 if (ret) {
Patrick Delaunayeb653ac2020-11-06 19:01:29 +010036 log_debug("Cannot get RAM size: %d\n", ret);
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010037 return ret;
38 }
Patrick Delaunayee15c722023-10-27 16:42:58 +020039 log_debug("RAM init base=%p, size=%zx\n", (void *)ram.base, ram.size);
Patrick Delaunay2514c2d2018-03-12 10:46:10 +010040
41 gd->ram_size = ram.size;
42
43 return 0;
44}
Patrick Delaunay4a1b9752020-03-18 09:22:48 +010045
Heinrich Schuchardtd768dd82023-08-12 20:16:58 +020046phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
Patrick Delaunay4a1b9752020-03-18 09:22:48 +010047{
Patrick Delaunay1419e5b2021-02-05 13:53:32 +010048 phys_size_t size;
Patrick Delaunay4a1b9752020-03-18 09:22:48 +010049 phys_addr_t reg;
50 struct lmb lmb;
51
Patrick Delaunay92b611e2021-07-26 11:55:27 +020052 if (!total_size)
Patrice Chotardc8510e32021-09-01 09:56:02 +020053 return gd->ram_top;
Patrick Delaunay92b611e2021-07-26 11:55:27 +020054
Patrice Chotard75ba0fd2023-10-27 16:42:59 +020055 /*
56 * make sure U-Boot uses address space below 4GB boundaries even
57 * if the effective available memory is bigger
58 */
59 gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1);
60
Patrick Delaunay4a1b9752020-03-18 09:22:48 +010061 /* found enough not-reserved memory to relocated U-Boot */
62 lmb_init(&lmb);
Patrice Chotard75ba0fd2023-10-27 16:42:59 +020063 lmb_add(&lmb, gd->ram_base, gd->ram_top - gd->ram_base);
Patrick Delaunay4a1b9752020-03-18 09:22:48 +010064 boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
Patrick Delaunay7dc60682021-05-07 14:50:34 +020065 /* add 8M for reserved memory for display, fdt, gd,... */
66 size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE),
Patrick Delaunay1419e5b2021-02-05 13:53:32 +010067 reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
Patrick Delaunay4a1b9752020-03-18 09:22:48 +010068
Patrick Delaunay1419e5b2021-02-05 13:53:32 +010069 if (!reg)
70 reg = gd->ram_top - size;
Patrick Delaunay4a1b9752020-03-18 09:22:48 +010071
Patrick Delaunay7dc60682021-05-07 14:50:34 +020072 /* before relocation, mark the U-Boot memory as cacheable by default */
73 if (!(gd->flags & GD_FLG_RELOC))
74 mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION);
Patrick Delaunay1419e5b2021-02-05 13:53:32 +010075
76 return reg + size;
Patrick Delaunay4a1b9752020-03-18 09:22:48 +010077}