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Bo Shen3225f342013-05-12 22:40:54 +00001/*
2 * Configuation settings for the SAMA5D3xEK board.
3 *
4 * Copyright (C) 2012 - 2013 Atmel
5 *
6 * based on at91sam9m10g45ek.h by:
7 * Stelian Pop <stelian@popies.net>
8 * Lead Tech Design <www.leadtechdesign.com>
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
Bo Shen3225f342013-05-12 22:40:54 +000011 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
Wu, Joshb2d387b2015-03-30 14:51:19 +080016/*
17 * If has No NOR flash, please put the definition: CONFIG_SYS_NO_FLASH
18 * before the common header.
19 */
20#include "at91-sama5_common.h"
Bo Shen3225f342013-05-12 22:40:54 +000021
22/* serial console */
23#define CONFIG_ATMEL_USART
24#define CONFIG_USART_BASE ATMEL_BASE_DBGU
25#define CONFIG_USART_ID ATMEL_ID_DBGU
26
27/*
28 * This needs to be defined for the OHCI code to work but it is defined as
29 * ATMEL_ID_UHPHS in the CPU specific header files.
30 */
31#define ATMEL_ID_UHP ATMEL_ID_UHPHS
32
33/*
34 * Specify the clock enable bit in the PMC_SCER register.
35 */
36#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
37
38/* LCD */
39#define CONFIG_LCD
40#define LCD_BPP LCD_COLOR16
41#define LCD_OUTPUT_BPP 24
42#define CONFIG_LCD_LOGO
Bo Shen3225f342013-05-12 22:40:54 +000043#define CONFIG_LCD_INFO
44#define CONFIG_LCD_INFO_BELOW_LOGO
45#define CONFIG_SYS_WHITE_ON_BLACK
46#define CONFIG_ATMEL_HLCD
47#define CONFIG_ATMEL_LCD_RGB565
48#define CONFIG_SYS_CONSOLE_IS_IN_ENV
49
50/* board specific (not enough SRAM) */
51#define CONFIG_SAMA5D3_LCD_BASE 0x23E00000
52
Bo Shend6b79432014-07-18 16:43:08 +080053/* NOR flash */
Wu, Joshb2d387b2015-03-30 14:51:19 +080054#ifndef CONFIG_SYS_NO_FLASH
Bo Shend6b79432014-07-18 16:43:08 +080055#define CONFIG_FLASH_CFI_DRIVER
56#define CONFIG_SYS_FLASH_CFI
57#define CONFIG_SYS_FLASH_PROTECTION
58#define CONFIG_SYS_FLASH_BASE 0x10000000
59#define CONFIG_SYS_MAX_FLASH_SECT 131
60#define CONFIG_SYS_MAX_FLASH_BANKS 1
Bo Shend6b79432014-07-18 16:43:08 +080061#endif
Bo Shen3225f342013-05-12 22:40:54 +000062
Bo Shen3225f342013-05-12 22:40:54 +000063/* SDRAM */
64#define CONFIG_NR_DRAM_BANKS 1
65#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
66#define CONFIG_SYS_SDRAM_SIZE 0x20000000
67
Bo Shenc5e88852013-11-15 11:12:38 +080068#ifdef CONFIG_SPL_BUILD
69#define CONFIG_SYS_INIT_SP_ADDR 0x310000
70#else
Bo Shen3225f342013-05-12 22:40:54 +000071#define CONFIG_SYS_INIT_SP_ADDR \
72 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
Bo Shenc5e88852013-11-15 11:12:38 +080073#endif
Bo Shen3225f342013-05-12 22:40:54 +000074
75/* SerialFlash */
76#define CONFIG_CMD_SF
77
78#ifdef CONFIG_CMD_SF
79#define CONFIG_ATMEL_SPI
Bo Shen3225f342013-05-12 22:40:54 +000080#define CONFIG_SPI_FLASH_ATMEL
81#define CONFIG_SF_DEFAULT_SPEED 30000000
82#endif
83
84/* NAND flash */
85#define CONFIG_CMD_NAND
86
87#ifdef CONFIG_CMD_NAND
Bo Shen3225f342013-05-12 22:40:54 +000088#define CONFIG_NAND_ATMEL
89#define CONFIG_SYS_MAX_NAND_DEVICE 1
90#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
91/* our ALE is AD21 */
92#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
93/* our CLE is AD22 */
94#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
95#define CONFIG_SYS_NAND_ONFI_DETECTION
96/* PMECC & PMERRLOC */
97#define CONFIG_ATMEL_NAND_HWECC
98#define CONFIG_ATMEL_NAND_HW_PMECC
99#define CONFIG_PMECC_CAP 4
100#define CONFIG_PMECC_SECTOR_SIZE 512
Bo Shen3225f342013-05-12 22:40:54 +0000101#define CONFIG_CMD_NAND_TRIMFFS
102#endif
103
104/* Ethernet Hardware */
105#define CONFIG_MACB
106#define CONFIG_RMII
Bo Shen3225f342013-05-12 22:40:54 +0000107#define CONFIG_NET_RETRY_COUNT 20
108#define CONFIG_MACB_SEARCH_PHY
Bo Shene08d6f32013-06-26 10:11:06 +0800109#define CONFIG_RGMII
110#define CONFIG_CMD_MII
111#define CONFIG_PHYLIB
112#define CONFIG_PHY_MICREL
113#define CONFIG_PHY_MICREL_KSZ9021
Bo Shen3225f342013-05-12 22:40:54 +0000114
115/* MMC */
116#define CONFIG_CMD_MMC
117
118#ifdef CONFIG_CMD_MMC
119#define CONFIG_MMC
120#define CONFIG_GENERIC_MMC
121#define CONFIG_GENERIC_ATMEL_MCI
122#define ATMEL_BASE_MMCI ATMEL_BASE_MCI0
123#endif
124
125/* USB */
126#define CONFIG_CMD_USB
127
128#ifdef CONFIG_CMD_USB
129#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +0800130#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
Bo Shen3225f342013-05-12 22:40:54 +0000131#define CONFIG_USB_OHCI_NEW
132#define CONFIG_SYS_USB_OHCI_CPU_INIT
133#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
134#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3"
135#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
136#define CONFIG_DOS_PARTITION
137#define CONFIG_USB_STORAGE
138#endif
139
Bo Shen3668ce32013-09-11 18:24:51 +0800140/* USB device */
141#define CONFIG_USB_GADGET
142#define CONFIG_USB_GADGET_DUALSPEED
143#define CONFIG_USB_GADGET_ATMEL_USBA
144#define CONFIG_USB_ETHER
145#define CONFIG_USB_ETH_RNDIS
146#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D3xEK"
147
Bo Shen3225f342013-05-12 22:40:54 +0000148#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
149#define CONFIG_CMD_FAT
Wu, Josha2485582015-01-20 10:33:32 +0800150#define CONFIG_FAT_WRITE
Bo Shen3225f342013-05-12 22:40:54 +0000151#endif
152
153#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
154
155#ifdef CONFIG_SYS_USE_SERIALFLASH
156/* bootstrap + u-boot + env + linux in serial flash */
157#define CONFIG_ENV_IS_IN_SPI_FLASH
158#define CONFIG_ENV_OFFSET 0x5000
159#define CONFIG_ENV_SIZE 0x3000
160#define CONFIG_ENV_SECT_SIZE 0x1000
161#define CONFIG_BOOTCOMMAND "sf probe 0; " \
162 "sf read 0x22000000 0x42000 0x300000; " \
163 "bootm 0x22000000"
164#elif CONFIG_SYS_USE_NANDFLASH
165/* bootstrap + u-boot + env in nandflash */
166#define CONFIG_ENV_IS_IN_NAND
167#define CONFIG_ENV_OFFSET 0xc0000
168#define CONFIG_ENV_OFFSET_REDUND 0x100000
169#define CONFIG_ENV_SIZE 0x20000
170#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \
171 "nand read 0x22000000 0x200000 0x600000;" \
172 "bootm 0x22000000 - 0x21000000"
173#elif CONFIG_SYS_USE_MMC
174/* bootstrap + u-boot + env in sd card */
Wu, Josha2485582015-01-20 10:33:32 +0800175#define CONFIG_ENV_IS_IN_FAT
176#define FAT_ENV_INTERFACE "mmc"
177#define FAT_ENV_FILE "uboot.env"
178#define FAT_ENV_DEVICE_AND_PART "0"
179#define CONFIG_ENV_SIZE 0x4000
Bo Shen3225f342013-05-12 22:40:54 +0000180#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 dtb; " \
181 "fatload mmc 0:1 0x22000000 uImage; " \
182 "bootm 0x22000000 - 0x21000000"
Bo Shen3225f342013-05-12 22:40:54 +0000183#else
Bo Shena4c79b32013-08-11 14:26:20 +0000184#define CONFIG_ENV_IS_NOWHERE
Bo Shen3225f342013-05-12 22:40:54 +0000185#endif
186
Bo Shenc5e88852013-11-15 11:12:38 +0800187/* SPL */
Bo Shenc5e88852013-11-15 11:12:38 +0800188#define CONFIG_SPL_FRAMEWORK
189#define CONFIG_SPL_TEXT_BASE 0x300000
190#define CONFIG_SPL_MAX_SIZE 0x10000
191#define CONFIG_SPL_BSS_START_ADDR 0x20000000
192#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
193#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
194#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
195
196#define CONFIG_SPL_LIBCOMMON_SUPPORT
197#define CONFIG_SPL_LIBGENERIC_SUPPORT
198#define CONFIG_SPL_GPIO_SUPPORT
199#define CONFIG_SPL_SERIAL_SUPPORT
200
201#define CONFIG_SPL_BOARD_INIT
Bo Shen8a45b0b2014-03-03 14:47:15 +0800202#define CONFIG_SYS_MONITOR_LEN (512 << 10)
203
Bo Shenc5e88852013-11-15 11:12:38 +0800204#ifdef CONFIG_SYS_USE_MMC
Bo Shen993ea972015-03-04 13:32:57 +0800205#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds
Bo Shenc5e88852013-11-15 11:12:38 +0800206#define CONFIG_SPL_MMC_SUPPORT
207#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
208#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
Paul Kocialkowskie2ccdf82014-11-08 23:14:55 +0100209#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
Guillaume GARDET205b4f32014-10-15 17:53:11 +0200210#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Bo Shenc5e88852013-11-15 11:12:38 +0800211#define CONFIG_SPL_FAT_SUPPORT
212#define CONFIG_SPL_LIBDISK_SUPPORT
Bo Shen8a45b0b2014-03-03 14:47:15 +0800213
Bo Shen27019e42014-03-03 14:47:17 +0800214#elif CONFIG_SYS_USE_NANDFLASH
215#define CONFIG_SPL_NAND_SUPPORT
216#define CONFIG_SPL_NAND_DRIVERS
217#define CONFIG_SPL_NAND_BASE
218#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
219#define CONFIG_SYS_NAND_5_ADDR_CYCLE
220#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
221#define CONFIG_SYS_NAND_PAGE_COUNT 64
222#define CONFIG_SYS_NAND_OOBSIZE 64
223#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
224#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
Andreas Bießmanne166a832014-05-19 14:23:41 +0200225#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
Bo Shen27019e42014-03-03 14:47:17 +0800226
Bo Shen8a45b0b2014-03-03 14:47:15 +0800227#elif CONFIG_SYS_USE_SERIALFLASH
228#define CONFIG_SPL_SPI_SUPPORT
229#define CONFIG_SPL_SPI_FLASH_SUPPORT
230#define CONFIG_SPL_SPI_LOAD
Bo Shen8a45b0b2014-03-03 14:47:15 +0800231#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
232
Bo Shenc5e88852013-11-15 11:12:38 +0800233#endif
234
Bo Shen3225f342013-05-12 22:40:54 +0000235#endif