blob: 0b31c50daf4da0dde659700e502c8648fa86f486 [file] [log] [blame]
Wolfgang Denk52568c32009-05-16 10:47:46 +02001/*
2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3 * (C) Copyright 2009, DAVE Srl <www.dave.eu>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Aria board configuration file
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#define CONFIG_ARIA 1
32/*
33 * Memory map for the ARIA board:
34 *
35 * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB)
36 * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB)
37 * 0x3010_0000-0x3011_FFFF On Board SRAM (128 KB) - CS6
38 * 0x3020_0000-0x3021_FFFF FPGA (128 KB) - CS2
39 * 0x8000_0000-0x803F_FFFF IMMR (4 MB)
40 * 0x8400_0000-0x82FF_FFFF PCI I/O space (16 MB)
41 * 0xA000_0000-0xAFFF_FFFF PCI memory space (256 MB)
42 * 0xB000_0000-0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
43 * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB)
44 */
45
46/*
47 * High Level Configuration Options
48 */
49#define CONFIG_E300 1 /* E300 Family */
50#define CONFIG_MPC512X 1 /* MPC512X family */
51#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
Wolfgang Denk52568c32009-05-16 10:47:46 +020052
Wolfgang Denk2ae18242010-10-06 09:05:45 +020053#define CONFIG_SYS_TEXT_BASE 0xFFF00000
54
Wolfgang Denk52568c32009-05-16 10:47:46 +020055/* video */
56#undef CONFIG_VIDEO
57
58#if defined(CONFIG_VIDEO)
59#define CONFIG_CFB_CONSOLE
60#define CONFIG_VGA_AS_SINGLE_DEVICE
61#endif
62
63/* CONFIG_PCI is defined at config time */
64
65#define CONFIG_SYS_MPC512X_CLKIN 33000000 /* in Hz */
66
67#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
68#define CONFIG_MISC_INIT_R
69
70#define CONFIG_SYS_IMMR 0x80000000
71#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100)
72
73#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
74#define CONFIG_SYS_MEMTEST_END 0x00400000
75
76/*
77 * DDR Setup - manually set all parameters as there's no SPD etc.
78 */
79#define CONFIG_SYS_DDR_SIZE 256 /* MB */
80#define CONFIG_SYS_DDR_BASE 0x00000000
81#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Anatolij Gustschinb9947bb2010-04-24 19:27:08 +020082#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
Wolfgang Denk52568c32009-05-16 10:47:46 +020083
Anatolij Gustschin5d937e82010-04-24 19:27:07 +020084#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036
85
Wolfgang Denk52568c32009-05-16 10:47:46 +020086/* DDR Controller Configuration
87 *
88 * SYS_CFG:
89 * [31:31] MDDRC Soft Reset: Diabled
90 * [30:30] DRAM CKE pin: Enabled
91 * [29:29] DRAM CLK: Enabled
92 * [28:28] Command Mode: Enabled (For initialization only)
93 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
94 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
95 * [20:19] Read Test: DON'T USE
96 * [18:18] Self Refresh: Enabled
97 * [17:17] 16bit Mode: Disabled
98 * [16:13] Ready Delay: 2
99 * [12:12] Half DQS Delay: Disabled
100 * [11:11] Quarter DQS Delay: Disabled
101 * [10:08] Write Delay: 2
102 * [07:07] Early ODT: Disabled
103 * [06:06] On DIE Termination: Disabled
104 * [05:05] FIFO Overflow Clear: DON'T USE here
105 * [04:04] FIFO Underflow Clear: DON'T USE here
106 * [03:03] FIFO Overflow Pending: DON'T USE here
107 * [02:02] FIFO Underlfow Pending: DON'T USE here
108 * [01:01] FIFO Overlfow Enabled: Enabled
109 * [00:00] FIFO Underflow Enabled: Enabled
110 * TIME_CFG0
111 * [31:16] DRAM Refresh Time: 0 CSB clocks
112 * [15:8] DRAM Command Time: 0 CSB clocks
113 * [07:00] DRAM Precharge Time: 0 CSB clocks
114 * TIME_CFG1
115 * [31:26] DRAM tRFC:
116 * [25:21] DRAM tWR1:
117 * [20:17] DRAM tWRT1:
118 * [16:11] DRAM tDRR:
119 * [10:05] DRAM tRC:
120 * [04:00] DRAM tRAS:
121 * TIME_CFG2
122 * [31:28] DRAM tRCD:
123 * [27:23] DRAM tFAW:
124 * [22:19] DRAM tRTW1:
125 * [18:15] DRAM tCCD:
126 * [14:10] DRAM tRTP:
127 * [09:05] DRAM tRP:
128 * [04:00] DRAM tRPA
129 */
Wolfgang Denk25671c82009-06-14 20:58:48 +0200130#define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \
131 (1 << 30) | /* CKE */ \
132 (1 << 29) | /* CLK_ON */ \
Martha M Stan054197b2009-09-21 14:07:14 -0400133 (0 << 28) | /* CMD_MODE */ \
Wolfgang Denk25671c82009-06-14 20:58:48 +0200134 (4 << 25) | /* DRAM_ROW_SELECT */ \
135 (3 << 21) | /* DRAM_BANK_SELECT */ \
136 (0 << 18) | /* SELF_REF_EN */ \
137 (0 << 17) | /* 16BIT_MODE */ \
138 (2 << 13) | /* RDLY */ \
139 (0 << 12) | /* HALF_DQS_DLY */ \
140 (1 << 11) | /* QUART_DQS_DLY */ \
141 (2 << 8) | /* WDLY */ \
142 (0 << 7) | /* EARLY_ODT */ \
143 (1 << 6) | /* ON_DIE_TERMINATE */ \
144 (0 << 5) | /* FIFO_OV_CLEAR */ \
145 (0 << 4) | /* FIFO_UV_CLEAR */ \
146 (0 << 1) | /* FIFO_OV_EN */ \
147 (0 << 0) /* FIFO_UV_EN */ \
148 )
149
Martha M Stan054197b2009-09-21 14:07:14 -0400150#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E
Wolfgang Denk25671c82009-06-14 20:58:48 +0200151#define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189
152#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863
Wolfgang Denk52568c32009-05-16 10:47:46 +0200153
Martha M Stan054197b2009-09-21 14:07:14 -0400154#define CONFIG_SYS_DDRCMD_NOP 0x01380000
155#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
Wolfgang Denk25671c82009-06-14 20:58:48 +0200156#define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \
157 (0 << 22) | /* DRAM_CS */ \
158 (0 << 21) | /* DRAM_RAS */ \
159 (0 << 20) | /* DRAM_CAS */ \
160 (0 << 19) | /* DRAM_WEB */ \
161 (1 << 16) | /* DRAM_BS[2:0] */ \
162 (0 << 15) | /* */ \
163 (0 << 12) | /* A12->out */ \
164 (0 << 11) | /* A11->RDQS */ \
165 (0 << 10) | /* A10->DQS# */ \
166 (0 << 7) | /* OCD program */ \
167 (0 << 6) | /* Rtt1 */ \
168 (0 << 3) | /* posted CAS# */ \
169 (0 << 2) | /* Rtt0 */ \
170 (1 << 1) | /* ODS */ \
171 (0 << 0) /* DLL */ \
172 )
173#define CONFIG_SYS_MICRON_EMR2 0x01020000
174#define CONFIG_SYS_MICRON_EMR3 0x01030000
Martha M Stan054197b2009-09-21 14:07:14 -0400175#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
Wolfgang Denk52568c32009-05-16 10:47:46 +0200176#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
Wolfgang Denk25671c82009-06-14 20:58:48 +0200177#define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \
178 (0 << 22) | /* DRAM_CS */ \
179 (0 << 21) | /* DRAM_RAS */ \
180 (0 << 20) | /* DRAM_CAS */ \
181 (0 << 19) | /* DRAM_WEB */ \
182 (1 << 16) | /* DRAM_BS[2:0] */ \
183 (0 << 15) | /* */ \
184 (0 << 12) | /* A12->out */ \
185 (0 << 11) | /* A11->RDQS */ \
186 (1 << 10) | /* A10->DQS# */ \
187 (7 << 7) | /* OCD program */ \
188 (0 << 6) | /* Rtt1 */ \
189 (0 << 3) | /* posted CAS# */ \
190 (1 << 2) | /* Rtt0 */ \
191 (0 << 1) | /* ODS (Output Drive Strength) */ \
192 (0 << 0) /* DLL */ \
193 )
194
195/*
196 * Backward compatible definitions,
Stefan Roesea47a12b2010-04-15 16:07:28 +0200197 * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
Wolfgang Denk25671c82009-06-14 20:58:48 +0200198 */
Martha M Stan054197b2009-09-21 14:07:14 -0400199#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
200#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
201#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR)
202#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200203
204/* DDR Priority Manager Configuration */
205#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
206#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
207#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
208#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
209#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
210#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
211#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
212#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
213#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
214#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
215#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
216#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
217#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
218#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
219#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
220#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
221#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
222#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
223#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
224#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
225#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
226#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
227#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
228
229/*
230 * NOR FLASH on the Local Bus
231 */
232#define CONFIG_SYS_FLASH_CFI /* use the CFI code */
233#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
234#define CONFIG_SYS_FLASH_BASE 0xF8000000 /* start of FLASH */
235#define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max flash size */
236
237#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
238#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
239#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
240#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max sectors */
241
242#undef CONFIG_SYS_FLASH_CHECKSUM
243
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200244/*
245 * NAND FLASH support
246 * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
247 */
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200248#define CONFIG_CMD_NAND /* enable NAND support */
249#define CONFIG_JFFS2_NAND /* with JFFS2 on it */
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200250#define CONFIG_NAND_MPC5121_NFC
251#define CONFIG_SYS_NAND_BASE 0x40000000
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200252#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200253
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200254/*
255 * Configuration parameters for MPC5121 NAND driver
256 */
257#define CONFIG_FSL_NFC_WIDTH 1
258#define CONFIG_FSL_NFC_WRITE_SIZE 2048
259#define CONFIG_FSL_NFC_SPARE_SIZE 64
260#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
261
Wolfgang Denk52568c32009-05-16 10:47:46 +0200262#define CONFIG_SYS_SRAM_BASE 0x30000000
263#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
264
Wolfgang Denk25671c82009-06-14 20:58:48 +0200265/* Make two SRAM regions contiguous */
266#define CONFIG_SYS_ARIA_SRAM_BASE (CONFIG_SYS_SRAM_BASE + \
267 CONFIG_SYS_SRAM_SIZE)
268#define CONFIG_SYS_ARIA_SRAM_SIZE 0x00100000 /* reserve 1MB-window */
Wolfgang Denk52568c32009-05-16 10:47:46 +0200269
270#define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \
271 CONFIG_SYS_ARIA_SRAM_SIZE)
272#define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000 /* 128 KB */
273
274#define CONFIG_SYS_CS0_CFG 0x05059150
275#define CONFIG_SYS_CS2_CFG ( (5 << 24) | \
276 (5 << 16) | \
277 (1 << 15) | \
278 (0 << 14) | \
279 (0 << 13) | \
280 (1 << 12) | \
281 (0 << 10) | \
282 (3 << 8) | /* 32 bit */ \
283 (0 << 7) | \
284 (1 << 6) | \
285 (1 << 4) | \
286 (0 << 3) | \
287 (0 << 2) | \
288 (0 << 1) | \
289 (0 << 0) \
290 )
291#define CONFIG_SYS_CS6_CFG 0x05059150
292
293/* Use alternative CS timing for CS0 and CS2 */
294#define CONFIG_SYS_CS_ALETIMING 0x00000005
295
296/* Use SRAM for initial stack */
297#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
Wolfgang Denk553f0982010-10-26 13:32:32 +0200298#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE
Wolfgang Denk52568c32009-05-16 10:47:46 +0200299
Wolfgang Denk553f0982010-10-26 13:32:32 +0200300#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200301 GENERATED_GBL_DATA_SIZE)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200302#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
303
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200304#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200305#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200306
307#ifdef CONFIG_FSL_DIU_FB
308#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
309#else
310#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
311#endif
312
313/* FPGA */
314#define CONFIG_ARIA_FPGA 1
315
316/*
317 * Serial Port
318 */
319#define CONFIG_CONS_INDEX 1
Wolfgang Denk52568c32009-05-16 10:47:46 +0200320
321/*
322 * Serial console configuration
323 */
324#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */
Marek Vasutbfb31272012-09-16 16:07:24 +0200325#define CONFIG_SYS_PSC3
Wolfgang Denk52568c32009-05-16 10:47:46 +0200326#if CONFIG_PSC_CONSOLE != 3
327#error CONFIG_PSC_CONSOLE must be 3
328#endif
329
330#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
331#define CONFIG_SYS_BAUDRATE_TABLE \
332 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
333
334#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
335#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
336#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
337#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
338
339#define CONFIG_CMDLINE_EDITING 1 /* command line history */
340/* Use the HUSH parser */
341#define CONFIG_SYS_HUSH_PARSER
342#ifdef CONFIG_SYS_HUSH_PARSER
Wolfgang Denk52568c32009-05-16 10:47:46 +0200343#endif
344
345/*
346 * PCI
347 */
348#ifdef CONFIG_PCI
349
350#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
351#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
352#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
353#define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + \
354 CONFIG_SYS_PCI_MEM_SIZE)
355#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
356#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
357#define CONFIG_SYS_PCI_IO_BASE 0x00000000
358#define CONFIG_SYS_PCI_IO_PHYS 0x84000000
359#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */
360
361#define CONFIG_PCI_PNP /* do pci plug-and-play */
362
363#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
364
365#endif
366
367/* I2C */
368#define CONFIG_HARD_I2C /* I2C with hardware support */
369#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
370#define CONFIG_I2C_MULTI_BUS
Wolfgang Denk52568c32009-05-16 10:47:46 +0200371
372/* I2C speed and slave address */
373#define CONFIG_SYS_I2C_SPEED 100000
374#define CONFIG_SYS_I2C_SLAVE 0x7F
375#if 0
376#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
377#endif
378
379/*
380 * IIM - IC Identification Module
381 */
382#undef CONFIG_IIM
383
384/*
385 * EEPROM configuration for Atmel AT24C32A-10TQ-2.7:
386 * 16-bit addresses, 10ms write delay, 32-Byte Page Write Mode
387 */
388#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
389#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
390#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
391#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
392
393/*
394 * Ethernet configuration
395 */
396#define CONFIG_MPC512x_FEC 1
Wolfgang Denk52568c32009-05-16 10:47:46 +0200397#define CONFIG_PHY_ADDR 0x17
398#define CONFIG_MII 1 /* MII PHY management */
399#define CONFIG_FEC_AN_TIMEOUT 1
400#define CONFIG_HAS_ETH0
401
402/*
403 * Environment
404 */
405#define CONFIG_ENV_IS_IN_FLASH 1
406/* This has to be a multiple of the flash sector size */
407#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
408 CONFIG_SYS_MONITOR_LEN)
409#define CONFIG_ENV_SIZE 0x2000
410#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) */
411
412/* Address and size of Redundant Environment Sector */
413#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
414 CONFIG_ENV_SECT_SIZE)
415#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
416
417#define CONFIG_LOADS_ECHO 1
418#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
419
420#include <config_cmd_default.h>
421
422#define CONFIG_CMD_ASKENV
423#define CONFIG_CMD_DHCP
424#define CONFIG_CMD_EEPROM
425#undef CONFIG_CMD_FUSE
426#define CONFIG_CMD_I2C
427#undef CONFIG_CMD_IDE
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200428#define CONFIG_CMD_JFFS2
Wolfgang Denk52568c32009-05-16 10:47:46 +0200429#define CONFIG_CMD_MII
430#define CONFIG_CMD_NFS
431#define CONFIG_CMD_PING
432#define CONFIG_CMD_REGINFO
433
434#if defined(CONFIG_PCI)
435#define CONFIG_CMD_PCI
436#endif
437
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200438#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200439#define CONFIG_DOS_PARTITION
440#define CONFIG_MAC_PARTITION
441#define CONFIG_ISO_PARTITION
442#endif /* defined(CONFIG_CMD_IDE) */
443
444/*
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200445 * Dynamic MTD partition support
446 */
447#define CONFIG_CMD_MTDPARTS
448#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
449#define CONFIG_FLASH_CFI_MTD
450#define MTDIDS_DEFAULT "nor0=f8000000.flash,nand0=mpc5121.nand"
451
452/*
453 * NOR flash layout:
454 *
455 * F8000000 - FEAFFFFF 107 MiB User Data
456 * FEB00000 - FFAFFFFF 16 MiB Root File System
457 * FFB00000 - FFFEFFFF 4 MiB Linux Kernel
458 * FFF00000 - FFFBFFFF 768 KiB U-Boot (up to 512 KiB) and 2 x * env
459 * FFFC0000 - FFFFFFFF 256 KiB Device Tree
460 *
461 * NAND flash layout: one big partition
462 */
463#define MTDPARTS_DEFAULT "mtdparts=f8000000.flash:107m(user)," \
464 "16m(rootfs)," \
465 "4m(kernel)," \
466 "768k(u-boot)," \
467 "256k(dtb);" \
468 "mpc5121.nand:-(data)"
469
470/*
Wolfgang Denk52568c32009-05-16 10:47:46 +0200471 * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
472 * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE
473 * is set to 0xFFFF, watchdog timeouts after about 64s. For details
474 * refer to chapter 36 of the MPC5121e Reference Manual.
475 */
476/* #define CONFIG_WATCHDOG */ /* enable watchdog */
477#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
478
479 /*
480 * Miscellaneous configurable options
481 */
482#define CONFIG_SYS_LONGHELP /* undef to save memory */
483#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
484#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
485
486#ifdef CONFIG_CMD_KGDB
487# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
488#else
489# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
490#endif
491
492/* Print Buffer Size */
493#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
494 sizeof(CONFIG_SYS_PROMPT) + 16)
495/* max number of command args */
496#define CONFIG_SYS_MAXARGS 32
497/* Boot Argument Buffer Size */
498#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
499
500#define CONFIG_SYS_HZ 1000
501
502/*
503 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700504 * have to be in the first 256 MB of memory, since this is
Wolfgang Denk52568c32009-05-16 10:47:46 +0200505 * the maximum mapped by the Linux kernel during initialization.
506 */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700507#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200508
509/* Cache Configuration */
510#define CONFIG_SYS_DCACHE_SIZE 32768
511#define CONFIG_SYS_CACHELINE_SIZE 32
512#ifdef CONFIG_CMD_KGDB
513#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */
514#endif
515
516#define CONFIG_SYS_HID0_INIT 0x000000000
517#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
518 HID0_ICE)
519#define CONFIG_SYS_HID2 HID2_HBE
520
521#define CONFIG_HIGH_BATS 1 /* High BATs supported */
522
Wolfgang Denk52568c32009-05-16 10:47:46 +0200523#ifdef CONFIG_CMD_KGDB
524#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
525#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
526#endif
527
528/*
529 * Environment Configuration
530 */
531#define CONFIG_ENV_OVERWRITE
532#define CONFIG_TIMESTAMP
533
534#define CONFIG_HOSTNAME aria
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000535#define CONFIG_BOOTFILE "aria/uImage"
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000536#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
Wolfgang Denk52568c32009-05-16 10:47:46 +0200537
538#define CONFIG_LOADADDR 400000 /* default load addr */
539
540#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
541#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
542
543#define CONFIG_BAUDRATE 115200
544
545#define CONFIG_PREBOOT "echo;" \
546 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
547 "echo"
548
549#define CONFIG_EXTRA_ENV_SETTINGS \
550 "u-boot_addr_r=200000\0" \
551 "kernel_addr_r=600000\0" \
552 "fdt_addr_r=880000\0" \
553 "ramdisk_addr_r=900000\0" \
554 "u-boot_addr=FFF00000\0" \
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200555 "kernel_addr=FFB00000\0" \
556 "fdt_addr=FFFC0000\0" \
557 "ramdisk_addr=FEB00000\0" \
Wolfgang Denk52568c32009-05-16 10:47:46 +0200558 "ramdiskfile=aria/uRamdisk\0" \
559 "u-boot=aria/u-boot.bin\0" \
560 "fdtfile=aria/aria.dtb\0" \
561 "netdev=eth0\0" \
562 "consdev=ttyPSC0\0" \
563 "nfsargs=setenv bootargs root=/dev/nfs rw " \
564 "nfsroot=${serverip}:${rootpath}\0" \
565 "ramargs=setenv bootargs root=/dev/ram rw\0" \
566 "addip=setenv bootargs ${bootargs} " \
567 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
568 ":${hostname}:${netdev}:off panic=1\0" \
569 "addtty=setenv bootargs ${bootargs} " \
570 "console=${consdev},${baudrate}\0" \
571 "flash_nfs=run nfsargs addip addtty;" \
572 "bootm ${kernel_addr} - ${fdt_addr}\0" \
573 "flash_self=run ramargs addip addtty;" \
574 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
575 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
576 "tftp ${fdt_addr_r} ${fdtfile};" \
577 "run nfsargs addip addtty;" \
578 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
579 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
580 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
581 "tftp ${fdt_addr_r} ${fdtfile};" \
582 "run ramargs addip addtty;" \
583 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
584 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
585 "update=protect off ${u-boot_addr} +${filesize};" \
586 "era ${u-boot_addr} +${filesize};" \
587 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
588 "upd=run load update\0" \
589 ""
590
591#define CONFIG_BOOTCOMMAND "run flash_self"
592
593#define CONFIG_OF_LIBFDT 1
594#define CONFIG_OF_BOARD_SETUP 1
595#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
596
597#define OF_CPU "PowerPC,5121@0"
598#define OF_SOC_COMPAT "fsl,mpc5121-immr"
599#define OF_TBCLK (bd->bi_busfreq / 4)
600#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
601
602/*-----------------------------------------------------------------------
603 * IDE/ATA stuff
604 *-----------------------------------------------------------------------
605 */
606
607#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
608#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
609#undef CONFIG_IDE_LED /* LED for IDE not supported */
610
611#define CONFIG_IDE_RESET /* reset for IDE supported */
612#define CONFIG_IDE_PREINIT
613
614#define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */
615#define CONFIG_SYS_IDE_MAXDEVICE 2 /* 1 drive per IDE bus */
616
617#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
618#define CONFIG_SYS_ATA_BASE_ADDR get_pata_base()
619
620/* Offset for data I/O RefMan MPC5121EE Table 28-10 */
621#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
622
623/* Offset for normal register accesses */
624#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
625
626/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */
627#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
628
629/* Interval between registers */
630#define CONFIG_SYS_ATA_STRIDE 4
631
632#define ATA_BASE_ADDR get_pata_base()
633
634/*
635 * Control register bit definitions
636 */
637#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
638#define FSL_ATA_CTRL_ATA_RST_B 0x40000000
639#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
640#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
641#define FSL_ATA_CTRL_DMA_PENDING 0x08000000
642#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
643#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
644#define FSL_ATA_CTRL_IORDY_EN 0x01000000
645
646#endif /* __CONFIG_H */