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wdenk7abf0c52004-04-18 21:45:42 +00001/*
2 * (C) Copyright 2003 Embedded Edge, LLC
3 * Dan Malek <dan@embeddededge.com>
4 * Copied from ADS85xx.
5 * Updates for Silicon Tx GP3 8560 board.
6 *
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/* mpc8560ads board configuration file */
30/* please refer to doc/README.mpc85xx for more info */
31/* make sure you change the MAC address and other network params first,
32 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
38/* High Level Configuration Options */
39#define CONFIG_BOOKE 1 /* BOOKE */
40#define CONFIG_E500 1 /* BOOKE e500 family */
41#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050042#define CONFIG_CPM2 1 /* has CPM2 */
wdenk7abf0c52004-04-18 21:45:42 +000043#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/
Kumar Galaf0600542008-06-11 00:44:10 -050044#define CONFIG_MPC8560 1
wdenk7abf0c52004-04-18 21:45:42 +000045
Wolfgang Denk2ae18242010-10-06 09:05:45 +020046#define CONFIG_SYS_TEXT_BASE 0xfff80000
47
Wolfgang Denk53677ef2008-05-20 16:00:29 +020048#undef CONFIG_PCI /* pci ethernet support */
49#define CONFIG_TSEC_ENET /* tsec ethernet support*/
wdenk7abf0c52004-04-18 21:45:42 +000050#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
51#define CONFIG_ENV_OVERWRITE
wdenk7abf0c52004-04-18 21:45:42 +000052
Kumar Gala572b13a2008-01-16 09:11:53 -060053#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk9aea9532004-08-01 23:02:45 +000054
55/* sysclk for MPC85xx
wdenk7abf0c52004-04-18 21:45:42 +000056 */
wdenk7abf0c52004-04-18 21:45:42 +000057
58#define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */
59
60/* Blinkin' LEDs for Robert :-)
61*/
62#define CONFIG_SHOW_ACTIVITY 1
63
wdenk9aea9532004-08-01 23:02:45 +000064/*
65 * These can be toggled for performance analysis, otherwise use default.
66 */
wdenk7abf0c52004-04-18 21:45:42 +000067#define CONFIG_L2_CACHE /* toggle L2 cache */
wdenk9aea9532004-08-01 23:02:45 +000068#define CONFIG_BTB /* toggle branch predition */
wdenk7abf0c52004-04-18 21:45:42 +000069
wdenk9aea9532004-08-01 23:02:45 +000070#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
Peter Tyser004eca02009-09-16 22:03:08 -050071#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenk7abf0c52004-04-18 21:45:42 +000072
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
74#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
75#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk7abf0c52004-04-18 21:45:42 +000076
wdenk7abf0c52004-04-18 21:45:42 +000077
78/* Localbus SDRAM is an option, not all boards have it.
wdenk9aea9532004-08-01 23:02:45 +000079 * This address, however, is used to configure a 256M local bus
80 * window that includes the Config latch below.
81 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
83#define CONFIG_SYS_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */
wdenk7abf0c52004-04-18 21:45:42 +000084
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
86#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk7abf0c52004-04-18 21:45:42 +000087
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */
89#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
90#define CONFIG_SYS_MAX_FLASH_SECT 136 /* sectors per device */
91#undef CONFIG_SYS_FLASH_CHECKSUM
92#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */
93#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk7abf0c52004-04-18 21:45:42 +000094
95/* The configuration latch is Chip Select 1.
wdenk9aea9532004-08-01 23:02:45 +000096 * It's an 8-bit latch in the lower 8 bits of the word.
wdenk7abf0c52004-04-18 21:45:42 +000097 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_BR1_PRELIM 0xfc001801 /* 32-bit port */
99#define CONFIG_SYS_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
100#define CONFIG_SYS_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */
wdenk7abf0c52004-04-18 21:45:42 +0000101
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200102#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk7abf0c52004-04-18 21:45:42 +0000103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
105#define CONFIG_SYS_RAMBOOT
wdenk7abf0c52004-04-18 21:45:42 +0000106#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#undef CONFIG_SYS_RAMBOOT
wdenk7abf0c52004-04-18 21:45:42 +0000108#endif
109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#ifdef CONFIG_SYS_RAMBOOT
111#define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
wdenk7abf0c52004-04-18 21:45:42 +0000112#endif
Timur Tabie46fedf2011-08-04 18:03:41 -0500113#define CONFIG_SYS_CCSRBAR 0xfdf00000
114#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
wdenk7abf0c52004-04-18 21:45:42 +0000115
Kumar Galac360d9b2008-08-27 01:03:42 -0500116/* DDR Setup */
117#define CONFIG_FSL_DDR1
118#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
119#define CONFIG_DDR_SPD
120#undef CONFIG_FSL_DDR_INTERACTIVE
wdenk7abf0c52004-04-18 21:45:42 +0000121
Kumar Galac360d9b2008-08-27 01:03:42 -0500122#undef CONFIG_DDR_ECC /* only for ECC DDR module */
Becky Bruce810c4422010-12-17 17:17:58 -0600123#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
Kumar Galac360d9b2008-08-27 01:03:42 -0500124#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
wdenk7abf0c52004-04-18 21:45:42 +0000125
Kumar Galac360d9b2008-08-27 01:03:42 -0500126#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
129#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk9aea9532004-08-01 23:02:45 +0000130
Kumar Galac360d9b2008-08-27 01:03:42 -0500131#define CONFIG_NUM_DDR_CONTROLLERS 1
132#define CONFIG_DIMM_SLOTS_PER_CTLR 1
133#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
134
135/* I2C addresses of SPD EEPROMs */
136#define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */
wdenk7abf0c52004-04-18 21:45:42 +0000137
138#undef CONFIG_CLOCKS_IN_MHZ
139
140/* local bus definitions */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
142#define CONFIG_SYS_OR2_PRELIM 0xfc006901
143#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */
144#define CONFIG_SYS_LBC_LBCR 0x00000000
145#define CONFIG_SYS_LBC_LSRT 0x20000000
146#define CONFIG_SYS_LBC_MRTPR 0x20000000
147#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
148#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
149#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
150#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
151#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
wdenk7abf0c52004-04-18 21:45:42 +0000152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_INIT_RAM_LOCK 1
154#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200155#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk7abf0c52004-04-18 21:45:42 +0000156
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200157#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk7abf0c52004-04-18 21:45:42 +0000159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
161#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk7abf0c52004-04-18 21:45:42 +0000162
163/* Serial Port */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200164#define CONFIG_CONS_ON_SCC /* define if console on SCC */
165#undef CONFIG_CONS_NONE /* define if console on something else */
166#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
wdenk7abf0c52004-04-18 21:45:42 +0000167
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200168#define CONFIG_BAUDRATE 38400
wdenk7abf0c52004-04-18 21:45:42 +0000169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk7abf0c52004-04-18 21:45:42 +0000171 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
172
173/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_HUSH_PARSER
175#ifdef CONFIG_SYS_HUSH_PARSER
wdenk7abf0c52004-04-18 21:45:42 +0000176#endif
177
Jon Loeliger20476722006-10-20 15:50:15 -0500178/*
179 * I2C
180 */
181#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
182#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk7abf0c52004-04-18 21:45:42 +0000183#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
185#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk7abf0c52004-04-18 21:45:42 +0000186#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_I2C_NOPROBES {0x00} /* Don't probe these addrs */
wdenk7abf0c52004-04-18 21:45:42 +0000188#else
189/* I did the 'if 0' so we could keep the syntax above if ever needed. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#undef CONFIG_SYS_I2C_NOPROBES
wdenk7abf0c52004-04-18 21:45:42 +0000191#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_I2C_OFFSET 0x3000
wdenk7abf0c52004-04-18 21:45:42 +0000193
wdenk9aea9532004-08-01 23:02:45 +0000194/* RapdIO Map configuration, mapped 1:1.
195*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000
197#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
198#define CONFIG_SYS_RIO_MEM_SIZE 0x200000000 /* 512 M */
wdenk9aea9532004-08-01 23:02:45 +0000199
200/* Standard 8560 PCI addressing, mapped 1:1.
201*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
203#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
204#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
205#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
206#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
207#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16 M */
wdenk7abf0c52004-04-18 21:45:42 +0000208
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200209#if defined(CONFIG_PCI) /* PCI Ethernet card */
wdenk9aea9532004-08-01 23:02:45 +0000210
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200211#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk9aea9532004-08-01 23:02:45 +0000212
213#undef CONFIG_EEPRO100
214#undef CONFIG_TULIP
215
216#if !defined(CONFIG_PCI_PNP)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200217 #define PCI_ENET0_IOADDR 0xe0000000
wdenk7abf0c52004-04-18 21:45:42 +0000218 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200219 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk7abf0c52004-04-18 21:45:42 +0000220#endif
wdenk9aea9532004-08-01 23:02:45 +0000221
222#undef CONFIG_PCI_SCAN_SHOW
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk9aea9532004-08-01 23:02:45 +0000224
225#endif /* CONFIG_PCI */
226
227#if defined(CONFIG_TSEC_ENET)
228
wdenk7abf0c52004-04-18 21:45:42 +0000229#define CONFIG_MII 1 /* MII PHY management */
wdenk9aea9532004-08-01 23:02:45 +0000230
Kim Phillips255a35772007-05-16 16:52:19 -0500231#define CONFIG_TSEC1 1
232#define CONFIG_TSEC1_NAME "TSEC0"
233#define CONFIG_TSEC2 1
234#define CONFIG_TSEC2_NAME "TSEC1"
wdenk9aea9532004-08-01 23:02:45 +0000235
236#define TSEC1_PHY_ADDR 2
237#define TSEC2_PHY_ADDR 4
238#define TSEC1_PHYIDX 0
239#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500240#define TSEC1_FLAGS TSEC_GIGABIT
241#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500242#define CONFIG_ETHPRIME "TSEC0"
wdenk9aea9532004-08-01 23:02:45 +0000243
wdenk7abf0c52004-04-18 21:45:42 +0000244#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
wdenk9aea9532004-08-01 23:02:45 +0000245
wdenk7abf0c52004-04-18 21:45:42 +0000246#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
247#undef CONFIG_ETHER_NONE /* define if ether on something else */
248#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
wdenk9aea9532004-08-01 23:02:45 +0000249
250#if (CONFIG_ETHER_INDEX == 2)
wdenk7abf0c52004-04-18 21:45:42 +0000251 /*
252 * - Rx-CLK is CLK13
253 * - Tx-CLK is CLK14
254 * - Select bus for bd/buffers
255 * - Full duplex
256 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000257 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
258 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
wdenk7abf0c52004-04-18 21:45:42 +0000260#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
wdenk7abf0c52004-04-18 21:45:42 +0000262#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263 #define CONFIG_SYS_FCC_PSMR 0
wdenk7abf0c52004-04-18 21:45:42 +0000264#endif
265 #define FETH2_RST 0x01
wdenk9aea9532004-08-01 23:02:45 +0000266#elif (CONFIG_ETHER_INDEX == 3)
wdenk7abf0c52004-04-18 21:45:42 +0000267 /* need more definitions here for FE3 */
268 #define FETH3_RST 0x80
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200269#endif /* CONFIG_ETHER_INDEX */
wdenk9aea9532004-08-01 23:02:45 +0000270
271/* MDIO is done through the TSEC0 control.
272*/
wdenk7abf0c52004-04-18 21:45:42 +0000273#define CONFIG_MII /* MII PHY management */
274#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
wdenk7abf0c52004-04-18 21:45:42 +0000275
wdenk7abf0c52004-04-18 21:45:42 +0000276#endif
277
278/* Environment */
279/* We use the top boot sector flash, so we have some 16K sectors for env
wdenk7abf0c52004-04-18 21:45:42 +0000280 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200282 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200284 #define CONFIG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */
285 #define CONFIG_ENV_SIZE 0x2000
wdenk7abf0c52004-04-18 21:45:42 +0000286#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200288 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200290 #define CONFIG_ENV_SIZE 0x2000
wdenk7abf0c52004-04-18 21:45:42 +0000291#endif
292
293#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400"
wdenk9aea9532004-08-01 23:02:45 +0000294#define CONFIG_BOOTCOMMAND "bootm 0xff000000 0xff100000"
wdenk7abf0c52004-04-18 21:45:42 +0000295#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
296
297#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk7abf0c52004-04-18 21:45:42 +0000299
Jon Loeliger2835e512007-06-13 13:22:08 -0500300/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500301 * BOOTP options
302 */
303#define CONFIG_BOOTP_BOOTFILESIZE
304#define CONFIG_BOOTP_BOOTPATH
305#define CONFIG_BOOTP_GATEWAY
306#define CONFIG_BOOTP_HOSTNAME
307
308
309/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500310 * Command line configuration.
311 */
312#include <config_cmd_default.h>
313
314#define CONFIG_CMD_PING
315#define CONFIG_CMD_I2C
Becky Bruce199e2622010-06-17 11:37:25 -0500316#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500317
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500319 #undef CONFIG_CMD_SAVEENV
Jon Loeliger2835e512007-06-13 13:22:08 -0500320 #undef CONFIG_CMD_LOADS
wdenk7abf0c52004-04-18 21:45:42 +0000321#else
Jon Loeliger2835e512007-06-13 13:22:08 -0500322 #define CONFIG_CMD_ELF
wdenk7abf0c52004-04-18 21:45:42 +0000323#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500324
325#if defined(CONFIG_PCI)
326 #define CONFIG_CMD_PCI
327#endif
328
329#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
330 #define CONFIG_CMD_MII
331#endif
332
wdenk7abf0c52004-04-18 21:45:42 +0000333
334#undef CONFIG_WATCHDOG /* watchdog disabled */
335
336/*
337 * Miscellaneous configurable options
338 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_LONGHELP /* undef to save memory */
340#define CONFIG_SYS_PROMPT "GPPP=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500341#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk7abf0c52004-04-18 21:45:42 +0000343#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk7abf0c52004-04-18 21:45:42 +0000345#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
347#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
348#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
349#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
350#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk7abf0c52004-04-18 21:45:42 +0000351
352/*
353 * For booting Linux, the board info and command line data
354 * have to be in the first 8 MB of memory, since this is
355 * the maximum mapped by the Linux kernel during initialization.
356 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk7abf0c52004-04-18 21:45:42 +0000358
Jon Loeliger2835e512007-06-13 13:22:08 -0500359#if defined(CONFIG_CMD_KGDB)
wdenk7abf0c52004-04-18 21:45:42 +0000360#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
361#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
362#endif
363
364/*Note: change below for your network setting!!! */
365#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Andy Fleming10327dc2007-08-16 16:35:02 -0500366#define CONFIG_HAS_ETH0
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200367#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
wdenke2ffd592004-12-31 09:32:47 +0000368#define CONFIG_HAS_ETH1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200369#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
wdenke2ffd592004-12-31 09:32:47 +0000370#define CONFIG_HAS_ETH2
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200371#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
wdenk7abf0c52004-04-18 21:45:42 +0000372#endif
373
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200374#define CONFIG_SERVERIP 192.168.85.1
375#define CONFIG_IPADDR 192.168.85.60
wdenk7abf0c52004-04-18 21:45:42 +0000376#define CONFIG_GATEWAYIP 192.168.85.1
377#define CONFIG_NETMASK 255.255.255.0
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200378#define CONFIG_HOSTNAME STX_GP3
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000379#define CONFIG_ROOTPATH "/gppproot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000380#define CONFIG_BOOTFILE "uImage"
wdenk9aea9532004-08-01 23:02:45 +0000381#define CONFIG_LOADADDR 0x1000000
wdenk7abf0c52004-04-18 21:45:42 +0000382
383#endif /* __CONFIG_H */