blob: 419232483606a9acd11628f9caa27e643569f044 [file] [log] [blame]
wdenk03f5c552004-10-10 21:21:55 +00001/*
2 * Copyright 2004 Freescale Semiconductor.
3 *
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
wdenk03f5c552004-10-10 21:21:55 +000025#include <common.h>
26#include <pci.h>
27#include <asm/processor.h>
28#include <asm/immap_85xx.h>
Wolfgang Denk2d5df632005-07-21 16:14:36 +020029#include <ioports.h>
wdenk03f5c552004-10-10 21:21:55 +000030#include <spd.h>
31
32#include "../common/cadmus.h"
33#include "../common/eeprom.h"
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -050034#include "../common/via.h"
wdenk03f5c552004-10-10 21:21:55 +000035
Jon Loeligerd9b94f22005-07-25 14:05:07 -050036#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
wdenk03f5c552004-10-10 21:21:55 +000037extern void ddr_enable_ecc(unsigned int dram_size);
38#endif
39
40extern long int spd_sdram(void);
41
42void local_bus_init(void);
43void sdram_init(void);
44
Wolfgang Denk2d5df632005-07-21 16:14:36 +020045/*
46 * I/O Port configuration table
47 *
48 * if conf is 1, then that port pin will be configured at boot time
49 * according to the five values podr/pdir/ppar/psor/pdat for that entry
50 */
51
52const iop_conf_t iop_conf_tab[4][32] = {
53
54 /* Port A configuration */
55 { /* conf ppar psor pdir podr pdat */
56 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
57 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
58 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
59 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
60 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
61 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
62 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
63 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
64 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
65 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
66 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
67 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
68 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
69 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
70 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
71 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
72 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
73 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
74 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
75 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
76 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
77 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
78 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
79 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
80 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
81 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
82 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
83 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
84 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
85 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
86 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
87 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
88 },
89
90 /* Port B configuration */
91 { /* conf ppar psor pdir podr pdat */
92 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
93 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
94 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
95 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
96 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
97 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
98 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
99 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
100 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
101 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
102 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
103 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
104 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
105 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
106 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
107 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
108 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
109 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
110 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
111 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
112 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
113 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
114 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
115 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
116 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
117 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
118 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
119 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
120 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
121 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
122 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
123 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
124 },
125
126 /* Port C */
127 { /* conf ppar psor pdir podr pdat */
128 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
129 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
130 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
131 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
132 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
133 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
134 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
135 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
136 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
137 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
138 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
139 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
140 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
141 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
142 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
143 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
144 /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
145 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
146 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
147 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
148 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
149 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
150 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
151 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
152 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
153 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
154 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
155 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
156 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
157 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
158 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
159 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
160 },
161
162 /* Port D */
163 { /* conf ppar psor pdir podr pdat */
164 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
165 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
166 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
167 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
168 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
169 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
170 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
171 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
172 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
173 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
174 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
175 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
176 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
177 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
178 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
179 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
180 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
181 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
182 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
183 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
184 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
185 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
186 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
187 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
188 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
189 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
190 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
191 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
192 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
193 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
194 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
195 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
196 }
197};
198
wdenk5c952cf2004-10-10 21:27:30 +0000199int board_early_init_f (void)
wdenk03f5c552004-10-10 21:21:55 +0000200{
wdenk5c952cf2004-10-10 21:27:30 +0000201 return 0;
wdenk03f5c552004-10-10 21:21:55 +0000202}
203
wdenk5c952cf2004-10-10 21:27:30 +0000204int checkboard (void)
wdenk03f5c552004-10-10 21:21:55 +0000205{
wdenk5c952cf2004-10-10 21:27:30 +0000206 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
207 volatile ccsr_gur_t *gur = &immap->im_gur;
wdenk03f5c552004-10-10 21:21:55 +0000208
wdenk5c952cf2004-10-10 21:27:30 +0000209 /* PCI slot in USER bits CSR[6:7] by convention. */
210 uint pci_slot = get_pci_slot ();
wdenk03f5c552004-10-10 21:21:55 +0000211
wdenk5c952cf2004-10-10 21:27:30 +0000212 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
213 uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
214 uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
215 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
wdenk03f5c552004-10-10 21:21:55 +0000216
wdenk5c952cf2004-10-10 21:27:30 +0000217 uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
wdenk03f5c552004-10-10 21:21:55 +0000218
wdenk5c952cf2004-10-10 21:27:30 +0000219 uint cpu_board_rev = get_cpu_board_revision ();
wdenk03f5c552004-10-10 21:21:55 +0000220
wdenk5c952cf2004-10-10 21:27:30 +0000221 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
222 get_board_version (), pci_slot);
wdenk03f5c552004-10-10 21:21:55 +0000223
wdenk5c952cf2004-10-10 21:27:30 +0000224 printf ("CPU Board Revision %d.%d (0x%04x)\n",
225 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
226 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
wdenk03f5c552004-10-10 21:21:55 +0000227
wdenk5c952cf2004-10-10 21:27:30 +0000228 printf (" PCI1: %d bit, %s MHz, %s\n",
229 (pci1_32) ? 32 : 64,
230 (pci1_speed == 33000000) ? "33" :
231 (pci1_speed == 66000000) ? "66" : "unknown",
232 pci1_clk_sel ? "sync" : "async");
wdenk03f5c552004-10-10 21:21:55 +0000233
wdenk5c952cf2004-10-10 21:27:30 +0000234 if (pci_dual) {
235 printf (" PCI2: 32 bit, 66 MHz, %s\n",
236 pci2_clk_sel ? "sync" : "async");
237 } else {
238 printf (" PCI2: disabled\n");
239 }
wdenk03f5c552004-10-10 21:21:55 +0000240
wdenk5c952cf2004-10-10 21:27:30 +0000241 /*
242 * Initialize local bus.
243 */
244 local_bus_init ();
wdenk03f5c552004-10-10 21:21:55 +0000245
wdenk5c952cf2004-10-10 21:27:30 +0000246 return 0;
wdenk03f5c552004-10-10 21:21:55 +0000247}
248
wdenk03f5c552004-10-10 21:21:55 +0000249long int
250initdram(int board_type)
251{
252 long dram_size = 0;
253 volatile immap_t *immap = (immap_t *)CFG_IMMR;
254
255 puts("Initializing\n");
256
257#if defined(CONFIG_DDR_DLL)
258 {
259 /*
260 * Work around to stabilize DDR DLL MSYNC_IN.
261 * Errata DDR9 seems to have been fixed.
262 * This is now the workaround for Errata DDR11:
263 * Override DLL = 1, Course Adj = 1, Tap Select = 0
264 */
265
266 volatile ccsr_gur_t *gur= &immap->im_gur;
267
268 gur->ddrdllcr = 0x81000000;
269 asm("sync;isync;msync");
270 udelay(200);
271 }
272#endif
wdenk03f5c552004-10-10 21:21:55 +0000273 dram_size = spd_sdram();
274
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500275#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
wdenk03f5c552004-10-10 21:21:55 +0000276 /*
277 * Initialize and enable DDR ECC.
278 */
279 ddr_enable_ecc(dram_size);
280#endif
wdenk03f5c552004-10-10 21:21:55 +0000281 /*
282 * SDRAM Initialization
283 */
284 sdram_init();
285
286 puts(" DDR: ");
287 return dram_size;
288}
289
wdenk03f5c552004-10-10 21:21:55 +0000290/*
291 * Initialize Local Bus
292 */
wdenk03f5c552004-10-10 21:21:55 +0000293void
294local_bus_init(void)
295{
296 volatile immap_t *immap = (immap_t *)CFG_IMMR;
297 volatile ccsr_gur_t *gur = &immap->im_gur;
298 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
299
300 uint clkdiv;
301 uint lbc_hz;
302 sys_info_t sysinfo;
303 uint temp_lbcdll;
304
305 /*
306 * Errata LBC11.
307 * Fix Local Bus clock glitch when DLL is enabled.
308 *
309 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
310 * If localbus freq is > 133Mhz, DLL can be safely enabled.
311 * Between 66 and 133, the DLL is enabled with an override workaround.
312 */
313
314 get_sys_info(&sysinfo);
315 clkdiv = lbc->lcrr & 0x0f;
316 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
317
318 if (lbc_hz < 66) {
319 lbc->lcrr |= 0x80000000; /* DLL Bypass */
320
321 } else if (lbc_hz >= 133) {
322 lbc->lcrr &= (~0x80000000); /* DLL Enabled */
323
324 } else {
325 lbc->lcrr &= (~0x8000000); /* DLL Enabled */
326 udelay(200);
327
328 /*
329 * Sample LBC DLL ctrl reg, upshift it to set the
330 * override bits.
331 */
332 temp_lbcdll = gur->lbcdllcr;
333 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
334 asm("sync;isync;msync");
335 }
336}
337
wdenk03f5c552004-10-10 21:21:55 +0000338/*
339 * Initialize SDRAM memory on the Local Bus.
340 */
wdenk03f5c552004-10-10 21:21:55 +0000341void
342sdram_init(void)
343{
344#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
345
346 uint idx;
347 volatile immap_t *immap = (immap_t *)CFG_IMMR;
348 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
349 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
350 uint cpu_board_rev;
351 uint lsdmr_common;
352
353 puts(" SDRAM: ");
354
355 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
356
357 /*
358 * Setup SDRAM Base and Option Registers
359 */
360 lbc->or2 = CFG_OR2_PRELIM;
361 asm("msync");
362
363 lbc->br2 = CFG_BR2_PRELIM;
364 asm("msync");
365
366 lbc->lbcr = CFG_LBC_LBCR;
367 asm("msync");
368
369
370 lbc->lsrt = CFG_LBC_LSRT;
371 lbc->mrtpr = CFG_LBC_MRTPR;
372 asm("msync");
373
374 /*
375 * Determine which address lines to use baed on CPU board rev.
376 */
377 cpu_board_rev = get_cpu_board_revision();
378 lsdmr_common = CFG_LBC_LSDMR_COMMON;
379 if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
380 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
381 } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
382 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
383 } else {
384 /*
385 * Assume something unable to identify itself is
386 * really old, and likely has lines 16/17 mapped.
387 */
388 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
389 }
390
391 /*
392 * Issue PRECHARGE ALL command.
393 */
394 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
395 asm("sync;msync");
396 *sdram_addr = 0xff;
397 ppcDcbf((unsigned long) sdram_addr);
398 udelay(100);
399
400 /*
401 * Issue 8 AUTO REFRESH commands.
402 */
403 for (idx = 0; idx < 8; idx++) {
404 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
405 asm("sync;msync");
406 *sdram_addr = 0xff;
407 ppcDcbf((unsigned long) sdram_addr);
408 udelay(100);
409 }
410
411 /*
412 * Issue 8 MODE-set command.
413 */
414 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
415 asm("sync;msync");
416 *sdram_addr = 0xff;
417 ppcDcbf((unsigned long) sdram_addr);
418 udelay(100);
419
420 /*
421 * Issue NORMAL OP command.
422 */
423 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
424 asm("sync;msync");
425 *sdram_addr = 0xff;
426 ppcDcbf((unsigned long) sdram_addr);
427 udelay(200); /* Overkill. Must wait > 200 bus cycles */
428
429#endif /* enable SDRAM init */
430}
431
wdenk03f5c552004-10-10 21:21:55 +0000432#if defined(CFG_DRAM_TEST)
433int
434testdram(void)
435{
436 uint *pstart = (uint *) CFG_MEMTEST_START;
437 uint *pend = (uint *) CFG_MEMTEST_END;
438 uint *p;
439
440 printf("Testing DRAM from 0x%08x to 0x%08x\n",
441 CFG_MEMTEST_START,
442 CFG_MEMTEST_END);
443
444 printf("DRAM test phase 1:\n");
445 for (p = pstart; p < pend; p++)
446 *p = 0xaaaaaaaa;
447
448 for (p = pstart; p < pend; p++) {
449 if (*p != 0xaaaaaaaa) {
450 printf ("DRAM test fails at: %08x\n", (uint) p);
451 return 1;
452 }
453 }
454
455 printf("DRAM test phase 2:\n");
456 for (p = pstart; p < pend; p++)
457 *p = 0x55555555;
458
459 for (p = pstart; p < pend; p++) {
460 if (*p != 0x55555555) {
461 printf ("DRAM test fails at: %08x\n", (uint) p);
462 return 1;
463 }
464 }
465
466 printf("DRAM test passed.\n");
467 return 0;
468}
469#endif
470
wdenk03f5c552004-10-10 21:21:55 +0000471#if defined(CONFIG_PCI)
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500472/* For some reason the Tundra PCI bridge shows up on itself as a
473 * different device. Work around that by refusing to configure it.
wdenk03f5c552004-10-10 21:21:55 +0000474 */
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500475void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
wdenk03f5c552004-10-10 21:21:55 +0000476
wdenk03f5c552004-10-10 21:21:55 +0000477static struct pci_config_table pci_mpc85xxcds_config_table[] = {
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500478 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
479 {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
Andy Flemingffa621a2007-02-24 01:08:13 -0600480 {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
481 mpc85xx_config_via_usbide, {0,0,0}},
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500482 {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
483 {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
Andy Flemingffa621a2007-02-24 01:08:13 -0600484 {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
485 mpc85xx_config_via_power, {0,0,0}},
486 {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
487 {},
wdenk03f5c552004-10-10 21:21:55 +0000488};
wdenk03f5c552004-10-10 21:21:55 +0000489
Matthew McClintockcbfc7ce2006-06-28 10:46:13 -0500490static struct pci_controller hose[] = {
491 { config_table: pci_mpc85xxcds_config_table,},
492#ifdef CONFIG_MPC85XX_PCI2
493 {},
wdenk03f5c552004-10-10 21:21:55 +0000494#endif
495};
496
497#endif /* CONFIG_PCI */
498
wdenk03f5c552004-10-10 21:21:55 +0000499void
500pci_init_board(void)
501{
502#ifdef CONFIG_PCI
Matthew McClintock7376eb82006-10-11 15:13:01 -0500503 pci_mpc85xx_init(hose);
wdenk03f5c552004-10-10 21:21:55 +0000504#endif
505}