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Hugo Villeneuvec7f879e2008-05-21 13:58:41 -04001/*
2 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
3 *
Hugo Villeneuve2b1fa9d2008-07-08 11:02:05 -04004 * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
5 * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -04008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040012
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040013/* Board */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040014#define SFFSDR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020015#define CONFIG_SYS_NAND_LARGEPAGE
16#define CONFIG_SYS_USE_NAND
David Brownell7a4f5112009-05-15 23:47:12 +020017#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040018/* SoC Configuration */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040019#define CONFIG_ARM926EJS /* arm926ejs CPU core */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020020#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
21#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
David Brownellf7904362009-05-15 23:44:08 +020022#define CONFIG_SOC_DM644X
Hugo Villeneuve2b1fa9d2008-07-08 11:02:05 -040023/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020024#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
25#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
26#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
27#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040028/* Memory Info */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020030#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
31#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040032#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040033#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
34#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
35#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040036/* Serial Driver info */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037#define CONFIG_SYS_NS16550
38#define CONFIG_SYS_NS16550_SERIAL
David Brownell7ee38c02009-04-12 15:38:06 -070039#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
David Brownell7239c5da2009-04-12 15:40:16 -070041#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040042#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
43#define CONFIG_BAUDRATE 115200 /* Default baud rate */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040044/* I2C Configuration */
Vitaly Andrianove8459dc2014-04-04 13:16:52 -040045#define CONFIG_SYS_I2C
46#define CONFIG_SYS_I2C_DAVINCI
47#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
48#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040049/* Network & Ethernet Configuration */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040050#define CONFIG_DRIVER_TI_EMAC
51#define CONFIG_MII
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040052#define CONFIG_BOOTP_DNS
53#define CONFIG_BOOTP_DNS2
54#define CONFIG_BOOTP_SEND_HOSTNAME
55#define CONFIG_NET_RETRY_COUNT 10
56#define CONFIG_OVERWRITE_ETHADDR_ONCE
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040057/* Flash & Environment */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020058#undef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_NO_FLASH
Jean-Christophe PLAGNIOL-VILLARDee4f3e22009-03-30 18:58:39 +020060#define CONFIG_NAND_DAVINCI
Nick Thompson97f4eb82009-12-12 12:12:26 -050061#define CONFIG_SYS_NAND_CS 2
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +020062#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020063#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
Sandeep Paulraja16df2c2009-09-08 17:09:52 -040064#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040065#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_NAND_BASE 0x02000000
67#define CONFIG_SYS_NAND_HW_ECC
68#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020069#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
Hugo Villeneuve2b1fa9d2008-07-08 11:02:05 -040070/* I2C switch definitions for PCA9543 chip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_I2C_PCA9543_ADDR 0x70
72#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN 0 /* Single register. */
73#define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040074/* U-Boot general configuration */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040075#define CONFIG_MISC_INIT_R
Hugo Villeneuve2b1fa9d2008-07-08 11:02:05 -040076#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040077#define CONFIG_BOOTFILE "uImage" /* Boot file name */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */
79#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
80#define CONFIG_SYS_PBSIZE \
81 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */
82#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
83#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
84#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* Default Linux kernel
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040085 * load address. */
86#define CONFIG_VERSION_VARIABLE
87#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far,
88 * may be later */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_HUSH_PARSER
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040090#define CONFIG_CMDLINE_EDITING
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_LONGHELP
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040092#define CONFIG_CRC32_VERIFY
93#define CONFIG_MX_CYCLIC
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040094/* Linux Information */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -040095#define LINUX_BOOT_PARAM_ADDR 0x80000100
96#define CONFIG_CMDLINE_TAG
97#define CONFIG_SETUP_MEMORY_TAGS
Hugo Villeneuve2b1fa9d2008-07-08 11:02:05 -040098#define CONFIG_BOOTARGS \
99 "mem=56M " \
100 "console=ttyS0,115200n8 " \
101 "root=/dev/nfs rw noinitrd ip=dhcp " \
102 "nfsroot=${serverip}:/nfsroot/sffsdr " \
103 "eth0=${ethaddr}"
104#define CONFIG_BOOTCOMMAND \
105 "nand read 87A00000 100000 300000;" \
106 "bootelf 87A00000"
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400107/* U-Boot commands */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400108#include <config_cmd_default.h>
109#define CONFIG_CMD_ASKENV
110#define CONFIG_CMD_DHCP
111#define CONFIG_CMD_DIAG
112#define CONFIG_CMD_I2C
113#define CONFIG_CMD_MII
114#define CONFIG_CMD_PING
115#define CONFIG_CMD_SAVES
116#define CONFIG_CMD_NAND
117#define CONFIG_CMD_EEPROM
Hugo Villeneuvec15947d2008-07-10 10:46:33 -0400118#define CONFIG_CMD_ELF /* Needed to load Integrity kernel. */
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400119#undef CONFIG_CMD_BDI
120#undef CONFIG_CMD_FPGA
121#undef CONFIG_CMD_SETGETDCR
122#undef CONFIG_CMD_FLASH
123#undef CONFIG_CMD_IMLS
Sandeep Paulrajebc3c6c2010-12-11 20:38:12 -0500124
Hadli, Manjunath8f5d4682012-02-06 00:30:44 +0000125#ifdef CONFIG_CMD_BDI
126#define CONFIG_CLOCKS
127#endif
128
Sandeep Paulrajebc3c6c2010-12-11 20:38:12 -0500129#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
130
131#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
132#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
133#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
134 CONFIG_SYS_INIT_RAM_SIZE - \
135 GENERATED_GBL_DATA_SIZE)
136
Hugo Villeneuvec7f879e2008-05-21 13:58:41 -0400137#endif /* __CONFIG_H */