Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0+ |
Jean-Christophe PLAGNIOL-VILLARD | c8aa7df | 2008-10-31 12:26:55 +0100 | [diff] [blame] | 2 | # |
| 3 | # (C) Copyright 2008 |
| 4 | # Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
Jean-Christophe PLAGNIOL-VILLARD | c8aa7df | 2008-10-31 12:26:55 +0100 | [diff] [blame] | 5 | |
Masahiro Yamada | 710f1d3 | 2013-10-17 17:34:57 +0900 | [diff] [blame] | 6 | obj-y += fpga.o |
Alexander Dahl | 1323d08 | 2022-09-30 14:04:30 +0200 | [diff] [blame] | 7 | obj-$(CONFIG_DM_FPGA) += fpga-uclass.o |
| 8 | obj-$(CONFIG_SANDBOX_FPGA) += sandbox.o |
| 9 | |
Masahiro Yamada | 710f1d3 | 2013-10-17 17:34:57 +0900 | [diff] [blame] | 10 | obj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o |
| 11 | obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o |
Siva Durga Prasad Paladugu | 26e054c | 2019-08-05 15:54:59 +0530 | [diff] [blame] | 12 | obj-$(CONFIG_FPGA_VERSALPL) += versalpl.o |
Masahiro Yamada | 710f1d3 | 2013-10-17 17:34:57 +0900 | [diff] [blame] | 13 | obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o |
| 14 | obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o |
Siva Durga Prasad Paladugu | 6b24501 | 2016-01-13 16:25:37 +0530 | [diff] [blame] | 15 | obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o |
Masahiro Yamada | 710f1d3 | 2013-10-17 17:34:57 +0900 | [diff] [blame] | 16 | obj-$(CONFIG_FPGA_XILINX) += xilinx.o |
| 17 | obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o |
Jean-Christophe PLAGNIOL-VILLARD | c8aa7df | 2008-10-31 12:26:55 +0100 | [diff] [blame] | 18 | ifdef CONFIG_FPGA_ALTERA |
Masahiro Yamada | 710f1d3 | 2013-10-17 17:34:57 +0900 | [diff] [blame] | 19 | obj-y += altera.o |
| 20 | obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o |
| 21 | obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o |
Chee Hong Ang | d217016 | 2020-08-07 11:50:03 +0800 | [diff] [blame] | 22 | obj-$(CONFIG_FPGA_INTEL_SDM_MAILBOX) += intel_sdm_mb.o |
Masahiro Yamada | 710f1d3 | 2013-10-17 17:34:57 +0900 | [diff] [blame] | 23 | obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o |
Stefan Roese | ff9c4c5 | 2016-02-12 13:48:02 +0100 | [diff] [blame] | 24 | obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o |
Pavel Machek | 230fe9b | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 25 | obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o |
Tien Fong Chee | 6867e19 | 2017-07-26 13:05:38 +0800 | [diff] [blame] | 26 | obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o |
Tien Fong Chee | 2baa997 | 2017-07-26 13:05:43 +0800 | [diff] [blame] | 27 | obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o |
Jean-Christophe PLAGNIOL-VILLARD | c8aa7df | 2008-10-31 12:26:55 +0100 | [diff] [blame] | 28 | endif |