1. 0cf207e WS cleanup: remove SPACE(s) followed by TAB by Wolfgang Denk · 3 years ago
  2. c05ed00 common: Drop linux/delay.h from common header by Simon Glass · 4 years, 5 months ago
  3. 9b4a205 common: Move RAM-sizing functions to init.h by Simon Glass · 4 years, 9 months ago
  4. 297963f sunxi: Fix typos of spelling Allwinner by Priit Laes · 6 years ago
  5. 83d290c SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · 6 years ago
  6. e6e505b sunxi: Move cpu independent code to mach directory by Alexander Graf · 8 years ago[Renamed from arch/arm/cpu/armv7/sunxi/dram_sun4i.c]
  7. 8975cdf sunxi: Make DRAM_ODT_EN Kconfig setting a bool by Hans de Goede · 9 years ago
  8. 07f4fe7 sunxi: Move await_completion dram helper to dram.h by Hans de Goede · 10 years ago
  9. 9d4b7d0 sun4i: Rename dram_clk_cfg to dram_clk_gate by Hans de Goede · 10 years ago
  10. bec72c7 sun4i: Rename dram files to dram_sun4i.x by Hans de Goede · 10 years ago[Renamed from arch/arm/cpu/armv7/sunxi/dram.c]
  11. ed41e62 sunxi: Use CONFIG_MACH_SUN?I from Kconfig instead of CONFIG_SUN?I by Ian Campbell · 10 years ago
  12. accc9e4 sunxi: Add CONFIG_OLD_SUNXI_KERNEL_COMPAT Kconfig option by Hans de Goede · 10 years ago
  13. d0dbc28 sunxi: dram: Use clock_get_pll5p to calculate mbus, rather then hardcoding by Hans de Goede · 10 years ago
  14. bf4ca38 sunxi: dram: Autodetect DDR3 bus width and density by Siarhei Siamashka · 10 years ago
  15. 935758b sunxi: dram: Derive write recovery delay from DRAM clock speed by Siarhei Siamashka · 10 years ago
  16. b5c71f5 sunxi: dram: Drop DDR2 support and assume only single rank DDR3 memory by Siarhei Siamashka · 10 years ago
  17. d755a5f sunxi: dram: Configurable DQS gating window mode and delay by Siarhei Siamashka · 10 years ago
  18. e044daa sunxi: dram: Add a helper function 'mctl_get_number_of_lanes' by Siarhei Siamashka · 10 years ago
  19. b8f7cb6 sunxi: dram: Improve DQS gate data training error handling by Siarhei Siamashka · 10 years ago
  20. 013f2d7 sunxi: dram: Use divisor P=1 for PLL5 by Siarhei Siamashka · 10 years ago
  21. 1a9717c sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6) by Siarhei Siamashka · 10 years ago
  22. 5c18384 sunxi: dram: Re-introduce the impedance calibration ond ODT by Siarhei Siamashka · 10 years ago
  23. 94cd301 sunxi: dram: Add 'await_bits_clear'/'await_bits_set' helper functions by Siarhei Siamashka · 10 years ago
  24. cfc89b0 sunxi: dram: Do DDR3 reset in the same way on sun4i/sun5i/sun7i by Siarhei Siamashka · 10 years ago
  25. 7e40e19 sunxi: dram: Remove broken impedance and ODT configuration code by Siarhei Siamashka · 10 years ago
  26. f8e88b6 sunxi: dram: Fix CKE delay handling for sun4i/sun5i by Siarhei Siamashka · 10 years ago
  27. e626d2d sunxi: dram: Respect the DDR3 reset timing requirements by Siarhei Siamashka · 10 years ago
  28. f257796 sunxi: dram: Remove broken super-standby remnants by Siarhei Siamashka · 10 years ago
  29. 34759d7 sunxi: dram: Remove useless 'dramc_scan_dll_para()' function by Siarhei Siamashka · 10 years ago
  30. f84269c sunxi: Add sun5i support by Hans de Goede · 10 years ago
  31. 745325a sunxi: Add sun4i support by Hans de Goede · 10 years ago
  32. 286c3c3 sunxi: add sun7i dram setup support by Ian Campbell · 10 years ago