- a6d7e8c riscv: Split SiFive CLINT support between SPL and U-Boot proper by Bin Meng · 3 years, 6 months ago
- ffdc71b Revert "riscv: cpu: fu740: clear feature disable CSR" by Bin Meng · 3 years, 6 months ago
- bc8bbb7 riscv: cpu: fu740: clear feature disable CSR by Green Wan · 3 years, 6 months ago
- 529d5f9 cpu: Rename SPL_CPU_SUPPORT to SPL_CPU by Simon Glass · 3 years, 8 months ago
- 2ae8043 Merge branch '2021-02-02-drop-asm_global_data-when-unused' by Tom Rini · 3 years, 9 months ago
- 85c714d riscv: Adjust board_get_usable_ram_top() for 32-bit by Bin Meng · 3 years, 9 months ago
- 401d1c4 common: Drop asm/global_data.h from common header by Simon Glass · 4 years ago
- f517e5f riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controller by Pragnesh Patel · 4 years ago
- c33efaf riscv: Rework riscv timer driver to only support S-mode by Sean Anderson · 4 years, 1 month ago
- 52dc7ae riscv: fu540: Use correct API to get L2 cache controller base address by Bin Meng · 4 years, 3 months ago
- 6a43e3a riscv: sifive: fu540: redundant initialization by Heinrich Schuchardt · 4 years, 3 months ago
- ff8e88a riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC level by Bin Meng · 4 years, 3 months ago
- d6a0170 riscv: sifive/fu540: spl: Rename soc_spl_init() by Bin Meng · 4 years, 3 months ago
- ff7d25e env: Enable SPI flash env for SiFive FU540 by Jagan Teki · 4 years, 4 months ago
- 5ce5020 riscv: sifive: fu540: enable all cache ways from U-Boot proper by Pragnesh Patel · 4 years, 5 months ago
- 01cdef2 riscv: sifive: fu540: add SPL configuration by Pragnesh Patel · 4 years, 5 months ago
- 7c45fc9 riscv: cpu: fu540: Add support for cpu fu540 by Pragnesh Patel · 4 years, 5 months ago