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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 6d8565a1ed5acb01bad4a4cd74a93be5f7fb7f7c / cpu / mpc8xxx
  1. 6d8565a ppc/8xxx: Misc DDR related fixes by Kumar Gala · 15 years ago
  2. 21170c8 ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu(). by Poonam Aggrwal · 15 years ago
  3. f8027f6 ppc/85xx/86xx: Device tree fixup for number of cores by Poonam Aggrwal · 15 years ago
  4. 58442dc ppc/85xx,86xx: Handling Unknown SOC version by Poonam Aggrwal · 15 years ago
  5. 3e7b6c1 ppc/8xxx: Refactor code to determine if PCI is enabled & agent/host by Kumar Gala · 15 years ago
  6. 2abbd31 ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · 15 years ago
  7. a713ba9 85xx: Added single core members of FSL P1xx/P2xx processors series by Poonam Aggrwal · 15 years ago
  8. 87c7661 85xx: Added P1020 Processor Support. by Poonam Aggrwal · 15 years ago
  9. 0e87098 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx by Poonam Aggrwal · 15 years ago
  10. 18bacc2 8xxx: Refactored common cpu specific code for 85xx/86xx into one file. by Poonam Aggrwal · 15 years ago
  11. d9c147f 85xx, 86xx: Add common board_add_ram_info() by Peter Tyser · 15 years ago
  12. e66f38d fsl_ddr: Fix DDR3 calculation of rank density with 8GB or more by Timur Tabi · 15 years ago
  13. e7563af fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · 15 years ago
  14. c360cea fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · 16 years ago
  15. 6a81978 fsl-ddr: Fix two bugs in the ddr infrastructure by Dave Liu · 16 years ago
  16. edf0e25 fsl-ddr: Allow system to boot if we have more than 4G of memory by Kumar Gala · 16 years ago
  17. 1542fbd fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller by Kumar Gala · 16 years ago
  18. b4983e1 fsl-ddr: use the 1T timing as default configuration by Dave Liu · 16 years ago
  19. 22cca7e fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · 16 years ago
  20. 22ff3d0 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · 16 years ago
  21. 80ee3ce fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · 16 years ago
  22. 7008d26 fsl ddr skip interleaving if not supported. by Ed Swarthout · 16 years ago
  23. 1f293b4 Add debug information for DDR controller registers by Haiying Wang · 16 years ago
  24. c9ffd83 Check DDR interleaving mode by Haiying Wang · 16 years ago
  25. dfb4910 Pass dimm parameters to populate populate controller options by Haiying Wang · 16 years ago
  26. dbbbb3a Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  27. 6d0f6bc rename CFG_ macros to CONFIG_SYS by Jean-Christophe PLAGNIOL-VILLARD · 16 years ago
  28. f12e454 Coding style cleanup, update CHANGELOG by Wolfgang Denk · 16 years ago
  29. 302e52e Fix compiler warning in mpc8xxx ddr code by Kumar Gala · 16 years ago
  30. 233fdd5 FSL DDR: Add DDR2 DIMM paramter support by Kumar Gala · 16 years ago
  31. 05c05a2 FSL DDR: Add DDR1 DIMM paramter support by Kumar Gala · 16 years ago
  32. 58e5e9a FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago