- c29cc11 clk: sifive: only build sifive-prci.o for CONFIG_CLK_SIFIVE_PRCI by Ben Dooks · 1 year, 5 months ago
- d13cd77 dt-bindings: clock: sifive: sync FU740 PRCI clock binding header by Icenowy Zheng · 2 years, 2 months ago
- 2edb02e clk: sifive: Fix -Wint-to-pointer-cast warning by Bin Meng · 3 years, 1 month ago
- 3517ebc drivers: clk: sifive: fu740-prci: replace 'pciaux' with 'pcieaux' by Green Wan · 3 years, 4 months ago
- d56d79e drivers: clk: add fu740 support by Green Wan · 3 years, 5 months ago
- 65e25be dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET() by Simon Glass · 3 years, 10 months ago
- 41575d8 dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · 3 years, 11 months ago
- 0f0f4e5 clk: sifive: Include device_compat.h by Sean Anderson · 4 years, 1 month ago
- d04a464 sifive: reset: add DM based reset driver for SiFive SoC's by Sagar Shrikant Kadam · 4 years, 3 months ago
- d2e4398 fu540: prci: use common reset indexes defined in binding header by Sagar Shrikant Kadam · 4 years, 3 months ago
- 1ba43d2 clk: sifive: fu540-prci: Release ethernet clock reset by Pragnesh Patel · 4 years, 5 months ago
- 378c709 clk: sifive: fu540-prci: Add ddr clock initialization by Pragnesh Patel · 4 years, 5 months ago
- 79e49b0 clk: sifive: fu540-prci: Add clock enable and disable ops by Pragnesh Patel · 4 years, 5 months ago
- c05ed00 common: Drop linux/delay.h from common header by Simon Glass · 4 years, 5 months ago
- 61b29b8 dm: core: Require users of devres to include the header by Simon Glass · 4 years, 9 months ago
- 8633ede clk: sifive: Drop GEMGXL clock driver by Anup Patel · 5 years ago
- ed0ef37 clk: sifive: Sync-up main driver with upstream Linux by Anup Patel · 5 years ago
- 66591a7 clk: sifive: Sync-up DT bindings header with upstream Linux by Anup Patel · 5 years ago
- c236802 clk: sifive: Sync-up WRPLL library with upstream Linux by Anup Patel · 5 years ago
- d04c79d clk: sifive: Factor-out PLL library as separate module by Anup Patel · 5 years ago
- 49191d2 clk: sifive: Add clock driver for GEMGXL MGMT by Bin Meng · 5 years ago
- db2f696 clk: sifive: fu540-prci: Change include order by Jagan Teki · 5 years ago
- c40b6df clk: Add SiFive FU540 PRCI clock driver by Anup Patel · 6 years ago