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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / a3f5da1bee9a8c343a411080d7d468bdc78794a4 / cpu / mpc8xxx
  1. 3ad95de fsl-ddr: Fix the chip-select interleaving issue by Dave Liu · 15 years ago
  2. d11823c mpc8xxx: improve LAW error messages when setting up DDR by Paul Gortmaker · 15 years ago
  3. 7e4259b ppc/p4080: Add various p4080 related defines (and p4040) by Kumar Gala · 16 years ago
  4. 6d8565a ppc/8xxx: Misc DDR related fixes by Kumar Gala · 15 years ago
  5. 21170c8 ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu(). by Poonam Aggrwal · 15 years ago
  6. f8027f6 ppc/85xx/86xx: Device tree fixup for number of cores by Poonam Aggrwal · 15 years ago
  7. 58442dc ppc/85xx,86xx: Handling Unknown SOC version by Poonam Aggrwal · 15 years ago
  8. 3e7b6c1 ppc/8xxx: Refactor code to determine if PCI is enabled & agent/host by Kumar Gala · 15 years ago
  9. 2abbd31 ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · 15 years ago
  10. a713ba9 85xx: Added single core members of FSL P1xx/P2xx processors series by Poonam Aggrwal · 15 years ago
  11. 87c7661 85xx: Added P1020 Processor Support. by Poonam Aggrwal · 15 years ago
  12. 0e87098 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx by Poonam Aggrwal · 15 years ago
  13. 18bacc2 8xxx: Refactored common cpu specific code for 85xx/86xx into one file. by Poonam Aggrwal · 15 years ago
  14. d9c147f 85xx, 86xx: Add common board_add_ram_info() by Peter Tyser · 15 years ago
  15. e66f38d fsl_ddr: Fix DDR3 calculation of rank density with 8GB or more by Timur Tabi · 15 years ago
  16. e7563af fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · 15 years ago
  17. c360cea fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · 16 years ago
  18. 6a81978 fsl-ddr: Fix two bugs in the ddr infrastructure by Dave Liu · 16 years ago
  19. edf0e25 fsl-ddr: Allow system to boot if we have more than 4G of memory by Kumar Gala · 16 years ago
  20. 1542fbd fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller by Kumar Gala · 16 years ago
  21. b4983e1 fsl-ddr: use the 1T timing as default configuration by Dave Liu · 16 years ago
  22. 22cca7e fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · 16 years ago
  23. 22ff3d0 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · 16 years ago
  24. 80ee3ce fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · 16 years ago
  25. 7008d26 fsl ddr skip interleaving if not supported. by Ed Swarthout · 16 years ago
  26. 1f293b4 Add debug information for DDR controller registers by Haiying Wang · 16 years ago
  27. c9ffd83 Check DDR interleaving mode by Haiying Wang · 16 years ago
  28. dfb4910 Pass dimm parameters to populate populate controller options by Haiying Wang · 16 years ago
  29. dbbbb3a Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  30. 6d0f6bc rename CFG_ macros to CONFIG_SYS by Jean-Christophe PLAGNIOL-VILLARD · 16 years ago
  31. f12e454 Coding style cleanup, update CHANGELOG by Wolfgang Denk · 16 years ago
  32. 302e52e Fix compiler warning in mpc8xxx ddr code by Kumar Gala · 16 years ago
  33. 233fdd5 FSL DDR: Add DDR2 DIMM paramter support by Kumar Gala · 16 years ago
  34. 05c05a2 FSL DDR: Add DDR1 DIMM paramter support by Kumar Gala · 16 years ago
  35. 58e5e9a FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago