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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / a89929bbb372b3eee49282439ce37ddf45fd54d4 / arch / riscv / cpu / start.S
  1. 52923c6 riscv: cache: Implement i/dcache [status, enable, disable] by Rick Chen · 6 years ago
  2. 5d8b2e7 riscv: save hart ID and device tree passed by prior boot stage by Lukas Auer · 6 years ago
  3. 31f9058 riscv: do not blindly modify the mstatus CSR by Lukas Auer · 6 years ago
  4. 8bfa231 riscv: remove unused labels in start.S by Lukas Auer · 6 years ago
  5. c95cafd Drop CONFIG_INIT_CRITICAL by Bin Meng · 6 years ago
  6. 2a23ac6 riscv: align mtvec on a 4-byte boundary by Lukas Auer · 6 years ago
  7. c55309c riscv: fix inconsistent use of spaces and tabs in start.S by Lukas Auer · 6 years ago
  8. b5369c5 riscv: Make start.S available for all targets by Bin Meng · 6 years ago[Renamed from arch/riscv/cpu/ax25/start.S]
  9. 6f4dd62 riscv: cpu: nx25: Rename as ax25 by Rick Chen · 6 years ago[Renamed from arch/riscv/cpu/nx25/start.S]
  10. 83d290c SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · 6 years ago
  11. d58717e riscv: ae250: Support DT provided by the board at runtime by Rick Chen · 6 years ago
  12. e8e3959 riscv: cpu: Add nx25 to support RISC-V by Rick Chen · 7 years ago