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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +09002/*
3 * board/renesas/lager/lager.c
4 * This file is lager board support.
5 *
6 * Copyright (C) 2013 Renesas Electronics Corporation
7 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +09008 */
9
10#include <common.h>
Simon Glass9a3b4ce2019-12-28 10:45:01 -070011#include <cpu_func.h>
Simon Glass7b51b572019-08-01 09:46:52 -060012#include <env.h>
Simon Glassf3998fd2019-08-02 09:44:25 -060013#include <env_internal.h>
Simon Glassdb41d652019-12-28 10:45:07 -070014#include <hang.h>
Simon Glass691d7192020-05-10 11:40:02 -060015#include <init.h>
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090016#include <malloc.h>
17#include <netdev.h>
Nobuhiro Iwamatsucf839572014-12-09 16:20:04 +090018#include <dm.h>
Simon Glass401d1c42020-10-30 21:38:53 -060019#include <asm/global_data.h>
Nobuhiro Iwamatsucf839572014-12-09 16:20:04 +090020#include <dm/platform_data/serial_sh.h>
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090021#include <asm/processor.h>
22#include <asm/mach-types.h>
23#include <asm/io.h>
Simon Glasscd93d622020-05-10 11:40:13 -060024#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060025#include <linux/delay.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090026#include <linux/errno.h>
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090027#include <asm/arch/sys_proto.h>
28#include <asm/gpio.h>
29#include <asm/arch/rmobile.h>
Nobuhiro Iwamatsu44e1eeb2014-12-02 16:52:19 +090030#include <asm/arch/rcar-mstp.h>
Nobuhiro Iwamatsud7916b12014-12-03 15:30:30 +090031#include <asm/arch/mmc.h>
Nobuhiro Iwamatsuacdfecb2014-11-21 10:19:32 +090032#include <asm/arch/sh_sdhi.h>
Nobuhiro Iwamatsu23565c62013-10-20 20:28:24 +090033#include <miiphy.h>
Nobuhiro Iwamatsub9986be2013-10-10 09:13:41 +090034#include <i2c.h>
Nobuhiro Iwamatsud7916b12014-12-03 15:30:30 +090035#include <mmc.h>
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090036#include "qos.h"
37
38DECLARE_GLOBAL_DATA_PTR;
39
Nobuhiro Iwamatsu2c2c6ba2014-03-31 14:14:25 +090040#define CLK2MHZ(clk) (clk / 1000 / 1000)
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090041void s_init(void)
42{
Nobuhiro Iwamatsudc535e12014-03-27 16:18:19 +090043 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
44 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090045
46 /* Watchdog init */
47 writel(0xA5A5A500, &rwdt->rwtcsra);
48 writel(0xA5A5A500, &swdt->swtcsra);
49
Nobuhiro Iwamatsu2c2c6ba2014-03-31 14:14:25 +090050 /* CPU frequency setting. Set to 1.4GHz */
Nobuhiro Iwamatsuf212a8a2014-07-30 12:28:00 +090051 if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
Nobuhiro Iwamatsud8659c62014-10-31 16:08:11 +090052 u32 stat = 0;
Nobuhiro Iwamatsuf212a8a2014-07-30 12:28:00 +090053 u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
54 << PLL0_STC_BIT;
55 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
Nobuhiro Iwamatsud8659c62014-10-31 16:08:11 +090056
57 do {
58 stat = readl(PLLECR) & PLL0ST;
59 } while (stat == 0x0);
Nobuhiro Iwamatsuf212a8a2014-07-30 12:28:00 +090060 }
Nobuhiro Iwamatsu2c2c6ba2014-03-31 14:14:25 +090061
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090062 /* QoS(Quality-of-Service) Init */
63 qos_init();
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090064}
65
Marek Vasute6027e62018-04-23 20:24:06 +020066#define TMU0_MSTP125 BIT(25)
Nobuhiro Iwamatsu23565c62013-10-20 20:28:24 +090067
Marek Vasute6027e62018-04-23 20:24:06 +020068#define SD1CKCR 0xE6150078
69#define SD2CKCR 0xE615026C
70#define SD_97500KHZ 0x7
Nobuhiro Iwamatsuacdfecb2014-11-21 10:19:32 +090071
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090072int board_early_init_f(void)
73{
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090074 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
Nobuhiro Iwamatsuacdfecb2014-11-21 10:19:32 +090075
76 /*
77 * SD0 clock is set to 97.5MHz by default.
Marek Vasute6027e62018-04-23 20:24:06 +020078 * Set SD1 and SD2 to the 97.5MHz as well.
Nobuhiro Iwamatsuacdfecb2014-11-21 10:19:32 +090079 */
Marek Vasute6027e62018-04-23 20:24:06 +020080 writel(SD_97500KHZ, SD1CKCR);
81 writel(SD_97500KHZ, SD2CKCR);
Nobuhiro Iwamatsu23565c62013-10-20 20:28:24 +090082
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090083 return 0;
84}
85
Marek Vasute6027e62018-04-23 20:24:06 +020086#define ETHERNET_PHY_RESET 185 /* GPIO 5 31 */
87
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090088int board_init(void)
89{
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090090 /* adress of boot parameters */
Nobuhiro Iwamatsueeb266a2014-11-10 13:58:50 +090091 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +090092
Marek Vasute6027e62018-04-23 20:24:06 +020093 /* Force ethernet PHY out of reset */
94 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
95 gpio_direction_output(ETHERNET_PHY_RESET, 0);
96 mdelay(10);
97 gpio_direction_output(ETHERNET_PHY_RESET, 1);
Nobuhiro Iwamatsu23565c62013-10-20 20:28:24 +090098
99 return 0;
100}
101
Marek Vasute6027e62018-04-23 20:24:06 +0200102int dram_init(void)
Nobuhiro Iwamatsu23565c62013-10-20 20:28:24 +0900103{
Siva Durga Prasad Paladugu12308b12018-07-16 15:56:11 +0530104 if (fdtdec_setup_mem_size_base() != 0)
Marek Vasute6027e62018-04-23 20:24:06 +0200105 return -EINVAL;
Nobuhiro Iwamatsu23565c62013-10-20 20:28:24 +0900106
Marek Vasute6027e62018-04-23 20:24:06 +0200107 return 0;
Nobuhiro Iwamatsu23565c62013-10-20 20:28:24 +0900108}
109
Marek Vasute6027e62018-04-23 20:24:06 +0200110int dram_init_banksize(void)
111{
112 fdtdec_setup_memory_banksize();
113
114 return 0;
115}
116
117/* KSZ8041NL/RNL */
118#define PHY_CONTROL1 0x1E
Marek Vasut4bbd4642019-03-30 07:05:09 +0100119#define PHY_LED_MODE 0xC000
Nobuhiro Iwamatsu23565c62013-10-20 20:28:24 +0900120#define PHY_LED_MODE_ACK 0x4000
121int board_phy_config(struct phy_device *phydev)
122{
123 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
124 ret &= ~PHY_LED_MODE;
125 ret |= PHY_LED_MODE_ACK;
126 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
127
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +0900128 return 0;
129}
130
Harald Seiler35b65dd2020-12-15 16:47:52 +0100131void reset_cpu(void)
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +0900132{
Marek Vasute6027e62018-04-23 20:24:06 +0200133 struct udevice *dev;
134 const u8 pmic_bus = 2;
135 const u8 pmic_addr = 0x58;
136 u8 data;
137 int ret;
Nobuhiro Iwamatsub9986be2013-10-10 09:13:41 +0900138
Marek Vasute6027e62018-04-23 20:24:06 +0200139 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
140 if (ret)
141 hang();
142
143 ret = dm_i2c_read(dev, 0x13, &data, 1);
144 if (ret)
145 hang();
146
147 data |= BIT(1);
148
149 ret = dm_i2c_write(dev, 0x13, &data, 1);
150 if (ret)
151 hang();
Nobuhiro Iwamatsuf4ec4522013-11-21 17:06:46 +0900152}
Nobuhiro Iwamatsucf839572014-12-09 16:20:04 +0900153
Marek Vasute6027e62018-04-23 20:24:06 +0200154enum env_location env_get_location(enum env_operation op, int prio)
155{
156 const u32 load_magic = 0xb33fc0de;
Nobuhiro Iwamatsucf839572014-12-09 16:20:04 +0900157
Marek Vasute6027e62018-04-23 20:24:06 +0200158 /* Block environment access if loaded using JTAG */
159 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
160 (op != ENVOP_INIT))
161 return ENVL_UNKNOWN;
162
163 if (prio)
164 return ENVL_UNKNOWN;
165
166 return ENVL_SPI_FLASH;
167}