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Jon Loeliger5c9efb32006-04-27 10:15:16 -05001/*
Kumar Gala1b77ca82011-01-04 17:45:13 -06002 * Copyright 2006, 2010-2011 Freescale Semiconductor.
Jon Loeliger5c9efb32006-04-27 10:15:16 -05003 *
Jon Loeligerdebb7352006-04-26 17:58:56 -05004 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
Jon Loeliger5c9efb32006-04-27 10:15:16 -050026 * MPC8641HPCN board configuration file
Jon Loeligerdebb7352006-04-26 17:58:56 -050027 *
28 * Make sure you change the MAC address and other network params first,
29 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
30 */
31
32#ifndef __CONFIG_H
33#define __CONFIG_H
34
35/* High Level Configuration Options */
36#define CONFIG_MPC86xx 1 /* MPC86xx */
37#define CONFIG_MPC8641 1 /* MPC8641 specific */
38#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
Kumar Gala7649a592009-03-31 23:02:38 -050039#define CONFIG_MP 1 /* support multiple processors */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020040#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
Becky Bruce3111d322008-11-06 17:37:35 -060041/*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */
Becky Bruced591a802009-02-03 18:10:54 -060042#define CONFIG_ADDR_MAP 1 /* Use addr map */
Jon Loeligerdebb7352006-04-26 17:58:56 -050043
Wolfgang Denk2ae18242010-10-06 09:05:45 +020044/*
45 * default CCSRBAR is at 0xff700000
46 * assume U-Boot is less than 0.5MB
47 */
48#define CONFIG_SYS_TEXT_BASE 0xeff00000
49
Jon Loeligerdebb7352006-04-26 17:58:56 -050050#ifdef RUN_DIAG
Becky Bruce6bf98b12008-11-05 14:55:33 -060051#define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
Jon Loeligerdebb7352006-04-26 17:58:56 -050052#endif
Jon Loeliger5c9efb32006-04-27 10:15:16 -050053
Becky Bruceaf5d1002008-10-31 17:14:14 -050054/*
Becky Bruce1266df82008-11-03 15:44:01 -060055 * virtual address to be used for temporary mappings. There
56 * should be 128k free at this VA.
57 */
58#define CONFIG_SYS_SCRATCH_VA 0xe0000000
59
Kumar Gala1b77ca82011-01-04 17:45:13 -060060#define CONFIG_SYS_SRIO
61#define CONFIG_SRIO1 /* SRIO port 1 */
Becky Bruceaf5d1002008-10-31 17:14:14 -050062
Ed Swarthout63cec582007-08-02 14:09:49 -050063#define CONFIG_PCI 1 /* Enable PCI/PCIE */
Kumar Gala46f3e382010-07-09 00:02:34 -050064#define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */
65#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */
Ed Swarthout63cec582007-08-02 14:09:49 -050066#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Kumar Gala8ba93f62008-10-21 18:06:15 -050067#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Becky Bruce4933b912008-01-23 16:31:01 -060068#define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
Jon Loeliger5c9efb32006-04-27 10:15:16 -050069
Wolfgang Denk53677ef2008-05-20 16:00:29 +020070#define CONFIG_TSEC_ENET /* tsec ethernet support */
Jon Loeligerdebb7352006-04-26 17:58:56 -050071#define CONFIG_ENV_OVERWRITE
Jon Loeliger5c9efb32006-04-27 10:15:16 -050072
Peter Tyser4bbfd3e2010-10-07 22:32:48 -050073#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
Becky Bruce31d82672008-05-08 19:02:12 -050074#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
Becky Bruced591a802009-02-03 18:10:54 -060075#define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */
Jon Loeligerdebb7352006-04-26 17:58:56 -050076
Wolfgang Denk53677ef2008-05-20 16:00:29 +020077#define CONFIG_ALTIVEC 1
Jon Loeligerdebb7352006-04-26 17:58:56 -050078
Jon Loeliger5c9efb32006-04-27 10:15:16 -050079/*
Jon Loeligerdebb7352006-04-26 17:58:56 -050080 * L2CR setup -- make sure this is right for your board!
81 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_L2
Jon Loeligerdebb7352006-04-26 17:58:56 -050083#define L2_INIT 0
84#define L2_ENABLE (L2CR_L2E)
85
86#ifndef CONFIG_SYS_CLK_FREQ
Ed Swarthout63cec582007-08-02 14:09:49 -050087#ifndef __ASSEMBLY__
88extern unsigned long get_board_sys_clk(unsigned long dummy);
89#endif
Wolfgang Denk53677ef2008-05-20 16:00:29 +020090#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
Jon Loeligerdebb7352006-04-26 17:58:56 -050091#endif
92
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
94#define CONFIG_SYS_MEMTEST_END 0x00400000
Jon Loeligerdebb7352006-04-26 17:58:56 -050095
Jon Loeligerdebb7352006-04-26 17:58:56 -050096/*
Becky Bruce3111d322008-11-06 17:37:35 -060097 * With the exception of PCI Memory and Rapid IO, most devices will simply
98 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
99 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
100 */
101#ifdef CONFIG_PHYS_64BIT
Becky Bruce1605cc92011-10-03 19:10:51 -0500102#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
Becky Bruce3111d322008-11-06 17:37:35 -0600103#else
Becky Bruce1605cc92011-10-03 19:10:51 -0500104#define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
Becky Bruce3111d322008-11-06 17:37:35 -0600105#endif
106
107/*
Jon Loeligerdebb7352006-04-26 17:58:56 -0500108 * Base addresses -- Note these are effective addresses where the
109 * actual resources get mapped (not physical addresses)
110 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
Becky Brucec759a012008-11-06 17:36:04 -0600112#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500114
Becky Bruce3111d322008-11-06 17:37:35 -0600115/* Physical addresses */
116#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Becky Bruce1605cc92011-10-03 19:10:51 -0500117#define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH
118#define CONFIG_SYS_CCSRBAR_PHYS \
119 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
120 CONFIG_SYS_CCSRBAR_PHYS_HIGH)
Becky Bruce3111d322008-11-06 17:37:35 -0600121
york076bff82010-07-02 22:25:52 +0000122#define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
123
Jon Loeligerdebb7352006-04-26 17:58:56 -0500124/*
125 * DDR Setup
126 */
Kumar Gala6a8e5692008-08-26 15:01:35 -0500127#define CONFIG_FSL_DDR2
128#undef CONFIG_FSL_DDR_INTERACTIVE
129#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
130#define CONFIG_DDR_SPD
131
132#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
133#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
136#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Becky Bruce1266df82008-11-03 15:44:01 -0600137#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
Jin Zhengxiongfcb28e72006-07-13 10:35:10 -0500138#define CONFIG_VERY_BIG_RAM
Jon Loeligerdebb7352006-04-26 17:58:56 -0500139
Kumar Gala6a8e5692008-08-26 15:01:35 -0500140#define CONFIG_NUM_DDR_CONTROLLERS 2
141#define CONFIG_DIMM_SLOTS_PER_CTLR 2
142#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500143
Kumar Gala6a8e5692008-08-26 15:01:35 -0500144/*
145 * I2C addresses of SPD EEPROMs
146 */
147#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
148#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */
149#define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
150#define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500151
Jon Loeligerdebb7352006-04-26 17:58:56 -0500152
Kumar Gala6a8e5692008-08-26 15:01:35 -0500153/*
154 * These are used when DDR doesn't use SPD.
155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
157#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
158#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
159#define CONFIG_SYS_DDR_TIMING_3 0x00000000
160#define CONFIG_SYS_DDR_TIMING_0 0x00260802
161#define CONFIG_SYS_DDR_TIMING_1 0x39357322
162#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
163#define CONFIG_SYS_DDR_MODE_1 0x00480432
164#define CONFIG_SYS_DDR_MODE_2 0x00000000
165#define CONFIG_SYS_DDR_INTERVAL 0x06090100
166#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
167#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
168#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
169#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
170#define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
171#define CONFIG_SYS_DDR_CONTROL2 0x04400000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500172
Jon Loeligerad8f8682008-01-15 13:42:41 -0600173#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_I2C_EEPROM_NXID
Jean-Christophe PLAGNIOL-VILLARD32628c52008-08-30 23:54:58 +0200175#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
177#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
Jon Loeligerdebb7352006-04-26 17:58:56 -0500178
Becky Brucec759a012008-11-06 17:36:04 -0600179#define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
Becky Bruce1605cc92011-10-03 19:10:51 -0500180#define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE
181#define CONFIG_SYS_FLASH_BASE_PHYS \
182 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
183 CONFIG_SYS_PHYS_ADDR_HIGH)
Becky Bruce3111d322008-11-06 17:37:35 -0600184
Becky Bruceb81b7732009-02-02 16:34:52 -0600185#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
Jon Loeligerdebb7352006-04-26 17:58:56 -0500186
Becky Bruce3111d322008-11-06 17:37:35 -0600187#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
188 | 0x00001001) /* port size 16bit */
189#define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
Jon Loeligerdebb7352006-04-26 17:58:56 -0500190
Becky Bruce3111d322008-11-06 17:37:35 -0600191#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
192 | 0x00001001) /* port size 16bit */
193#define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500194
Becky Bruce3111d322008-11-06 17:37:35 -0600195#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
196 | 0x00000801) /* port size 8bit */
197#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
Jon Loeligerdebb7352006-04-26 17:58:56 -0500198
Becky Brucec759a012008-11-06 17:36:04 -0600199/*
200 * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
201 * The PIXIS and CF by themselves aren't large enough to take up the 128k
202 * required for the smallest BAT mapping, so there's a 64k hole.
203 */
204#define CONFIG_SYS_LBC_BASE 0xffde0000
Becky Bruce1605cc92011-10-03 19:10:51 -0500205#define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE
Jon Loeligerdebb7352006-04-26 17:58:56 -0500206
Kim Phillips7608d752007-08-21 17:00:17 -0500207#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
Becky Brucec759a012008-11-06 17:36:04 -0600208#define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
Becky Bruce1605cc92011-10-03 19:10:51 -0500209#define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
210#define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
211 CONFIG_SYS_PHYS_ADDR_HIGH)
Becky Brucec759a012008-11-06 17:36:04 -0600212#define PIXIS_SIZE 0x00008000 /* 32k */
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500213#define PIXIS_ID 0x0 /* Board ID at offset 0 */
214#define PIXIS_VER 0x1 /* Board version at offset 1 */
215#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
216#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
217#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
218#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
219#define PIXIS_VCTL 0x10 /* VELA Control Register */
220#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
221#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
222#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala9af9c6b2009-07-15 13:45:00 -0500223#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
224#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500225#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
226#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
227#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
228#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
Jon Loeligerdebb7352006-04-26 17:58:56 -0500230
Becky Bruceb5431562008-10-31 17:13:49 -0500231/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
Becky Brucec759a012008-11-06 17:36:04 -0600232#define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
Becky Bruce3111d322008-11-06 17:37:35 -0600233#define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
Becky Bruceb5431562008-10-31 17:13:49 -0500234
Becky Bruce170deac2008-11-05 14:55:32 -0600235#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#undef CONFIG_SYS_FLASH_CHECKSUM
239#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
240#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200241#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Becky Brucebf9a8c32008-11-05 14:55:35 -0600242#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500243
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200244#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_FLASH_CFI
246#define CONFIG_SYS_FLASH_EMPTY_INFO
Jon Loeligerdebb7352006-04-26 17:58:56 -0500247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
249#define CONFIG_SYS_RAMBOOT
Jon Loeligerdebb7352006-04-26 17:58:56 -0500250#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#undef CONFIG_SYS_RAMBOOT
Jon Loeligerdebb7352006-04-26 17:58:56 -0500252#endif
253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#if defined(CONFIG_SYS_RAMBOOT)
Jin Zhengxiong-R64188fa7db9c2006-06-27 18:11:54 +0800255#undef CONFIG_SPD_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_SDRAM_SIZE 256
Jon Loeligerdebb7352006-04-26 17:58:56 -0500257#endif
258
259#undef CONFIG_CLOCKS_IN_MHZ
260
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_INIT_RAM_LOCK 1
262#ifndef CONFIG_SYS_INIT_RAM_LOCK
263#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500264#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500266#endif
Wolfgang Denk553f0982010-10-26 13:32:32 +0200267#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500268
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200269#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Jon Loeligerdebb7352006-04-26 17:58:56 -0500271
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
273#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500274
275/* Serial Port */
276#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_NS16550
278#define CONFIG_SYS_NS16550_SERIAL
279#define CONFIG_SYS_NS16550_REG_SIZE 1
280#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500281
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_BAUDRATE_TABLE \
Jon Loeligerdebb7352006-04-26 17:58:56 -0500283 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
284
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
286#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500287
288/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_HUSH_PARSER
Jon Loeligerdebb7352006-04-26 17:58:56 -0500290
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500291/*
292 * Pass open firmware flat tree to kernel
293 */
Jon Loeligerea9f7392007-11-28 14:47:18 -0600294#define CONFIG_OF_LIBFDT 1
295#define CONFIG_OF_BOARD_SETUP 1
296#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Jon Loeligerdebb7352006-04-26 17:58:56 -0500297
Jon Loeliger586d1d52006-05-19 13:22:44 -0500298/*
299 * I2C
300 */
Jon Loeliger20476722006-10-20 15:50:15 -0500301#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
302#define CONFIG_HARD_I2C /* I2C with hardware support*/
Jon Loeligerdebb7352006-04-26 17:58:56 -0500303#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
305#define CONFIG_SYS_I2C_SLAVE 0x7F
306#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
307#define CONFIG_SYS_I2C_OFFSET 0x3100
Jon Loeligerdebb7352006-04-26 17:58:56 -0500308
Jon Loeliger586d1d52006-05-19 13:22:44 -0500309/*
310 * RapidIO MMU
311 */
Kumar Gala1b77ca82011-01-04 17:45:13 -0600312#define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */
Becky Bruce3111d322008-11-06 17:37:35 -0600313#ifdef CONFIG_PHYS_64BIT
Becky Bruce1605cc92011-10-03 19:10:51 -0500314#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000
315#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c
Becky Bruce3111d322008-11-06 17:37:35 -0600316#else
Becky Bruce1605cc92011-10-03 19:10:51 -0500317#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE
318#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000
Becky Bruce3111d322008-11-06 17:37:35 -0600319#endif
Becky Bruce1605cc92011-10-03 19:10:51 -0500320#define CONFIG_SYS_SRIO1_MEM_PHYS \
321 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
322 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
Kumar Gala1b77ca82011-01-04 17:45:13 -0600323#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500324
325/*
326 * General PCI
327 * Addresses are mapped 1-1.
328 */
Becky Bruce49f46f32009-02-03 18:10:53 -0600329
Kumar Gala64e55d52010-12-17 10:47:36 -0600330#define CONFIG_SYS_PCIE1_NAME "ULI"
Kumar Gala46f3e382010-07-09 00:02:34 -0500331#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
Becky Bruce3111d322008-11-06 17:37:35 -0600332#ifdef CONFIG_PHYS_64BIT
Kumar Gala46f3e382010-07-09 00:02:34 -0500333#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
Becky Bruce1605cc92011-10-03 19:10:51 -0500334#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000
335#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c
Becky Bruce3111d322008-11-06 17:37:35 -0600336#else
Kumar Gala46f3e382010-07-09 00:02:34 -0500337#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
Becky Bruce1605cc92011-10-03 19:10:51 -0500338#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT
339#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000
Becky Bruce3111d322008-11-06 17:37:35 -0600340#endif
Becky Bruce1605cc92011-10-03 19:10:51 -0500341#define CONFIG_SYS_PCIE1_MEM_PHYS \
342 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
343 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
Kumar Gala46f3e382010-07-09 00:02:34 -0500344#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
345#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
346#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
Becky Bruce1605cc92011-10-03 19:10:51 -0500347#define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT
348#define CONFIG_SYS_PCIE1_IO_PHYS \
349 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
350 CONFIG_SYS_PHYS_ADDR_HIGH)
Kumar Gala46f3e382010-07-09 00:02:34 -0500351#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500352
Becky Bruce4c78d4a2009-02-03 18:10:56 -0600353#ifdef CONFIG_PHYS_64BIT
354/*
Kumar Gala46f3e382010-07-09 00:02:34 -0500355 * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
Becky Bruce4c78d4a2009-02-03 18:10:56 -0600356 * This will increase the amount of PCI address space available for
357 * for mapping RAM.
358 */
Kumar Gala46f3e382010-07-09 00:02:34 -0500359#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS
Becky Bruce4c78d4a2009-02-03 18:10:56 -0600360#else
Kumar Gala46f3e382010-07-09 00:02:34 -0500361#define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \
362 + CONFIG_SYS_PCIE1_MEM_SIZE)
Becky Bruce4c78d4a2009-02-03 18:10:56 -0600363#endif
Kumar Gala46f3e382010-07-09 00:02:34 -0500364#define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \
365 + CONFIG_SYS_PCIE1_MEM_SIZE)
Becky Bruce1605cc92011-10-03 19:10:51 -0500366#define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
367 + CONFIG_SYS_PCIE1_MEM_SIZE)
368#define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
Kumar Gala46f3e382010-07-09 00:02:34 -0500369#define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \
370 + CONFIG_SYS_PCIE1_MEM_SIZE)
371#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
372#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
373#define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \
374 + CONFIG_SYS_PCIE1_IO_SIZE)
Becky Bruce1605cc92011-10-03 19:10:51 -0500375#define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
376 + CONFIG_SYS_PCIE1_IO_SIZE)
Kumar Gala46f3e382010-07-09 00:02:34 -0500377#define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \
378 + CONFIG_SYS_PCIE1_IO_SIZE)
379#define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE
Jon Loeligerdebb7352006-04-26 17:58:56 -0500380
Jon Loeligerdebb7352006-04-26 17:58:56 -0500381#if defined(CONFIG_PCI)
382
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200383#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500384
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
Jon Loeligerdebb7352006-04-26 17:58:56 -0500386
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200387#define CONFIG_PCI_PNP /* do pci plug-and-play */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500388
389#define CONFIG_RTL8139
390
Jon Loeligerdebb7352006-04-26 17:58:56 -0500391#undef CONFIG_EEPRO100
392#undef CONFIG_TULIP
393
Zhang Weia81d1c02007-06-06 10:08:14 +0200394/************************************************************
395 * USB support
396 ************************************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200397#define CONFIG_PCI_OHCI 1
Zhang Weia81d1c02007-06-06 10:08:14 +0200398#define CONFIG_USB_OHCI_NEW 1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200399#define CONFIG_USB_KEYBOARD 1
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +0200400#define CONFIG_SYS_STDIO_DEREGISTER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_USB_EVENT_POLL 1
402#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
403#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
404#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
Zhang Weia81d1c02007-06-06 10:08:14 +0200405
Jason Jin0f460a12007-07-13 12:14:58 +0800406/*PCIE video card used*/
Kumar Gala46f3e382010-07-09 00:02:34 -0500407#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
Jason Jin0f460a12007-07-13 12:14:58 +0800408
409/*PCI video card used*/
Kumar Gala46f3e382010-07-09 00:02:34 -0500410/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/
Jason Jin0f460a12007-07-13 12:14:58 +0800411
412/* video */
413#define CONFIG_VIDEO
414
415#if defined(CONFIG_VIDEO)
416#define CONFIG_BIOSEMU
417#define CONFIG_CFB_CONSOLE
418#define CONFIG_VIDEO_SW_CURSOR
419#define CONFIG_VGA_AS_SINGLE_DEVICE
420#define CONFIG_ATI_RADEON_FB
421#define CONFIG_VIDEO_LOGO
422/*#define CONFIG_CONSOLE_CURSOR*/
Kumar Gala46f3e382010-07-09 00:02:34 -0500423#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
Jason Jin0f460a12007-07-13 12:14:58 +0800424#endif
425
Jon Loeligerdebb7352006-04-26 17:58:56 -0500426#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500427
Jin Zhengxiongdabf9ef2006-08-23 19:15:12 +0800428#define CONFIG_DOS_PARTITION
429#define CONFIG_SCSI_AHCI
430
431#ifdef CONFIG_SCSI_AHCI
432#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
434#define CONFIG_SYS_SCSI_MAX_LUN 1
435#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
436#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Jin Zhengxiongdabf9ef2006-08-23 19:15:12 +0800437#endif
438
Jon Loeligerdebb7352006-04-26 17:58:56 -0500439#endif /* CONFIG_PCI */
440
Jon Loeligerdebb7352006-04-26 17:58:56 -0500441#if defined(CONFIG_TSEC_ENET)
442
Jon Loeligerdebb7352006-04-26 17:58:56 -0500443#define CONFIG_MII 1 /* MII PHY management */
444
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200445#define CONFIG_TSEC1 1
446#define CONFIG_TSEC1_NAME "eTSEC1"
447#define CONFIG_TSEC2 1
448#define CONFIG_TSEC2_NAME "eTSEC2"
449#define CONFIG_TSEC3 1
450#define CONFIG_TSEC3_NAME "eTSEC3"
451#define CONFIG_TSEC4 1
452#define CONFIG_TSEC4_NAME "eTSEC4"
Jon Loeligerdebb7352006-04-26 17:58:56 -0500453
Jon Loeligerdebb7352006-04-26 17:58:56 -0500454#define TSEC1_PHY_ADDR 0
455#define TSEC2_PHY_ADDR 1
456#define TSEC3_PHY_ADDR 2
457#define TSEC4_PHY_ADDR 3
458#define TSEC1_PHYIDX 0
459#define TSEC2_PHYIDX 0
460#define TSEC3_PHYIDX 0
461#define TSEC4_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500462#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
463#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
464#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
465#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500466
467#define CONFIG_ETHPRIME "eTSEC1"
468
469#endif /* CONFIG_TSEC_ENET */
470
Becky Bruce1605cc92011-10-03 19:10:51 -0500471
Becky Bruce3111d322008-11-06 17:37:35 -0600472#ifdef CONFIG_PHYS_64BIT
Becky Bruce3111d322008-11-06 17:37:35 -0600473#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
474#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
475
Becky Bruce1605cc92011-10-03 19:10:51 -0500476/* Put physical address into the BAT format */
477#define BAT_PHYS_ADDR(low, high) \
478 (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
479/* Convert high/low pairs to actual 64-bit value */
480#define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
481#else
482/* 32-bit systems just ignore the "high" bits */
483#define BAT_PHYS_ADDR(low, high) (low)
484#define PAIRED_PHYS_TO_PHYS(low, high) (low)
485#endif
486
Jon Loeliger586d1d52006-05-19 13:22:44 -0500487/*
Becky Brucec759a012008-11-06 17:36:04 -0600488 * BAT0 DDR
Jon Loeligerdebb7352006-04-26 17:58:56 -0500489 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200490#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
Timur Tabi9ff32d82010-03-29 12:51:07 -0500491#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500492
Jon Loeliger586d1d52006-05-19 13:22:44 -0500493/*
Becky Brucec759a012008-11-06 17:36:04 -0600494 * BAT1 LBC (PIXIS/CF)
Becky Bruceaf5d1002008-10-31 17:14:14 -0500495 */
Becky Bruce1605cc92011-10-03 19:10:51 -0500496#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
497 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600498 | BATL_PP_RW | BATL_CACHEINHIBIT | \
499 BATL_GUARDEDSTORAGE)
Becky Brucec759a012008-11-06 17:36:04 -0600500#define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
501 | BATU_VS | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500502#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
503 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600504 | BATL_PP_RW | BATL_MEMCOHERENCE)
Becky Brucec759a012008-11-06 17:36:04 -0600505#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
Becky Bruceaf5d1002008-10-31 17:14:14 -0500506
507/* if CONFIG_PCI:
Kumar Gala46f3e382010-07-09 00:02:34 -0500508 * BAT2 PCIE1 and PCIE1 MEM
Becky Bruceaf5d1002008-10-31 17:14:14 -0500509 * if CONFIG_RIO
Becky Brucec759a012008-11-06 17:36:04 -0600510 * BAT2 Rapidio Memory
Jon Loeligerdebb7352006-04-26 17:58:56 -0500511 */
Becky Bruceaf5d1002008-10-31 17:14:14 -0500512#ifdef CONFIG_PCI
Becky Bruce1605cc92011-10-03 19:10:51 -0500513#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
514 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600515 | BATL_PP_RW | BATL_CACHEINHIBIT \
516 | BATL_GUARDEDSTORAGE)
Kumar Gala46f3e382010-07-09 00:02:34 -0500517#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
Becky Bruceaf5d1002008-10-31 17:14:14 -0500518 | BATU_VS | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500519#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
520 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600521 | BATL_PP_RW | BATL_CACHEINHIBIT)
Becky Bruceaf5d1002008-10-31 17:14:14 -0500522#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
523#else /* CONFIG_RIO */
Becky Bruce1605cc92011-10-03 19:10:51 -0500524#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
525 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600526 | BATL_PP_RW | BATL_CACHEINHIBIT | \
527 BATL_GUARDEDSTORAGE)
Kumar Gala1b77ca82011-01-04 17:45:13 -0600528#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
Becky Bruce3111d322008-11-06 17:37:35 -0600529 | BATU_VS | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500530#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
531 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600532 | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200533#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
Becky Bruceaf5d1002008-10-31 17:14:14 -0500534#endif
Jon Loeligerdebb7352006-04-26 17:58:56 -0500535
Jon Loeliger586d1d52006-05-19 13:22:44 -0500536/*
Becky Brucec759a012008-11-06 17:36:04 -0600537 * BAT3 CCSR Space
Jon Loeligerdebb7352006-04-26 17:58:56 -0500538 */
Becky Bruce1605cc92011-10-03 19:10:51 -0500539#define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
540 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600541 | BATL_PP_RW | BATL_CACHEINHIBIT \
542 | BATL_GUARDEDSTORAGE)
Becky Brucec759a012008-11-06 17:36:04 -0600543#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
544 | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500545#define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
546 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600547 | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200548#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
Jon Loeligerdebb7352006-04-26 17:58:56 -0500549
Becky Bruce3111d322008-11-06 17:37:35 -0600550#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
551#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
552 | BATL_PP_RW | BATL_CACHEINHIBIT \
553 | BATL_GUARDEDSTORAGE)
554#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
555 | BATU_BL_1M | BATU_VS | BATU_VP)
556#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
557 | BATL_PP_RW | BATL_CACHEINHIBIT)
558#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
559#endif
560
Jon Loeliger586d1d52006-05-19 13:22:44 -0500561/*
Kumar Gala46f3e382010-07-09 00:02:34 -0500562 * BAT4 PCIE1_IO and PCIE2_IO
Jon Loeligerdebb7352006-04-26 17:58:56 -0500563 */
Becky Bruce1605cc92011-10-03 19:10:51 -0500564#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
565 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600566 | BATL_PP_RW | BATL_CACHEINHIBIT \
567 | BATL_GUARDEDSTORAGE)
Kumar Gala46f3e382010-07-09 00:02:34 -0500568#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
Becky Brucec759a012008-11-06 17:36:04 -0600569 | BATU_VS | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500570#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
571 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600572 | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200573#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
Jon Loeligerdebb7352006-04-26 17:58:56 -0500574
Jon Loeliger586d1d52006-05-19 13:22:44 -0500575/*
Becky Brucec759a012008-11-06 17:36:04 -0600576 * BAT5 Init RAM for stack in the CPU DCache (no backing memory)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500577 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200578#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
579#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
580#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
581#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
Jon Loeligerdebb7352006-04-26 17:58:56 -0500582
Jon Loeliger586d1d52006-05-19 13:22:44 -0500583/*
Becky Brucec759a012008-11-06 17:36:04 -0600584 * BAT6 FLASH
Jon Loeligerdebb7352006-04-26 17:58:56 -0500585 */
Becky Bruce1605cc92011-10-03 19:10:51 -0500586#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
587 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600588 | BATL_PP_RW | BATL_CACHEINHIBIT \
589 | BATL_GUARDEDSTORAGE)
Becky Bruce170deac2008-11-05 14:55:32 -0600590#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
591 | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500592#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
593 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600594 | BATL_PP_RW | BATL_MEMCOHERENCE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200595#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
Jon Loeligerdebb7352006-04-26 17:58:56 -0500596
Becky Brucebf9a8c32008-11-05 14:55:35 -0600597/* Map the last 1M of flash where we're running from reset */
598#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
599 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200600#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
Becky Brucebf9a8c32008-11-05 14:55:35 -0600601#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
602 | BATL_MEMCOHERENCE)
603#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
604
Becky Brucec759a012008-11-06 17:36:04 -0600605/*
606 * BAT7 FREE - used later for tmp mappings
607 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200608#define CONFIG_SYS_DBAT7L 0x00000000
609#define CONFIG_SYS_DBAT7U 0x00000000
610#define CONFIG_SYS_IBAT7L 0x00000000
611#define CONFIG_SYS_IBAT7U 0x00000000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500612
Jon Loeligerdebb7352006-04-26 17:58:56 -0500613/*
614 * Environment
615 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200616#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200617 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200618 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200619 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500620#else
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200621 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200622 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500623#endif
Becky Bruce0f2d6602008-11-05 14:55:31 -0600624#define CONFIG_ENV_SIZE 0x2000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500625
626#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200627#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500628
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500629
630/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500631 * BOOTP options
632 */
633#define CONFIG_BOOTP_BOOTFILESIZE
634#define CONFIG_BOOTP_BOOTPATH
635#define CONFIG_BOOTP_GATEWAY
636#define CONFIG_BOOTP_HOSTNAME
637
638
639/*
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500640 * Command line configuration.
641 */
642#include <config_cmd_default.h>
643
644#define CONFIG_CMD_PING
645#define CONFIG_CMD_I2C
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600646#define CONFIG_CMD_REGINFO
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500647
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200648#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500649 #undef CONFIG_CMD_SAVEENV
Jon Loeligerdebb7352006-04-26 17:58:56 -0500650#endif
651
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500652#if defined(CONFIG_PCI)
653 #define CONFIG_CMD_PCI
654 #define CONFIG_CMD_SCSI
655 #define CONFIG_CMD_EXT2
Zhang Weibbf47962007-10-25 17:30:04 +0800656 #define CONFIG_CMD_USB
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500657#endif
658
Jon Loeligerdebb7352006-04-26 17:58:56 -0500659
660#undef CONFIG_WATCHDOG /* watchdog disabled */
661
662/*
663 * Miscellaneous configurable options
664 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200665#define CONFIG_SYS_LONGHELP /* undef to save memory */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200666#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200667#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
668#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500669
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500670#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200671 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500672#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200673 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500674#endif
675
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200676#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
677#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
678#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
679#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500680
681/*
682 * For booting Linux, the board info and command line data
683 * have to be in the first 8 MB of memory, since this is
684 * the maximum mapped by the Linux kernel during initialization.
685 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200686#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Jon Loeligerdebb7352006-04-26 17:58:56 -0500687
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500688#if defined(CONFIG_CMD_KGDB)
689 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
690 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500691#endif
692
Jon Loeligerdebb7352006-04-26 17:58:56 -0500693/*
694 * Environment Configuration
695 */
696
697/* The mac addresses for all ethernet interface */
698#if defined(CONFIG_TSEC_ENET)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200699#define CONFIG_ETHADDR 00:E0:0C:00:00:01
Jon Loeligerdebb7352006-04-26 17:58:56 -0500700#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
701#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
702#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
703#endif
704
Andy Fleming10327dc2007-08-16 16:35:02 -0500705#define CONFIG_HAS_ETH0 1
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500706#define CONFIG_HAS_ETH1 1
707#define CONFIG_HAS_ETH2 1
708#define CONFIG_HAS_ETH3 1
Jon Loeligerdebb7352006-04-26 17:58:56 -0500709
Jon Loeliger18b6c8c2006-05-09 08:23:49 -0500710#define CONFIG_IPADDR 192.168.1.100
Jon Loeligerdebb7352006-04-26 17:58:56 -0500711
712#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000713#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000714#define CONFIG_BOOTFILE "uImage"
Ed Swarthout32922cd2007-06-05 12:30:52 -0500715#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500716
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500717#define CONFIG_SERVERIP 192.168.1.1
Jon Loeliger18b6c8c2006-05-09 08:23:49 -0500718#define CONFIG_GATEWAYIP 192.168.1.1
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500719#define CONFIG_NETMASK 255.255.255.0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500720
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500721/* default location for tftp and bootm */
722#define CONFIG_LOADADDR 1000000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500723
724#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200725#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500726
727#define CONFIG_BAUDRATE 115200
728
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200729#define CONFIG_EXTRA_ENV_SETTINGS \
730 "netdev=eth0\0" \
731 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
732 "tftpflash=tftpboot $loadaddr $uboot; " \
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200733 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
734 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
735 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
736 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
737 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200738 "consoledev=ttyS0\0" \
739 "ramdiskaddr=2000000\0" \
740 "ramdiskfile=your.ramdisk.u-boot\0" \
741 "fdtaddr=c00000\0" \
742 "fdtfile=mpc8641_hpcn.dtb\0" \
Becky Bruce3111d322008-11-06 17:37:35 -0600743 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
744 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200745 "maxcpus=2"
Jon Loeligerdebb7352006-04-26 17:58:56 -0500746
747
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200748#define CONFIG_NFSBOOTCOMMAND \
749 "setenv bootargs root=/dev/nfs rw " \
750 "nfsroot=$serverip:$rootpath " \
751 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
752 "console=$consoledev,$baudrate $othbootargs;" \
753 "tftp $loadaddr $bootfile;" \
754 "tftp $fdtaddr $fdtfile;" \
755 "bootm $loadaddr - $fdtaddr"
Jon Loeligerdebb7352006-04-26 17:58:56 -0500756
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200757#define CONFIG_RAMBOOTCOMMAND \
758 "setenv bootargs root=/dev/ram rw " \
759 "console=$consoledev,$baudrate $othbootargs;" \
760 "tftp $ramdiskaddr $ramdiskfile;" \
761 "tftp $loadaddr $bootfile;" \
762 "tftp $fdtaddr $fdtfile;" \
763 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeligerdebb7352006-04-26 17:58:56 -0500764
765#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
766
767#endif /* __CONFIG_H */