Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2006 Freescale Semiconductor. |
| 3 | * |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 4 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | /* |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 26 | * MPC8641HPCN board configuration file |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 27 | * |
| 28 | * Make sure you change the MAC address and other network params first, |
| 29 | * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. |
| 30 | */ |
| 31 | |
| 32 | #ifndef __CONFIG_H |
| 33 | #define __CONFIG_H |
| 34 | |
| 35 | /* High Level Configuration Options */ |
| 36 | #define CONFIG_MPC86xx 1 /* MPC86xx */ |
| 37 | #define CONFIG_MPC8641 1 /* MPC8641 specific */ |
| 38 | #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 39 | #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ |
| 40 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 41 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 42 | #ifdef RUN_DIAG |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 43 | #define CONFIG_SYS_DIAG_ADDR 0xff800000 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 44 | #endif |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 45 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 46 | #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 47 | |
Becky Bruce | af5d100 | 2008-10-31 17:14:14 -0500 | [diff] [blame^] | 48 | /* |
| 49 | * set this to enable Rapid IO. PCI and RIO are mutually exclusive |
| 50 | */ |
| 51 | /*#define CONFIG_RIO 1*/ |
| 52 | |
| 53 | #ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */ |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 54 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
| 55 | #define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */ |
| 56 | #define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */ |
| 57 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
Kumar Gala | 8ba93f6 | 2008-10-21 18:06:15 -0500 | [diff] [blame] | 58 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
Becky Bruce | af5d100 | 2008-10-31 17:14:14 -0500 | [diff] [blame^] | 59 | #endif |
Becky Bruce | 4933b91 | 2008-01-23 16:31:01 -0600 | [diff] [blame] | 60 | #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 61 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 62 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 63 | #define CONFIG_ENV_OVERWRITE |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 64 | |
Becky Bruce | 31d8267 | 2008-05-08 19:02:12 -0500 | [diff] [blame] | 65 | #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 66 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 67 | #define CONFIG_ALTIVEC 1 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 68 | |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 69 | /* |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 70 | * L2CR setup -- make sure this is right for your board! |
| 71 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 72 | #define CONFIG_SYS_L2 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 73 | #define L2_INIT 0 |
| 74 | #define L2_ENABLE (L2CR_L2E) |
| 75 | |
| 76 | #ifndef CONFIG_SYS_CLK_FREQ |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 77 | #ifndef __ASSEMBLY__ |
| 78 | extern unsigned long get_board_sys_clk(unsigned long dummy); |
| 79 | #endif |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 80 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 81 | #endif |
| 82 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 83 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
| 84 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 85 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
| 86 | #define CONFIG_SYS_MEMTEST_END 0x00400000 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 87 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 88 | /* |
| 89 | * Base addresses -- Note these are effective addresses where the |
| 90 | * actual resources get mapped (not physical addresses) |
| 91 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 92 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
| 93 | #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ |
| 94 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 95 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 96 | #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) |
| 97 | #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) |
Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 98 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 99 | /* |
| 100 | * DDR Setup |
| 101 | */ |
Kumar Gala | 6a8e569 | 2008-08-26 15:01:35 -0500 | [diff] [blame] | 102 | #define CONFIG_FSL_DDR2 |
| 103 | #undef CONFIG_FSL_DDR_INTERACTIVE |
| 104 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
| 105 | #define CONFIG_DDR_SPD |
| 106 | |
| 107 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
| 108 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 109 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 110 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
| 111 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
Jin Zhengxiong | fcb28e7 | 2006-07-13 10:35:10 -0500 | [diff] [blame] | 112 | #define CONFIG_VERY_BIG_RAM |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 113 | |
| 114 | #define MPC86xx_DDR_SDRAM_CLK_CNTL |
| 115 | |
Kumar Gala | 6a8e569 | 2008-08-26 15:01:35 -0500 | [diff] [blame] | 116 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
| 117 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 |
| 118 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 119 | |
Kumar Gala | 6a8e569 | 2008-08-26 15:01:35 -0500 | [diff] [blame] | 120 | /* |
| 121 | * I2C addresses of SPD EEPROMs |
| 122 | */ |
| 123 | #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ |
| 124 | #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ |
| 125 | #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ |
| 126 | #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 127 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 128 | |
Kumar Gala | 6a8e569 | 2008-08-26 15:01:35 -0500 | [diff] [blame] | 129 | /* |
| 130 | * These are used when DDR doesn't use SPD. |
| 131 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 132 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
| 133 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F |
| 134 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ |
| 135 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
| 136 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 |
| 137 | #define CONFIG_SYS_DDR_TIMING_1 0x39357322 |
| 138 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 |
| 139 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 |
| 140 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 |
| 141 | #define CONFIG_SYS_DDR_INTERVAL 0x06090100 |
| 142 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
| 143 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 |
| 144 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 |
| 145 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 |
| 146 | #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ |
| 147 | #define CONFIG_SYS_DDR_CONTROL2 0x04400000 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 148 | |
Jon Loeliger | ad8f868 | 2008-01-15 13:42:41 -0600 | [diff] [blame] | 149 | #define CONFIG_ID_EEPROM |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 150 | #define CONFIG_SYS_I2C_EEPROM_NXID |
Jean-Christophe PLAGNIOL-VILLARD | 32628c5 | 2008-08-30 23:54:58 +0200 | [diff] [blame] | 151 | #define CONFIG_ID_EEPROM |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 152 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 153 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 154 | |
| 155 | /* |
Jon Loeliger | 586d1d5 | 2006-05-19 13:22:44 -0500 | [diff] [blame] | 156 | * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000. |
| 157 | * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 158 | * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. |
| 159 | * However, when u-boot comes up, the flash_init needs hard start addresses |
Jon Loeliger | 586d1d5 | 2006-05-19 13:22:44 -0500 | [diff] [blame] | 160 | * to build its info table. For user convenience, the flash addresses is |
| 161 | * fe800000 and ff800000. That way, u-boot knows where the flash is |
| 162 | * and the user can download u-boot code from promjet to fef00000, a |
| 163 | * more intuitive location than fe700000. |
| 164 | * |
| 165 | * Note that, on switching the boot location, fef00000 becomes fff00000. |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 166 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 167 | #define CONFIG_SYS_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ |
| 168 | #define CONFIG_SYS_FLASH_BASE2 0xff800000 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 169 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 170 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 171 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 172 | #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ |
| 173 | #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 174 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 175 | #define CONFIG_SYS_BR1_PRELIM 0xfe001001 /* port size 16bit */ |
| 176 | #define CONFIG_SYS_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 177 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 178 | #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */ |
| 179 | #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 180 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 181 | #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */ |
| 182 | #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 183 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 184 | |
Kim Phillips | 7608d75 | 2007-08-21 17:00:17 -0500 | [diff] [blame] | 185 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 186 | #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 187 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ |
| 188 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ |
| 189 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ |
| 190 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ |
| 191 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ |
| 192 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ |
| 193 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ |
| 194 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ |
| 195 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ |
| 196 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ |
| 197 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
| 198 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ |
| 199 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ |
| 200 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 201 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 202 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 203 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 204 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 205 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 206 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 207 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 208 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 209 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 210 | |
Jean-Christophe PLAGNIOL-VILLARD | 00b1883 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 211 | #define CONFIG_FLASH_CFI_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 212 | #define CONFIG_SYS_FLASH_CFI |
| 213 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 214 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 215 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 216 | #define CONFIG_SYS_RAMBOOT |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 217 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 218 | #undef CONFIG_SYS_RAMBOOT |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 219 | #endif |
| 220 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 221 | #if defined(CONFIG_SYS_RAMBOOT) |
Jin Zhengxiong-R64188 | fa7db9c | 2006-06-27 18:11:54 +0800 | [diff] [blame] | 222 | #undef CONFIG_SPD_EEPROM |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 223 | #define CONFIG_SYS_SDRAM_SIZE 256 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 224 | #endif |
| 225 | |
| 226 | #undef CONFIG_CLOCKS_IN_MHZ |
| 227 | |
| 228 | #define CONFIG_L1_INIT_RAM |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 229 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 230 | #ifndef CONFIG_SYS_INIT_RAM_LOCK |
| 231 | #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 232 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 233 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 234 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 235 | #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 236 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 237 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
| 238 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
| 239 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 240 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 241 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 242 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 243 | |
| 244 | /* Serial Port */ |
| 245 | #define CONFIG_CONS_INDEX 1 |
| 246 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 247 | #define CONFIG_SYS_NS16550 |
| 248 | #define CONFIG_SYS_NS16550_SERIAL |
| 249 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 250 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 251 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 252 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 253 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 254 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 255 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 256 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 257 | |
| 258 | /* Use the HUSH parser */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 259 | #define CONFIG_SYS_HUSH_PARSER |
| 260 | #ifdef CONFIG_SYS_HUSH_PARSER |
| 261 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 262 | #endif |
| 263 | |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 264 | /* |
| 265 | * Pass open firmware flat tree to kernel |
| 266 | */ |
Jon Loeliger | ea9f739 | 2007-11-28 14:47:18 -0600 | [diff] [blame] | 267 | #define CONFIG_OF_LIBFDT 1 |
| 268 | #define CONFIG_OF_BOARD_SETUP 1 |
| 269 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 270 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 271 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 272 | #define CONFIG_SYS_64BIT_VSPRINTF 1 |
| 273 | #define CONFIG_SYS_64BIT_STRTOUL 1 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 274 | |
Jon Loeliger | 586d1d5 | 2006-05-19 13:22:44 -0500 | [diff] [blame] | 275 | /* |
| 276 | * I2C |
| 277 | */ |
Jon Loeliger | 2047672 | 2006-10-20 15:50:15 -0500 | [diff] [blame] | 278 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
| 279 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 280 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 281 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 282 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
| 283 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
| 284 | #define CONFIG_SYS_I2C_OFFSET 0x3100 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 285 | |
Jon Loeliger | 586d1d5 | 2006-05-19 13:22:44 -0500 | [diff] [blame] | 286 | /* |
| 287 | * RapidIO MMU |
| 288 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 289 | #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ |
| 290 | #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE |
| 291 | #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 292 | |
| 293 | /* |
| 294 | * General PCI |
| 295 | * Addresses are mapped 1-1. |
| 296 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 297 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
| 298 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE |
| 299 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
| 300 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
| 301 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
| 302 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 303 | |
| 304 | /* For RTL8139 */ |
Jin Zhengxiong-R64188 | bc09cf3 | 2006-06-27 18:12:10 +0800 | [diff] [blame] | 305 | #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 306 | #define _IO_BASE 0x00000000 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 307 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 308 | #define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 |
| 309 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE |
| 310 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ |
| 311 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 |
| 312 | #define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000 |
| 313 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 314 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 315 | #if defined(CONFIG_PCI) |
| 316 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 317 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 318 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 319 | #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 320 | |
| 321 | #define CONFIG_NET_MULTI |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 322 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 323 | |
| 324 | #define CONFIG_RTL8139 |
| 325 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 326 | #undef CONFIG_EEPRO100 |
| 327 | #undef CONFIG_TULIP |
| 328 | |
Zhang Wei | a81d1c0 | 2007-06-06 10:08:14 +0200 | [diff] [blame] | 329 | /************************************************************ |
| 330 | * USB support |
| 331 | ************************************************************/ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 332 | #define CONFIG_PCI_OHCI 1 |
Zhang Wei | a81d1c0 | 2007-06-06 10:08:14 +0200 | [diff] [blame] | 333 | #define CONFIG_USB_OHCI_NEW 1 |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 334 | #define CONFIG_USB_KEYBOARD 1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 335 | #define CONFIG_SYS_DEVICE_DEREGISTER |
| 336 | #define CONFIG_SYS_USB_EVENT_POLL 1 |
| 337 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" |
| 338 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 |
| 339 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 |
Zhang Wei | a81d1c0 | 2007-06-06 10:08:14 +0200 | [diff] [blame] | 340 | |
Jason Jin | 0f460a1 | 2007-07-13 12:14:58 +0800 | [diff] [blame] | 341 | /*PCIE video card used*/ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 342 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_PHYS |
Jason Jin | 0f460a1 | 2007-07-13 12:14:58 +0800 | [diff] [blame] | 343 | |
| 344 | /*PCI video card used*/ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 345 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/ |
Jason Jin | 0f460a1 | 2007-07-13 12:14:58 +0800 | [diff] [blame] | 346 | |
| 347 | /* video */ |
| 348 | #define CONFIG_VIDEO |
| 349 | |
| 350 | #if defined(CONFIG_VIDEO) |
| 351 | #define CONFIG_BIOSEMU |
| 352 | #define CONFIG_CFB_CONSOLE |
| 353 | #define CONFIG_VIDEO_SW_CURSOR |
| 354 | #define CONFIG_VGA_AS_SINGLE_DEVICE |
| 355 | #define CONFIG_ATI_RADEON_FB |
| 356 | #define CONFIG_VIDEO_LOGO |
| 357 | /*#define CONFIG_CONSOLE_CURSOR*/ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 358 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_PHYS |
Jason Jin | 0f460a1 | 2007-07-13 12:14:58 +0800 | [diff] [blame] | 359 | #endif |
| 360 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 361 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 362 | |
Jin Zhengxiong | dabf9ef | 2006-08-23 19:15:12 +0800 | [diff] [blame] | 363 | #define CONFIG_DOS_PARTITION |
| 364 | #define CONFIG_SCSI_AHCI |
| 365 | |
| 366 | #ifdef CONFIG_SCSI_AHCI |
| 367 | #define CONFIG_SATA_ULI5288 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 368 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
| 369 | #define CONFIG_SYS_SCSI_MAX_LUN 1 |
| 370 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) |
| 371 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE |
Jin Zhengxiong | dabf9ef | 2006-08-23 19:15:12 +0800 | [diff] [blame] | 372 | #endif |
| 373 | |
Jason Jin | 0f460a1 | 2007-07-13 12:14:58 +0800 | [diff] [blame] | 374 | #define CONFIG_MPC86XX_PCI2 |
| 375 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 376 | #endif /* CONFIG_PCI */ |
| 377 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 378 | #if defined(CONFIG_TSEC_ENET) |
| 379 | |
| 380 | #ifndef CONFIG_NET_MULTI |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 381 | #define CONFIG_NET_MULTI 1 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 382 | #endif |
| 383 | |
| 384 | #define CONFIG_MII 1 /* MII PHY management */ |
| 385 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 386 | #define CONFIG_TSEC1 1 |
| 387 | #define CONFIG_TSEC1_NAME "eTSEC1" |
| 388 | #define CONFIG_TSEC2 1 |
| 389 | #define CONFIG_TSEC2_NAME "eTSEC2" |
| 390 | #define CONFIG_TSEC3 1 |
| 391 | #define CONFIG_TSEC3_NAME "eTSEC3" |
| 392 | #define CONFIG_TSEC4 1 |
| 393 | #define CONFIG_TSEC4_NAME "eTSEC4" |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 394 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 395 | #define TSEC1_PHY_ADDR 0 |
| 396 | #define TSEC2_PHY_ADDR 1 |
| 397 | #define TSEC3_PHY_ADDR 2 |
| 398 | #define TSEC4_PHY_ADDR 3 |
| 399 | #define TSEC1_PHYIDX 0 |
| 400 | #define TSEC2_PHYIDX 0 |
| 401 | #define TSEC3_PHYIDX 0 |
| 402 | #define TSEC4_PHYIDX 0 |
Andy Fleming | 3a79013 | 2007-08-15 20:03:25 -0500 | [diff] [blame] | 403 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 404 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 405 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 406 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 407 | |
| 408 | #define CONFIG_ETHPRIME "eTSEC1" |
| 409 | |
| 410 | #endif /* CONFIG_TSEC_ENET */ |
| 411 | |
Jon Loeliger | 586d1d5 | 2006-05-19 13:22:44 -0500 | [diff] [blame] | 412 | /* |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 413 | * BAT0 2G Cacheable, non-guarded |
| 414 | * 0x0000_0000 2G DDR |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 415 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 416 | #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
| 417 | #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) |
| 418 | #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) |
| 419 | #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 420 | |
Jon Loeliger | 586d1d5 | 2006-05-19 13:22:44 -0500 | [diff] [blame] | 421 | /* |
Becky Bruce | af5d100 | 2008-10-31 17:14:14 -0500 | [diff] [blame^] | 422 | * BAT1 unused |
| 423 | */ |
| 424 | #define CONFIG_SYS_DBAT1L 0 |
| 425 | #define CONFIG_SYS_DBAT1U 0 |
| 426 | #define CONFIG_SYS_IBAT1L 0 |
| 427 | #define CONFIG_SYS_IBAT1U 0 |
| 428 | |
| 429 | /* if CONFIG_PCI: |
| 430 | * BAT2 1G Cache-inhibited, guarded |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 431 | * 0x8000_0000 512M PCI-Express 1 Memory |
| 432 | * 0xa000_0000 512M PCI-Express 2 Memory |
Jon Loeliger | 586d1d5 | 2006-05-19 13:22:44 -0500 | [diff] [blame] | 433 | * Changed it for operating from 0xd0000000 |
Becky Bruce | af5d100 | 2008-10-31 17:14:14 -0500 | [diff] [blame^] | 434 | * |
| 435 | * if CONFIG_RIO |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 436 | * BAT2 512M Cache-inhibited, guarded |
| 437 | * 0xc000_0000 512M RapidIO Memory |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 438 | */ |
Becky Bruce | af5d100 | 2008-10-31 17:14:14 -0500 | [diff] [blame^] | 439 | #ifdef CONFIG_PCI |
| 440 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \ |
| 441 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 442 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G \ |
| 443 | | BATU_VS | BATU_VP) |
| 444 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \ |
| 445 | | BATL_CACHEINHIBIT) |
| 446 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U |
| 447 | #else /* CONFIG_RIO */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 448 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \ |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 449 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 450 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) |
| 451 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 452 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U |
Becky Bruce | af5d100 | 2008-10-31 17:14:14 -0500 | [diff] [blame^] | 453 | #endif |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 454 | |
Jon Loeliger | 586d1d5 | 2006-05-19 13:22:44 -0500 | [diff] [blame] | 455 | /* |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 456 | * BAT3 4M Cache-inhibited, guarded |
| 457 | * 0xf800_0000 4M CCSR |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 458 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 459 | #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 460 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 461 | #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) |
| 462 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 463 | #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 464 | |
Jon Loeliger | 586d1d5 | 2006-05-19 13:22:44 -0500 | [diff] [blame] | 465 | /* |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 466 | * BAT4 32M Cache-inhibited, guarded |
| 467 | * 0xe200_0000 16M PCI-Express 1 I/O |
| 468 | * 0xe300_0000 16M PCI-Express 2 I/0 |
Jon Loeliger | 586d1d5 | 2006-05-19 13:22:44 -0500 | [diff] [blame] | 469 | * Note that this is at 0xe0000000 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 470 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 471 | #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \ |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 472 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 473 | #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) |
| 474 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 475 | #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 476 | |
Jon Loeliger | 586d1d5 | 2006-05-19 13:22:44 -0500 | [diff] [blame] | 477 | /* |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 478 | * BAT5 128K Cacheable, non-guarded |
| 479 | * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 480 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 481 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
| 482 | #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) |
| 483 | #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L |
| 484 | #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 485 | |
Jon Loeliger | 586d1d5 | 2006-05-19 13:22:44 -0500 | [diff] [blame] | 486 | /* |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 487 | * BAT6 32M Cache-inhibited, guarded |
| 488 | * 0xfe00_0000 32M FLASH |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 489 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 490 | #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 491 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 492 | #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) |
| 493 | #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) |
| 494 | #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 495 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 496 | #define CONFIG_SYS_DBAT7L 0x00000000 |
| 497 | #define CONFIG_SYS_DBAT7U 0x00000000 |
| 498 | #define CONFIG_SYS_IBAT7L 0x00000000 |
| 499 | #define CONFIG_SYS_IBAT7U 0x00000000 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 500 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 501 | /* |
| 502 | * Environment |
| 503 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 504 | #ifndef CONFIG_SYS_RAMBOOT |
Jean-Christophe PLAGNIOL-VILLARD | 5a1aceb | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 505 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 506 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 507 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
| 508 | #define CONFIG_ENV_SIZE 0x2000 |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 509 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 93f6d72 | 2008-09-10 22:48:00 +0200 | [diff] [blame] | 510 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 511 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 512 | #define CONFIG_ENV_SIZE 0x2000 |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 513 | #endif |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 514 | |
| 515 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 516 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 517 | |
Jon Loeliger | 2f9c19e | 2007-06-11 19:03:44 -0500 | [diff] [blame] | 518 | |
| 519 | /* |
Jon Loeliger | 659e2f6 | 2007-07-10 09:10:49 -0500 | [diff] [blame] | 520 | * BOOTP options |
| 521 | */ |
| 522 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 523 | #define CONFIG_BOOTP_BOOTPATH |
| 524 | #define CONFIG_BOOTP_GATEWAY |
| 525 | #define CONFIG_BOOTP_HOSTNAME |
| 526 | |
| 527 | |
| 528 | /* |
Jon Loeliger | 2f9c19e | 2007-06-11 19:03:44 -0500 | [diff] [blame] | 529 | * Command line configuration. |
| 530 | */ |
| 531 | #include <config_cmd_default.h> |
| 532 | |
| 533 | #define CONFIG_CMD_PING |
| 534 | #define CONFIG_CMD_I2C |
Becky Bruce | 4f93f8b | 2008-01-23 16:31:06 -0600 | [diff] [blame] | 535 | #define CONFIG_CMD_REGINFO |
Jon Loeliger | 2f9c19e | 2007-06-11 19:03:44 -0500 | [diff] [blame] | 536 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 537 | #if defined(CONFIG_SYS_RAMBOOT) |
Jon Loeliger | 2f9c19e | 2007-06-11 19:03:44 -0500 | [diff] [blame] | 538 | #undef CONFIG_CMD_ENV |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 539 | #endif |
| 540 | |
Jon Loeliger | 2f9c19e | 2007-06-11 19:03:44 -0500 | [diff] [blame] | 541 | #if defined(CONFIG_PCI) |
| 542 | #define CONFIG_CMD_PCI |
| 543 | #define CONFIG_CMD_SCSI |
| 544 | #define CONFIG_CMD_EXT2 |
Zhang Wei | bbf4796 | 2007-10-25 17:30:04 +0800 | [diff] [blame] | 545 | #define CONFIG_CMD_USB |
Jon Loeliger | 2f9c19e | 2007-06-11 19:03:44 -0500 | [diff] [blame] | 546 | #endif |
| 547 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 548 | |
| 549 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 550 | |
| 551 | /* |
| 552 | * Miscellaneous configurable options |
| 553 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 554 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 555 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 556 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 557 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 558 | |
Jon Loeliger | 2f9c19e | 2007-06-11 19:03:44 -0500 | [diff] [blame] | 559 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 560 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 561 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 562 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 563 | #endif |
| 564 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 565 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 566 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 567 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| 568 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 569 | |
| 570 | /* |
| 571 | * For booting Linux, the board info and command line data |
| 572 | * have to be in the first 8 MB of memory, since this is |
| 573 | * the maximum mapped by the Linux kernel during initialization. |
| 574 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 575 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 576 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 577 | /* |
| 578 | * Internal Definitions |
| 579 | * |
| 580 | * Boot Flags |
| 581 | */ |
| 582 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 583 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 584 | |
Jon Loeliger | 2f9c19e | 2007-06-11 19:03:44 -0500 | [diff] [blame] | 585 | #if defined(CONFIG_CMD_KGDB) |
| 586 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 587 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 588 | #endif |
| 589 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 590 | /* |
| 591 | * Environment Configuration |
| 592 | */ |
| 593 | |
| 594 | /* The mac addresses for all ethernet interface */ |
| 595 | #if defined(CONFIG_TSEC_ENET) |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 596 | #define CONFIG_ETHADDR 00:E0:0C:00:00:01 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 597 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
| 598 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD |
| 599 | #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD |
| 600 | #endif |
| 601 | |
Andy Fleming | 10327dc | 2007-08-16 16:35:02 -0500 | [diff] [blame] | 602 | #define CONFIG_HAS_ETH0 1 |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 603 | #define CONFIG_HAS_ETH1 1 |
| 604 | #define CONFIG_HAS_ETH2 1 |
| 605 | #define CONFIG_HAS_ETH3 1 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 606 | |
Jon Loeliger | 18b6c8c | 2006-05-09 08:23:49 -0500 | [diff] [blame] | 607 | #define CONFIG_IPADDR 192.168.1.100 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 608 | |
| 609 | #define CONFIG_HOSTNAME unknown |
| 610 | #define CONFIG_ROOTPATH /opt/nfsroot |
| 611 | #define CONFIG_BOOTFILE uImage |
Ed Swarthout | 32922cd | 2007-06-05 12:30:52 -0500 | [diff] [blame] | 612 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 613 | |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 614 | #define CONFIG_SERVERIP 192.168.1.1 |
Jon Loeliger | 18b6c8c | 2006-05-09 08:23:49 -0500 | [diff] [blame] | 615 | #define CONFIG_GATEWAYIP 192.168.1.1 |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 616 | #define CONFIG_NETMASK 255.255.255.0 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 617 | |
Jon Loeliger | 5c9efb3 | 2006-04-27 10:15:16 -0500 | [diff] [blame] | 618 | /* default location for tftp and bootm */ |
| 619 | #define CONFIG_LOADADDR 1000000 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 620 | |
| 621 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 622 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 623 | |
| 624 | #define CONFIG_BAUDRATE 115200 |
| 625 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 626 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 627 | "netdev=eth0\0" \ |
| 628 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ |
| 629 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
| 630 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ |
| 631 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ |
| 632 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ |
| 633 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ |
| 634 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ |
| 635 | "consoledev=ttyS0\0" \ |
| 636 | "ramdiskaddr=2000000\0" \ |
| 637 | "ramdiskfile=your.ramdisk.u-boot\0" \ |
| 638 | "fdtaddr=c00000\0" \ |
| 639 | "fdtfile=mpc8641_hpcn.dtb\0" \ |
| 640 | "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ |
| 641 | "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ |
| 642 | "maxcpus=2" |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 643 | |
| 644 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 645 | #define CONFIG_NFSBOOTCOMMAND \ |
| 646 | "setenv bootargs root=/dev/nfs rw " \ |
| 647 | "nfsroot=$serverip:$rootpath " \ |
| 648 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 649 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 650 | "tftp $loadaddr $bootfile;" \ |
| 651 | "tftp $fdtaddr $fdtfile;" \ |
| 652 | "bootm $loadaddr - $fdtaddr" |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 653 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 654 | #define CONFIG_RAMBOOTCOMMAND \ |
| 655 | "setenv bootargs root=/dev/ram rw " \ |
| 656 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 657 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 658 | "tftp $loadaddr $bootfile;" \ |
| 659 | "tftp $fdtaddr $fdtfile;" \ |
| 660 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 661 | |
| 662 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
| 663 | |
| 664 | #endif /* __CONFIG_H */ |