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wdenk75dc29e2002-08-19 15:30:13 +00001/*
Wolfgang Denk7c803be2008-09-16 18:02:19 +02002 * (C) Copyright 2000-2008
wdenk75dc29e2002-08-19 15:30:13 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#undef TQM8xxL_80MHz /* 1 / * define for 80 MHz CPU only */
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
39#define CONFIG_SM850 1 /*...on a MPC850 Service Module */
40
Wolfgang Denk2ae18242010-10-06 09:05:45 +020041#define CONFIG_SYS_TEXT_BASE 0x40000000
42
wdenk75dc29e2002-08-19 15:30:13 +000043#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020044#define CONFIG_SYS_SMC_RXBUFLEN 128
45#define CONFIG_SYS_MAXIDLE 10
wdenk75dc29e2002-08-19 15:30:13 +000046#define CONFIG_BAUDRATE 115200
wdenk75dc29e2002-08-19 15:30:13 +000047#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenk75dc29e2002-08-19 15:30:13 +000048
49#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
50
51#define CONFIG_BOARD_TYPES 1 /* support board types */
52
53#undef CONFIG_BOOTARGS
54#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020055 "bootp; " \
56 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
57 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk75dc29e2002-08-19 15:30:13 +000058 "bootm"
59
60#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk75dc29e2002-08-19 15:30:13 +000062
63#undef CONFIG_WATCHDOG /* watchdog disabled */
64
65#undef CONFIG_STATUS_LED /* Status LED not enabled */
66
67#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
68
Jon Loeliger18225e82007-07-09 21:31:24 -050069/*
70 * BOOTP options
71 */
72#define CONFIG_BOOTP_SUBNETMASK
73#define CONFIG_BOOTP_GATEWAY
74#define CONFIG_BOOTP_HOSTNAME
75#define CONFIG_BOOTP_BOOTPATH
76#define CONFIG_BOOTP_BOOTFILESIZE
77
wdenk75dc29e2002-08-19 15:30:13 +000078
79#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
80
wdenk75dc29e2002-08-19 15:30:13 +000081
Jon Loeligerfe7f7822007-07-08 15:02:44 -050082/*
83 * Command line configuration.
84 */
85#include <config_cmd_default.h>
86
87#define CONFIG_CMD_DHCP
88#define CONFIG_CMD_DATE
89
wdenk75dc29e2002-08-19 15:30:13 +000090
91/*
92 * Miscellaneous configurable options
93 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_LONGHELP /* undef to save memory */
95#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerfe7f7822007-07-08 15:02:44 -050096#if defined(CONFIG_CMD_KGDB) && defined(KGDB_DEBUG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk75dc29e2002-08-19 15:30:13 +000098#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk75dc29e2002-08-19 15:30:13 +0000100#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
102#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
103#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk75dc29e2002-08-19 15:30:13 +0000104
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
106#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk75dc29e2002-08-19 15:30:13 +0000107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk75dc29e2002-08-19 15:30:13 +0000109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk75dc29e2002-08-19 15:30:13 +0000111
wdenk75dc29e2002-08-19 15:30:13 +0000112/*
113 * Low Level Configuration Settings
114 * (address mappings, register initial values, etc.)
115 * You should know what you are doing if you make changes here.
116 */
117/*-----------------------------------------------------------------------
118 * Internal Memory Mapped Register
119 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_IMMR 0xFFF00000
wdenk75dc29e2002-08-19 15:30:13 +0000121
122/*-----------------------------------------------------------------------
123 * Definitions for initial stack pointer and data area (in DPRAM)
124 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200126#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200127#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk75dc29e2002-08-19 15:30:13 +0000129
130/*-----------------------------------------------------------------------
131 * Start addresses for the final memory configuration
132 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk75dc29e2002-08-19 15:30:13 +0000134 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_SDRAM_BASE 0x00000000
136#define CONFIG_SYS_FLASH_BASE 0x40000000
wdenk75dc29e2002-08-19 15:30:13 +0000137#if defined(DEBUG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenk75dc29e2002-08-19 15:30:13 +0000139#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
wdenk75dc29e2002-08-19 15:30:13 +0000141#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
143#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk75dc29e2002-08-19 15:30:13 +0000144
145/*
146 * For booting Linux, the board info and command line data
147 * have to be in the first 8 MB of memory, since this is
148 * the maximum mapped by the Linux kernel during initialization.
149 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk75dc29e2002-08-19 15:30:13 +0000151
152/*-----------------------------------------------------------------------
153 * FLASH organization
154 */
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200155/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200157#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
159#define CONFIG_SYS_FLASH_EMPTY_INFO
160#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
161#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
162#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenk75dc29e2002-08-19 15:30:13 +0000163
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200164#define CONFIG_ENV_IS_IN_FLASH 1
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200165#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200166#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenk75dc29e2002-08-19 15:30:13 +0000167
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200168#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
169
wdenk75dc29e2002-08-19 15:30:13 +0000170/*-----------------------------------------------------------------------
171 * Hardware Information Block
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
174#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
175#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenk75dc29e2002-08-19 15:30:13 +0000176
177/*-----------------------------------------------------------------------
178 * Cache Configuration
179 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligerfe7f7822007-07-08 15:02:44 -0500181#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk75dc29e2002-08-19 15:30:13 +0000183#endif
184
185/*-----------------------------------------------------------------------
186 * SYPCR - System Protection Control 11-9
187 * SYPCR can only be written once after reset!
188 *-----------------------------------------------------------------------
189 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
190 */
191#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk75dc29e2002-08-19 15:30:13 +0000193 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
194#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk75dc29e2002-08-19 15:30:13 +0000196#endif
197
198/*-----------------------------------------------------------------------
199 * SIUMCR - SIU Module Configuration 11-6
200 *-----------------------------------------------------------------------
201 * PCMCIA config., multi-function pin tri-state
202 */
203#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenk75dc29e2002-08-19 15:30:13 +0000205#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenk75dc29e2002-08-19 15:30:13 +0000207#endif /* CONFIG_CAN_DRIVER */
208
209/*-----------------------------------------------------------------------
210 * TBSCR - Time Base Status and Control 11-26
211 *-----------------------------------------------------------------------
212 * Clear Reference Interrupt Status, Timebase freezing enabled
213 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenk75dc29e2002-08-19 15:30:13 +0000215
216/*-----------------------------------------------------------------------
217 * RTCSC - Real-Time Clock Status and Control Register 11-27
218 *-----------------------------------------------------------------------
219 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenk75dc29e2002-08-19 15:30:13 +0000221
222/*-----------------------------------------------------------------------
223 * PISCR - Periodic Interrupt Status and Control 11-31
224 *-----------------------------------------------------------------------
225 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
226 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk75dc29e2002-08-19 15:30:13 +0000228
229/*-----------------------------------------------------------------------
230 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
231 *-----------------------------------------------------------------------
232 * Reset PLL lock status sticky bit, timer expired status bit and timer
233 * interrupt status bit
234 *
235 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
236 */
237#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_PLPRCR \
wdenk75dc29e2002-08-19 15:30:13 +0000239 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
240#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenk75dc29e2002-08-19 15:30:13 +0000242#endif /* TQM8xxL_80MHz */
243
244/*-----------------------------------------------------------------------
245 * SCCR - System Clock and reset Control Register 15-27
246 *-----------------------------------------------------------------------
247 * Set clock output, timebase and RTC source and divider,
248 * power management and some other internal clocks
249 */
250#define SCCR_MASK SCCR_EBDF11
251#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ \
wdenk75dc29e2002-08-19 15:30:13 +0000253 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
254 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
255 SCCR_DFALCD00)
256#else /* up to 50 MHz we use a 1:1 clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_SCCR (SCCR_TBS | \
wdenk75dc29e2002-08-19 15:30:13 +0000258 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
259 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
260 SCCR_DFALCD00)
261#endif /* TQM8xxL_80MHz */
262
263/*-----------------------------------------------------------------------
264 * PCMCIA stuff
265 *-----------------------------------------------------------------------
266 *
267 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
269#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
270#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
271#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
272#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
273#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
274#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
275#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenk75dc29e2002-08-19 15:30:13 +0000276
277/*-----------------------------------------------------------------------
278 *
279 *-----------------------------------------------------------------------
280 *
281 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_DER 0
wdenk75dc29e2002-08-19 15:30:13 +0000283
284/*
285 * Init Memory Controller:
286 *
287 * BR0/1 and OR0/1 (FLASH)
288 */
289
290#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
291#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
292
293/* used to re-map FLASH both when starting from SRAM or FLASH:
294 * restrict access enough to keep SRAM working (if any)
295 * but not too much to meddle with FLASH accesses
296 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
298#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenk75dc29e2002-08-19 15:30:13 +0000299
300/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
wdenk75dc29e2002-08-19 15:30:13 +0000302 OR_SCY_5_CLK | OR_EHTR)
303
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
305#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
306#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenk75dc29e2002-08-19 15:30:13 +0000307
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
309#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
310#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenk75dc29e2002-08-19 15:30:13 +0000311
312/*
313 * BR2/3 and OR2/3 (SDRAM)
314 *
315 */
316#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
317#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
318#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
319
320/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenk75dc29e2002-08-19 15:30:13 +0000322
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
324#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenk75dc29e2002-08-19 15:30:13 +0000325
326#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
328#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenk75dc29e2002-08-19 15:30:13 +0000329#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
331#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
332#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
333#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenk75dc29e2002-08-19 15:30:13 +0000334 BR_PS_8 | BR_MS_UPMB | BR_V )
335#endif /* CONFIG_CAN_DRIVER */
336
337/*
338 * Memory Periodic Timer Prescaler
339 */
340
341/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
wdenk75dc29e2002-08-19 15:30:13 +0000343
344/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
346#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenk75dc29e2002-08-19 15:30:13 +0000347
348/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
350#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk75dc29e2002-08-19 15:30:13 +0000351
352/*
353 * MAMR settings for SDRAM
354 */
355
356/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk75dc29e2002-08-19 15:30:13 +0000358 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
359 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
360/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk75dc29e2002-08-19 15:30:13 +0000362 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
363 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
364
Heiko Schocher7026ead2010-02-09 15:50:27 +0100365/* pass open firmware flat tree */
366#define CONFIG_OF_LIBFDT 1
367#define CONFIG_OF_BOARD_SETUP 1
368#define CONFIG_HWCONFIG 1
369
wdenk75dc29e2002-08-19 15:30:13 +0000370#endif /* __CONFIG_H */