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wdenk5b1d7132002-11-03 00:07:02 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Keith Outwater, keith_outwater@mvis.com
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenk5b1d7132002-11-03 00:07:02 +00007 */
8
9/*
10 * board/config_GEN860T.h - board specific configuration options
11 */
12
13#ifndef __CONFIG_GEN860T_H
14#define __CONFIG_H
15
16/*
17 * High Level Configuration Options
18 */
19#define CONFIG_MPC860
20#define CONFIG_GEN860T
21
Wolfgang Denk2ae18242010-10-06 09:05:45 +020022#define CONFIG_SYS_TEXT_BASE 0x40000000
23
wdenk5b1d7132002-11-03 00:07:02 +000024/*
25 * Identify the board
26 */
wdenk7aa78612003-05-03 15:50:43 +000027#if !defined(CONFIG_SC)
Wolfgang Denk53677ef2008-05-20 16:00:29 +020028#define CONFIG_IDENT_STRING " B2"
wdenk7aa78612003-05-03 15:50:43 +000029#else
Wolfgang Denk53677ef2008-05-20 16:00:29 +020030#define CONFIG_IDENT_STRING " SC"
wdenk7aa78612003-05-03 15:50:43 +000031#endif
wdenk5b1d7132002-11-03 00:07:02 +000032
33/*
34 * Don't depend on the RTC clock to determine clock frequency -
35 * the 860's internal rtc uses a 32.768 KHz clock which is
36 * generated by the DS1337 - and the DS1337 clock can be turned off.
37 */
wdenk7aa78612003-05-03 15:50:43 +000038#if !defined(CONFIG_SC)
Wolfgang Denk53677ef2008-05-20 16:00:29 +020039#define CONFIG_8xx_GCLK_FREQ 66600000
wdenk7aa78612003-05-03 15:50:43 +000040#else
Wolfgang Denk53677ef2008-05-20 16:00:29 +020041#define CONFIG_8xx_GCLK_FREQ 48000000
wdenk7aa78612003-05-03 15:50:43 +000042#endif
wdenk5b1d7132002-11-03 00:07:02 +000043
44/*
45 * The RS-232 console port is on SMC1
46 */
47#define CONFIG_8xx_CONS_SMC1
Wolfgang Denk53677ef2008-05-20 16:00:29 +020048#define CONFIG_BAUDRATE 38400
wdenk5b1d7132002-11-03 00:07:02 +000049
50/*
wdenk5b1d7132002-11-03 00:07:02 +000051 * Print console information
52 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#undef CONFIG_SYS_CONSOLE_INFO_QUIET
wdenk5b1d7132002-11-03 00:07:02 +000054
55/*
56 * Set the autoboot delay in seconds. A delay of -1 disables autoboot
57 */
58#define CONFIG_BOOTDELAY 5
59
60/*
61 * Pass the clock frequency to the Linux kernel in units of MHz
62 */
63#define CONFIG_CLOCKS_IN_MHZ
64
65#define CONFIG_PREBOOT \
66 "echo;echo"
67
68#undef CONFIG_BOOTARGS
69#define CONFIG_BOOTCOMMAND \
70 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010071 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
72 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk5b1d7132002-11-03 00:07:02 +000073 "bootm"
74
75/*
76 * Turn off echo for serial download by default. Allow baud rate to be changed
77 * for downloads
78 */
79#undef CONFIG_LOADS_ECHO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_LOADS_BAUD_CHANGE
wdenk5b1d7132002-11-03 00:07:02 +000081
82/*
wdenk5b1d7132002-11-03 00:07:02 +000083 * Turn off the watchdog timer
84 */
85#undef CONFIG_WATCHDOG
86
87/*
88 * Do not reboot if a panic occurs
89 */
90#define CONFIG_PANIC_HANG
91
92/*
93 * Enable the status LED
94 */
95#define CONFIG_STATUS_LED
96
97/*
98 * Reset address. We pick an address such that when an instruction
99 * is executed at that address, a machine check exception occurs
100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_RESET_ADDRESS ((ulong) -1)
wdenk5b1d7132002-11-03 00:07:02 +0000102
103/*
104 * BOOTP options
105 */
Jon Loeliger5d2ebe12007-07-09 21:16:53 -0500106#define CONFIG_BOOTP_SUBNETMASK
107#define CONFIG_BOOTP_GATEWAY
108#define CONFIG_BOOTP_HOSTNAME
109#define CONFIG_BOOTP_BOOTPATH
110#define CONFIG_BOOTP_BOOTFILESIZE
111
wdenk5b1d7132002-11-03 00:07:02 +0000112
113/*
114 * The GEN860T network interface uses the on-chip 10/100 FEC with
115 * an Intel LXT971A PHY connected to the 860T's MII. The PHY's
116 * MII address is hardwired on the board to zero.
117 */
118#define CONFIG_FEC_ENET
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_DISCOVER_PHY
wdenk5b1d7132002-11-03 00:07:02 +0000120#define CONFIG_MII
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500121#define CONFIG_MII_INIT 1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200122#define CONFIG_PHY_ADDR 0
wdenk5b1d7132002-11-03 00:07:02 +0000123
124/*
125 * Set default IP stuff just to get bootstrap entries into the
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200126 * environment so that we can source the full default environment.
wdenk5b1d7132002-11-03 00:07:02 +0000127 */
128#define CONFIG_ETHADDR 9a:52:63:15:85:25
wdenk7aa78612003-05-03 15:50:43 +0000129#define CONFIG_SERVERIP 10.0.4.201
wdenk5b1d7132002-11-03 00:07:02 +0000130#define CONFIG_IPADDR 10.0.4.111
131
132/*
133 * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
134 * the MPC860T I2C interface.
135 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
137#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
138#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10 mS w/ 20% margin */
139#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200140#define CONFIG_ENV_EEPROM_SIZE (32 * 1024)
wdenk5b1d7132002-11-03 00:07:02 +0000141
wdenk5b1d7132002-11-03 00:07:02 +0000142/*
wdenk7aa78612003-05-03 15:50:43 +0000143 * Enable I2C and select the hardware/software driver
wdenk5b1d7132002-11-03 00:07:02 +0000144 */
Heiko Schocherea818db2013-01-29 08:53:15 +0100145#define CONFIG_HARD_I2C 1 /* CPM based I2C */
146#undef CONFIG_SYS_I2C_SOFT /* Bit-banged I2C */
wdenk7aa78612003-05-03 15:50:43 +0000147
148#ifdef CONFIG_HARD_I2C
Heiko Schocherea818db2013-01-29 08:53:15 +0100149#define CONFIG_SYS_I2C_SPEED 100000 /* clock speed in Hz */
150#define CONFIG_SYS_I2C_SLAVE 0xFE /* I2C slave address */
wdenk7aa78612003-05-03 15:50:43 +0000151#endif
152
Heiko Schocherea818db2013-01-29 08:53:15 +0100153#ifdef CONFIG_SYS_I2C_SOFT
154#define CONFIG_SYS_I2C
155#define CONFIG_SYS_I2C_SOFT_SPEED 50000
156#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
157#define PB_SCL 0x00000020 /* PB 26 */
158#define PB_SDA 0x00000010 /* PB 27 */
159#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
160#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
161#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
162#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
163#define I2C_SDA(bit) if (bit) \
164 immr->im_cpm.cp_pbdat |= PB_SDA; \
165 else \
166 immr->im_cpm.cp_pbdat &= ~PB_SDA
167#define I2C_SCL(bit) if (bit) \
168 immr->im_cpm.cp_pbdat |= PB_SCL; \
169 else \
170 immr->im_cpm.cp_pbdat &= ~PB_SCL
171#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
wdenk7aa78612003-05-03 15:50:43 +0000172#endif
wdenk5b1d7132002-11-03 00:07:02 +0000173
174/*
175 * Allow environment overwrites by anyone
176 */
177#define CONFIG_ENV_OVERWRITE
178
wdenk7aa78612003-05-03 15:50:43 +0000179#if !defined(CONFIG_SC)
wdenk5b1d7132002-11-03 00:07:02 +0000180/*
181 * The MPC860's internal RTC is horribly broken in rev D masks. Three
182 * internal MPC860T circuit nodes were inadvertently left floating; this
183 * causes KAPWR current in power down mode to be three orders of magnitude
184 * higher than specified in the datasheet (from 10 uA to 10 mA). No
185 * reasonable battery can keep that kind RTC running during powerdown for any
186 * length of time, so we use an external RTC on the I2C bus instead.
187 */
wdenk5b1d7132002-11-03 00:07:02 +0000188#define CONFIG_RTC_DS1337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_I2C_RTC_ADDR 0x68
wdenk7aa78612003-05-03 15:50:43 +0000190
191#else
192/*
193 * No external RTC on SC variant, so we're stuck with the internal one.
194 */
195#define CONFIG_RTC_MPC8xx
196#endif
wdenk5b1d7132002-11-03 00:07:02 +0000197
198/*
wdenk7aa78612003-05-03 15:50:43 +0000199 * Power On Self Test support
wdenk5b1d7132002-11-03 00:07:02 +0000200 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_POST ( CONFIG_SYS_POST_CACHE | \
202 CONFIG_SYS_POST_MEMORY | \
203 CONFIG_SYS_POST_CPU | \
204 CONFIG_SYS_POST_UART | \
205 CONFIG_SYS_POST_SPR )
wdenk7aa78612003-05-03 15:50:43 +0000206
Jon Loeliger60a08762007-07-07 21:04:26 -0500207
wdenk5b1d7132002-11-03 00:07:02 +0000208/*
Jon Loeliger60a08762007-07-07 21:04:26 -0500209 * Command line configuration.
wdenk5b1d7132002-11-03 00:07:02 +0000210 */
Jon Loeliger60a08762007-07-07 21:04:26 -0500211#include <config_cmd_default.h>
212
213#define CONFIG_CMD_ASKENV
214#define CONFIG_CMD_DHCP
215#define CONFIG_CMD_I2C
216#define CONFIG_CMD_EEPROM
217#define CONFIG_CMD_REGINFO
218#define CONFIG_CMD_IMMAP
219#define CONFIG_CMD_ELF
220#define CONFIG_CMD_DATE
221#define CONFIG_CMD_FPGA
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530222#define CONFIG_CMD_FPGA_LOADMK
Jon Loeliger60a08762007-07-07 21:04:26 -0500223#define CONFIG_CMD_MII
224#define CONFIG_CMD_BEDBUG
wdenk7aa78612003-05-03 15:50:43 +0000225
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500226#ifdef CONFIG_POST
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200227#define CONFIG_CMD_DIAG
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500228#endif
Jon Loeliger60a08762007-07-07 21:04:26 -0500229
wdenk5b1d7132002-11-03 00:07:02 +0000230/*
231 * There is no IDE/PCMCIA hardware support on the board.
232 */
233#undef CONFIG_IDE_PCMCIA
234#undef CONFIG_IDE_LED
235#undef CONFIG_IDE_RESET
236
237/*
238 * Enable the call to misc_init_r() for miscellaneous platform
239 * dependent initialization.
240 */
241#define CONFIG_MISC_INIT_R
242
243/*
244 * Enable call to last_stage_init() so we can twiddle some LEDS :)
245 */
246#define CONFIG_LAST_STAGE_INIT
247
248/*
249 * Virtex2 FPGA configuration support
250 */
251#define CONFIG_FPGA_COUNT 1
Matthias Fuchs01335022007-12-27 17:12:34 +0100252#define CONFIG_FPGA
253#define CONFIG_FPGA_XILINX
254#define CONFIG_FPGA_VIRTEX2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_FPGA_PROG_FEEDBACK
wdenk5b1d7132002-11-03 00:07:02 +0000256
wdenk5b1d7132002-11-03 00:07:02 +0000257/*
258 * Verbose help from command monitor.
259 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_LONGHELP
wdenk7aa78612003-05-03 15:50:43 +0000261#if !defined(CONFIG_SC)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_PROMPT "B2> "
wdenk7aa78612003-05-03 15:50:43 +0000263#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_PROMPT "SC> "
wdenk7aa78612003-05-03 15:50:43 +0000265#endif
266
wdenk5b1d7132002-11-03 00:07:02 +0000267
268/*
269 * Use the "hush" command parser
270 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_HUSH_PARSER
wdenk5b1d7132002-11-03 00:07:02 +0000272
273/*
274 * Set buffer size for console I/O
275 */
Jon Loeliger60a08762007-07-07 21:04:26 -0500276#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_CBSIZE 1024
wdenk5b1d7132002-11-03 00:07:02 +0000278#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_CBSIZE 256
wdenk5b1d7132002-11-03 00:07:02 +0000280#endif
281
282/*
283 * Print buffer size
284 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
wdenk5b1d7132002-11-03 00:07:02 +0000286
287/*
288 * Maximum number of arguments that a command can accept
289 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_MAXARGS 16
wdenk5b1d7132002-11-03 00:07:02 +0000291
292/*
293 * Boot argument buffer size
294 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
wdenk5b1d7132002-11-03 00:07:02 +0000296
297/*
298 * Default memory test range
299 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_MEMTEST_START 0x0100000
301#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (128 * 1024))
wdenk5b1d7132002-11-03 00:07:02 +0000302
303/*
304 * Select the more full-featured memory test
305 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_ALT_MEMTEST
wdenk5b1d7132002-11-03 00:07:02 +0000307
308/*
309 * Default load address
310 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_LOAD_ADDR 0x01000000
wdenk5b1d7132002-11-03 00:07:02 +0000312
313/*
wdenk5b1d7132002-11-03 00:07:02 +0000314 * Device memory map (after SDRAM remap to 0x0):
315 *
316 * CS Device Base Addr Size
317 * ----------------------------------------------------
318 * CS0* Flash 0x40000000 64 M
319 * CS1* SDRAM 0x00000000 16 M
320 * CS2* Disk-On-Chip 0x50000000 32 K
321 * CS3* FPGA 0x60000000 64 M
322 * CS4* SelectMap 0x70000000 32 K
323 * CS5* Mil-Std 1553 I/F 0x80000000 32 K
324 * CS6* Unused
325 * CS7* Unused
326 * IMMR 860T Registers 0xfff00000
327 */
328
329/*
330 * Base addresses and block sizes
331 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_IMMR 0xFF000000
wdenk5b1d7132002-11-03 00:07:02 +0000333
334#define SDRAM_BASE 0x00000000
335#define SDRAM_SIZE (64 * 1024 * 1024)
336
337#define FLASH_BASE 0x40000000
338#define FLASH_SIZE (16 * 1024 * 1024)
339
340#define DOC_BASE 0x50000000
341#define DOC_SIZE (32 * 1024)
342
343#define FPGA_BASE 0x60000000
344#define FPGA_SIZE (64 * 1024 * 1024)
345
346#define SELECTMAP_BASE 0x70000000
347#define SELECTMAP_SIZE (32 * 1024)
348
349#define M1553_BASE 0x80000000
350#define M1553_SIZE (64 * 1024)
351
352/*
353 * Definitions for initial stack pointer and data area (in DPRAM)
354 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200356#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/
Wolfgang Denk553f0982010-10-26 13:32:32 +0200358#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk5b1d7132002-11-03 00:07:02 +0000360
361/*
362 * Start addresses for the final memory configuration
363 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk5b1d7132002-11-03 00:07:02 +0000365 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_SDRAM_BASE SDRAM_BASE
wdenk5b1d7132002-11-03 00:07:02 +0000367
368/*
369 * FLASH organization
370 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_FLASH_BASE FLASH_BASE
372#define CONFIG_SYS_FLASH_SIZE FLASH_SIZE
373#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
374#define CONFIG_SYS_MAX_FLASH_BANKS 1
375#define CONFIG_SYS_MAX_FLASH_SECT 128
wdenk5b1d7132002-11-03 00:07:02 +0000376
377/*
378 * The timeout values are for an entire chip and are in milliseconds.
379 * Yes I know that the write timeout is huge. Accroding to the
380 * datasheet a single byte takes 630 uS (round to 1 ms) max at worst
381 * case VCC and temp after 100K programming cycles. It works out
382 * to 280 minutes (might as well be forever).
383 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_FLASH_ERASE_TOUT (CONFIG_SYS_MAX_FLASH_SECT * 5000)
385#define CONFIG_SYS_FLASH_WRITE_TOUT (CONFIG_SYS_MAX_FLASH_SECT * 128 * 1024 * 1)
wdenk5b1d7132002-11-03 00:07:02 +0000386
387/*
388 * Allow direct writes to FLASH from tftp transfers (** dangerous **)
389 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_DIRECT_FLASH_TFTP
wdenk5b1d7132002-11-03 00:07:02 +0000391
392/*
393 * Reserve memory for U-Boot.
394 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_MAX_UBOOT_SECTS 4
396#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_MAX_UBOOT_SECTS * CONFIG_SYS_FLASH_SECT_SIZE)
397#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
wdenk5b1d7132002-11-03 00:07:02 +0000398
399/*
400 * Select environment placement. NOTE that u-boot.lds must
401 * be edited if this is changed!
402 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200403#undef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200404#define CONFIG_ENV_IS_IN_EEPROM
wdenk5b1d7132002-11-03 00:07:02 +0000405
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200406#if defined(CONFIG_ENV_IS_IN_EEPROM)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200407#define CONFIG_ENV_SIZE (2 * 1024)
408#define CONFIG_ENV_OFFSET (CONFIG_ENV_EEPROM_SIZE - (8 * 1024))
wdenk5b1d7132002-11-03 00:07:02 +0000409#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200410#define CONFIG_ENV_SIZE 0x1000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE
wdenk7aa78612003-05-03 15:50:43 +0000412
413/*
414 * This ultimately gets passed right into the linker script, so we have to
415 * use a number :(
416 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200417#define CONFIG_ENV_OFFSET 0x060000
wdenk5b1d7132002-11-03 00:07:02 +0000418#endif
419
420/*
421 * Reserve memory for malloc()
422 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
wdenk5b1d7132002-11-03 00:07:02 +0000424
425/*
426 * For booting Linux, the board info and command line data
427 * have to be in the first 8 MB of memory, since this is
428 * the maximum mapped by the Linux kernel during initialization.
429 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200430#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
wdenk5b1d7132002-11-03 00:07:02 +0000431
432/*
433 * Cache Configuration
434 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger60a08762007-07-07 21:04:26 -0500436#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of above value */
wdenk5b1d7132002-11-03 00:07:02 +0000438#endif
439
440/*------------------------------------------------------------------------
wdenk7aa78612003-05-03 15:50:43 +0000441 * SYPCR - System Protection Control UM 11-9
wdenk5b1d7132002-11-03 00:07:02 +0000442 * -----------------------------------------------------------------------
443 * SYPCR can only be written once after reset!
444 *
445 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
446 */
447#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448#define CONFIG_SYS_SYPCR ( SYPCR_SWTC | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200449 SYPCR_BMT | \
450 SYPCR_BME | \
451 SYPCR_SWF | \
452 SYPCR_SWE | \
wdenk5b1d7132002-11-03 00:07:02 +0000453 SYPCR_SWRI | \
454 SYPCR_SWP \
455 )
456#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457#define CONFIG_SYS_SYPCR ( SYPCR_SWTC | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200458 SYPCR_BMT | \
459 SYPCR_BME | \
460 SYPCR_SWF | \
wdenk5b1d7132002-11-03 00:07:02 +0000461 SYPCR_SWP \
462 )
463#endif
464
465/*-----------------------------------------------------------------------
466 * SIUMCR - SIU Module Configuration UM 11-6
467 *-----------------------------------------------------------------------
468 * Set debug pin mux, enable SPKROUT and GPLB5*.
469 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#define CONFIG_SYS_SIUMCR ( SIUMCR_DBGC11 | \
wdenk5b1d7132002-11-03 00:07:02 +0000471 SIUMCR_DBPC11 | \
472 SIUMCR_MLRC11 | \
473 SIUMCR_GB5E \
474 )
475
476/*-----------------------------------------------------------------------
477 * TBSCR - Time Base Status and Control UM 11-26
478 *-----------------------------------------------------------------------
479 * Clear Reference Interrupt Status, Timebase freeze enabled
480 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200481#define CONFIG_SYS_TBSCR ( TBSCR_REFA | \
wdenk5b1d7132002-11-03 00:07:02 +0000482 TBSCR_REFB | \
483 TBSCR_TBF \
484 )
485
486/*-----------------------------------------------------------------------
487 * RTCSC - Real-Time Clock Status and Control Register UM 11-27
488 *-----------------------------------------------------------------------
489 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200490#define CONFIG_SYS_RTCSC ( RTCSC_SEC | \
wdenk5b1d7132002-11-03 00:07:02 +0000491 RTCSC_ALR | \
492 RTCSC_RTF | \
493 RTCSC_RTE \
494 )
495
496/*-----------------------------------------------------------------------
497 * PISCR - Periodic Interrupt Status and Control UM 11-31
498 *-----------------------------------------------------------------------
499 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
500 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200501#define CONFIG_SYS_PISCR ( PISCR_PS | \
wdenk5b1d7132002-11-03 00:07:02 +0000502 PISCR_PITF \
503 )
504
505/*-----------------------------------------------------------------------
506 * PLPRCR - PLL, Low-Power, and Reset Control Register UM 15-30
507 *-----------------------------------------------------------------------
508 * Reset PLL lock status sticky bit, timer expired status bit and timer
509 * interrupt status bit. Set MF for 1:2:1 mode.
510 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200511#define CONFIG_SYS_PLPRCR ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK) | \
wdenk5b1d7132002-11-03 00:07:02 +0000512 PLPRCR_SPLSS | \
513 PLPRCR_TEXPS | \
514 PLPRCR_TMIST \
515 )
516
517/*-----------------------------------------------------------------------
518 * SCCR - System Clock and reset Control Register UM 15-27
519 *-----------------------------------------------------------------------
520 * Set clock output, timebase and RTC source and divider,
521 * power management and some other internal clocks
522 */
523#define SCCR_MASK SCCR_EBDF11
524
wdenk7aa78612003-05-03 15:50:43 +0000525#if !defined(CONFIG_SC)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200526#define CONFIG_SYS_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200527 SCCR_COM00 | /* full strength CLKOUT */ \
528 SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
529 SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
wdenk5b1d7132002-11-03 00:07:02 +0000530 SCCR_DFNL000 | \
531 SCCR_DFNH000 \
532 )
wdenk7aa78612003-05-03 15:50:43 +0000533#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200534#define CONFIG_SYS_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200535 SCCR_COM00 | /* full strength CLKOUT */ \
536 SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
537 SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
wdenk7aa78612003-05-03 15:50:43 +0000538 SCCR_DFNL000 | \
539 SCCR_DFNH000 | \
540 SCCR_RTDIV | \
541 SCCR_RTSEL \
542 )
543#endif
wdenk5b1d7132002-11-03 00:07:02 +0000544
545/*-----------------------------------------------------------------------
546 * DER - Debug Enable Register UM 37-46
547 *-----------------------------------------------------------------------
548 * Mask all events that can cause entry into debug mode
549 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200550#define CONFIG_SYS_DER 0
wdenk5b1d7132002-11-03 00:07:02 +0000551
552/*
553 * Initialize Memory Controller:
554 *
555 * BR0 and OR0 (FLASH memory)
556 */
557#define FLASH_BASE0_PRELIM FLASH_BASE
558
559/*
560 * Flash address mask
561 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200562#define CONFIG_SYS_PRELIM_OR_AM 0xfe000000
wdenk5b1d7132002-11-03 00:07:02 +0000563
564/*
565 * FLASH timing:
566 * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
567 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200568#define CONFIG_SYS_OR_TIMING_FLASH ( OR_CSNT_SAM | \
wdenk5b1d7132002-11-03 00:07:02 +0000569 OR_ACS_DIV2 | \
570 OR_BI | \
571 OR_SCY_2_CLK | \
572 OR_TRLX | \
573 OR_EHTR \
574 )
575
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200576#define CONFIG_SYS_OR0_PRELIM ( CONFIG_SYS_PRELIM_OR_AM | \
577 CONFIG_SYS_OR_TIMING_FLASH \
wdenk5b1d7132002-11-03 00:07:02 +0000578 )
579
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200580#define CONFIG_SYS_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \
wdenk5b1d7132002-11-03 00:07:02 +0000581 BR_MS_GPCM | \
582 BR_PS_8 | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200583 BR_V \
wdenk5b1d7132002-11-03 00:07:02 +0000584 )
585
586/*
587 * SDRAM configuration
588 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200589#define CONFIG_SYS_OR1_AM 0xfc000000
590#define CONFIG_SYS_OR1 ( (CONFIG_SYS_OR1_AM & OR_AM_MSK) | \
wdenk5b1d7132002-11-03 00:07:02 +0000591 OR_CSNT_SAM \
592 )
593
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200594#define CONFIG_SYS_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200595 BR_MS_UPMA | \
596 BR_PS_32 | \
597 BR_V \
wdenk5b1d7132002-11-03 00:07:02 +0000598 )
599
600/*
601 * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
602 * of 256 MBit SDRAM
603 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200604#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16
wdenk5b1d7132002-11-03 00:07:02 +0000605
606/*
607 * Periodic timer for refresh @ 33 MHz system clock
608 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200609#define CONFIG_SYS_MAMR_PTA 64
wdenk5b1d7132002-11-03 00:07:02 +0000610
611/*
612 * MAMR settings for SDRAM
613 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200614#define CONFIG_SYS_MAMR_8COL ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200615 MAMR_PTAE | \
wdenk5b1d7132002-11-03 00:07:02 +0000616 MAMR_AMA_TYPE_1 | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200617 MAMR_DSA_1_CYCL | \
wdenk5b1d7132002-11-03 00:07:02 +0000618 MAMR_G0CLA_A10 | \
619 MAMR_RLFA_1X | \
620 MAMR_WLFA_1X | \
621 MAMR_TLFA_4X \
622 )
623
624/*
625 * CS2* configuration for Disk On Chip:
626 * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
627 * no burst.
628 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200629#define CONFIG_SYS_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
wdenk5b1d7132002-11-03 00:07:02 +0000630 OR_CSNT_SAM | \
631 OR_ACS_DIV2 | \
632 OR_BI | \
633 OR_SCY_2_CLK | \
634 OR_TRLX | \
635 OR_EHTR \
636 )
637
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200638#define CONFIG_SYS_BR2_PRELIM ( (DOC_BASE & BR_BA_MSK) | \
wdenk5b1d7132002-11-03 00:07:02 +0000639 BR_PS_8 | \
640 BR_MS_GPCM | \
641 BR_V \
642 )
643
644/*
645 * CS3* configuration for FPGA:
646 * 33 MHz bus with SCY=15, no burst.
647 * The FPGA uses TA and TEA to terminate bus cycles, but we
648 * clear SETA and set the cycle length to a large number so that
649 * the cycle will still complete even if there is a configuration
650 * error that prevents TA from asserting on FPGA accesss.
651 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200652#define CONFIG_SYS_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \
wdenk5b1d7132002-11-03 00:07:02 +0000653 OR_SCY_15_CLK | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200654 OR_BI \
wdenk5b1d7132002-11-03 00:07:02 +0000655 )
656
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200657#define CONFIG_SYS_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \
wdenk5b1d7132002-11-03 00:07:02 +0000658 BR_PS_32 | \
659 BR_MS_GPCM | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200660 BR_V \
wdenk5b1d7132002-11-03 00:07:02 +0000661 )
662/*
663 * CS4* configuration for FPGA SelectMap configuration interface.
664 * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
665 * of GCLK1_50
666 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200667#define CONFIG_SYS_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
wdenk5b1d7132002-11-03 00:07:02 +0000668 OR_G5LS | \
669 OR_BI \
670 )
671
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200672#define CONFIG_SYS_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \
wdenk5b1d7132002-11-03 00:07:02 +0000673 BR_PS_8 | \
674 BR_MS_UPMB | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200675 BR_V \
wdenk5b1d7132002-11-03 00:07:02 +0000676 )
677
678/*
679 * CS5* configuration for Mil-Std 1553 databus interface.
680 * 33 MHz bus, GPCM, no burst.
681 * The 1553 interface uses TA and TEA to terminate bus cycles,
682 * but we clear SETA and set the cycle length to a large number so that
683 * the cycle will still complete even if there is a configuration
684 * error that prevents TA from asserting on FPGA accesss.
685 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200686#define CONFIG_SYS_OR5_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
wdenk5b1d7132002-11-03 00:07:02 +0000687 OR_SCY_15_CLK | \
688 OR_EHTR | \
689 OR_TRLX | \
690 OR_CSNT_SAM | \
691 OR_BI \
692 )
693
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200694#define CONFIG_SYS_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \
wdenk5b1d7132002-11-03 00:07:02 +0000695 BR_PS_16 | \
696 BR_MS_GPCM | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200697 BR_V \
wdenk5b1d7132002-11-03 00:07:02 +0000698 )
699
700/*
wdenk5b1d7132002-11-03 00:07:02 +0000701 * FEC interrupt assignment
702 */
703#define FEC_INTERRUPT SIU_LEVEL1
704
705/*
706 * Sanity checks
707 */
708#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
709#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
710#endif
711
712#endif /* __CONFIG_GEN860T_H */