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Ian Campbell2c7e3b92014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Hans de Goede44d8ae52015-04-06 20:33:34 +02003# Note only one of these may be selected at a time! But hidden choices are
4# not supported by Kconfig
5config SUNXI_GEN_SUN4I
6 bool
7 ---help---
8 Select this for sunxi SoCs which have resets and clocks set up
9 as the original A10 (mach-sun4i).
10
11config SUNXI_GEN_SUN6I
12 bool
13 ---help---
14 Select this for sunxi SoCs which have sun6i like periphery, like
15 separate ahb reset control registers, custom pmic bus, new style
16 watchdog, etc.
17
18
Ian Campbell2c7e3b92014-10-24 21:20:44 +010019choice
20 prompt "Sunxi SoC Variant"
Joe Hershbergera26cd042015-05-12 14:46:23 -050021 optional
Ian Campbell2c7e3b92014-10-24 21:20:44 +010022
Ian Campbellc3be2792014-10-24 21:20:45 +010023config MACH_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010024 bool "sun4i (Allwinner A10)"
25 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020026 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010027 select SUPPORT_SPL
28
Ian Campbellc3be2792014-10-24 21:20:45 +010029config MACH_SUN5I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010030 bool "sun5i (Allwinner A13)"
31 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020032 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010033 select SUPPORT_SPL
34
Ian Campbellc3be2792014-10-24 21:20:45 +010035config MACH_SUN6I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010036 bool "sun6i (Allwinner A31)"
37 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020038 select SUNXI_GEN_SUN6I
Hans de Goede8c2c9cf2014-10-25 20:18:10 +020039 select SUPPORT_SPL
Ian Campbell2c7e3b92014-10-24 21:20:44 +010040
Ian Campbellc3be2792014-10-24 21:20:45 +010041config MACH_SUN7I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010042 bool "sun7i (Allwinner A20)"
43 select CPU_V7
Hans de Goedeea624e12014-11-14 09:34:30 +010044 select CPU_V7_HAS_NONSEC
45 select CPU_V7_HAS_VIRT
Hans de Goede44d8ae52015-04-06 20:33:34 +020046 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010047 select SUPPORT_SPL
Hans de Goedeb366fb92014-10-24 20:12:04 +020048 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010049
Hans de Goede5e6bacd2015-04-06 20:55:39 +020050config MACH_SUN8I_A23
Ian Campbell2c7e3b92014-10-24 21:20:44 +010051 bool "sun8i (Allwinner A23)"
52 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020053 select SUNXI_GEN_SUN6I
Hans de Goede08fd1472014-12-07 14:34:27 +010054 select SUPPORT_SPL
Ian Campbell2c7e3b92014-10-24 21:20:44 +010055
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053056config MACH_SUN8I_A33
57 bool "sun8i (Allwinner A33)"
58 select CPU_V7
59 select SUNXI_GEN_SUN6I
60 select SUPPORT_SPL
61
Ian Campbell2c7e3b92014-10-24 21:20:44 +010062endchoice
Maxime Ripard8a6564d2014-10-03 20:16:29 +080063
Hans de Goede5e6bacd2015-04-06 20:55:39 +020064# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
65config MACH_SUN8I
66 bool
67 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33
68
69
Hans de Goede37781a12014-11-15 19:46:39 +010070config DRAM_CLK
Hans de Goede8ffc4872015-01-17 14:24:55 +010071 int "sunxi dram clock speed"
72 default 312 if MACH_SUN6I || MACH_SUN8I
73 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +010074 ---help---
75 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goedee1a08882015-01-25 11:29:27 +010076 of 24.
Hans de Goede37781a12014-11-15 19:46:39 +010077
Siarhei Siamashka47e35012015-02-01 00:27:06 +020078if MACH_SUN5I || MACH_SUN7I
79config DRAM_MBUS_CLK
80 int "sunxi mbus clock speed"
81 default 300
82 ---help---
83 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
84
85endif
86
Hans de Goede37781a12014-11-15 19:46:39 +010087config DRAM_ZQ
Hans de Goede8ffc4872015-01-17 14:24:55 +010088 int "sunxi dram zq value"
89 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
90 default 127 if MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +010091 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +010092 Set the dram zq value.
Hans de Goede37781a12014-11-15 19:46:39 +010093
Hans de Goede8ffc4872015-01-17 14:24:55 +010094if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
95config DRAM_EMR1
96 int "sunxi dram emr1 value"
97 default 0 if MACH_SUN4I
98 default 4 if MACH_SUN5I || MACH_SUN7I
99 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100100 Set the dram controller emr1 value.
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200101
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200102config DRAM_ODT_EN
103 int "sunxi dram odt_en value"
104 default 0
105 ---help---
106 Set the dram controller odt_en parameter. This can be used to
107 enable/disable the ODT feature.
108
109config DRAM_TPR3
110 hex "sunxi dram tpr3 value"
111 default 0
112 ---help---
113 Set the dram controller tpr3 parameter. This parameter configures
114 the delay on the command lane and also phase shifts, which are
115 applied for sampling incoming read data. The default value 0
116 means that no phase/delay adjustments are necessary. Properly
117 configuring this parameter increases reliability at high DRAM
118 clock speeds.
119
120config DRAM_DQS_GATING_DELAY
121 hex "sunxi dram dqs_gating_delay value"
122 default 0
123 ---help---
124 Set the dram controller dqs_gating_delay parmeter. Each byte
125 encodes the DQS gating delay for each byte lane. The delay
126 granularity is 1/4 cycle. For example, the value 0x05060606
127 means that the delay is 5 quarter-cycles for one lane (1.25
128 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
129 The default value 0 means autodetection. The results of hardware
130 autodetection are not very reliable and depend on the chip
131 temperature (sometimes producing different results on cold start
132 and warm reboot). But the accuracy of hardware autodetection
133 is usually good enough, unless running at really high DRAM
134 clocks speeds (up to 600MHz). If unsure, keep as 0.
135
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200136choice
137 prompt "sunxi dram timings"
138 default DRAM_TIMINGS_VENDOR_MAGIC
139 ---help---
140 Select the timings of the DDR3 chips.
141
142config DRAM_TIMINGS_VENDOR_MAGIC
143 bool "Magic vendor timings from Android"
144 ---help---
145 The same DRAM timings as in the Allwinner boot0 bootloader.
146
147config DRAM_TIMINGS_DDR3_1066F_1333H
148 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
149 ---help---
150 Use the timings of the standard JEDEC DDR3-1066F speed bin for
151 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
152 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
153 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
154 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
155 that down binning to DDR3-1066F is supported (because DDR3-1066F
156 uses a bit faster timings than DDR3-1333H).
157
158config DRAM_TIMINGS_DDR3_800E_1066G_1333J
159 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
160 ---help---
161 Use the timings of the slowest possible JEDEC speed bin for the
162 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
163 DDR3-800E, DDR3-1066G or DDR3-1333J.
164
165endchoice
166
Hans de Goede37781a12014-11-15 19:46:39 +0100167endif
168
Iain Patone71b4222015-03-28 10:26:38 +0000169config SYS_CLK_FREQ
170 default 912000000 if MACH_SUN7I
171 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
172
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800173config SYS_CONFIG_NAME
Ian Campbellc3be2792014-10-24 21:20:45 +0100174 default "sun4i" if MACH_SUN4I
175 default "sun5i" if MACH_SUN5I
176 default "sun6i" if MACH_SUN6I
177 default "sun7i" if MACH_SUN7I
178 default "sun8i" if MACH_SUN8I
Hans de Goede6ae66f22014-08-01 09:28:24 +0200179
Masahiro Yamadadd840582014-07-30 14:08:14 +0900180config SYS_BOARD
Masahiro Yamadadd840582014-07-30 14:08:14 +0900181 default "sunxi"
182
183config SYS_SOC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900184 default "sunxi"
185
Ian Campbell4ce99412014-10-24 21:20:46 +0100186config SPL_FEL
187 bool "SPL/FEL mode support"
188 depends on SPL
189 default n
Simon Glass942cb0b2015-02-07 10:47:30 -0700190 help
191 This enables support for Fast Early Loader (FEL) mode. This
192 allows U-Boot to be loaded to the board over USB by the on-chip
193 boot rom. U-Boot should be sent in two parts: SPL first, with
194 'fel write 0x2000 u-boot-spl.bin; fel exe 0x2000' then U-Boot with
195 'fel write 0x4a000000 u-boot.bin; fel exe 0x4a000000'. This option
196 shrinks the amount of SRAM available to SPL, so only enable it if
197 you need FEL. Note that enabling this option only allows FEL to be
198 used; it is still possible to boot U-Boot from boot media. U-Boot
199 SPL detects when it is being loaded using FEL.
Ian Campbell4ce99412014-10-24 21:20:46 +0100200
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200201config UART0_PORT_F
202 bool "UART0 on MicroSD breakout board"
203 depends on SPL_FEL
204 default n
205 ---help---
206 Repurpose the SD card slot for getting access to the UART0 serial
207 console. Primarily useful only for low level u-boot debugging on
208 tablets, where normal UART0 is difficult to access and requires
209 device disassembly and/or soldering. As the SD card can't be used
210 at the same time, the system can be only booted in the FEL mode.
211 Only enable this if you really know what you are doing.
212
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200213config OLD_SUNXI_KERNEL_COMPAT
214 boolean "Enable workarounds for booting old kernels"
215 default n
216 ---help---
217 Set this to enable various workarounds for old kernels, this results in
218 sub-optimal settings for newer kernels, only enable if needed.
219
Hans de Goedecd821132014-10-02 20:29:26 +0200220config MMC0_CD_PIN
221 string "Card detect pin for mmc0"
222 default ""
223 ---help---
224 Set the card detect pin for mmc0, leave empty to not use cd. This
225 takes a string in the format understood by sunxi_name_to_gpio, e.g.
226 PH1 for pin 1 of port H.
227
228config MMC1_CD_PIN
229 string "Card detect pin for mmc1"
230 default ""
231 ---help---
232 See MMC0_CD_PIN help text.
233
234config MMC2_CD_PIN
235 string "Card detect pin for mmc2"
236 default ""
237 ---help---
238 See MMC0_CD_PIN help text.
239
240config MMC3_CD_PIN
241 string "Card detect pin for mmc3"
242 default ""
243 ---help---
244 See MMC0_CD_PIN help text.
245
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100246config MMC1_PINS
247 string "Pins for mmc1"
248 default ""
249 ---help---
250 Set the pins used for mmc1, when applicable. This takes a string in the
251 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
252
253config MMC2_PINS
254 string "Pins for mmc2"
255 default ""
256 ---help---
257 See MMC1_PINS help text.
258
259config MMC3_PINS
260 string "Pins for mmc3"
261 default ""
262 ---help---
263 See MMC1_PINS help text.
264
Hans de Goede2ccfac02014-10-02 20:43:50 +0200265config MMC_SUNXI_SLOT_EXTRA
266 int "mmc extra slot number"
267 default -1
268 ---help---
269 sunxi builds always enable mmc0, some boards also have a second sdcard
270 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
271 support for this.
272
Hans de Goede4458b7a2015-01-07 15:26:06 +0100273config USB0_VBUS_PIN
274 string "Vbus enable pin for usb0 (otg)"
275 default ""
276 ---help---
277 Set the Vbus enable pin for usb0 (otg). This takes a string in the
278 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
279
Hans de Goede52defe82015-02-16 22:13:43 +0100280config USB0_VBUS_DET
281 string "Vbus detect pin for usb0 (otg)"
Hans de Goede52defe82015-02-16 22:13:43 +0100282 default ""
283 ---help---
284 Set the Vbus detect pin for usb0 (otg). This takes a string in the
285 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
286
Hans de Goede115200c2014-11-07 16:09:00 +0100287config USB1_VBUS_PIN
288 string "Vbus enable pin for usb1 (ehci0)"
289 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100290 default "PH27" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100291 ---help---
292 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
293 a string in the format understood by sunxi_name_to_gpio, e.g.
294 PH1 for pin 1 of port H.
295
296config USB2_VBUS_PIN
297 string "Vbus enable pin for usb2 (ehci1)"
298 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100299 default "PH24" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100300 ---help---
301 See USB1_VBUS_PIN help text.
302
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200303config I2C0_ENABLE
304 bool "Enable I2C/TWI controller 0"
305 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
306 default n if MACH_SUN6I || MACH_SUN8I
307 ---help---
308 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
309 its clock and setting up the bus. This is especially useful on devices
310 with slaves connected to the bus or with pins exposed through e.g. an
311 expansion port/header.
312
313config I2C1_ENABLE
314 bool "Enable I2C/TWI controller 1"
315 default n
316 ---help---
317 See I2C0_ENABLE help text.
318
319config I2C2_ENABLE
320 bool "Enable I2C/TWI controller 2"
321 default n
322 ---help---
323 See I2C0_ENABLE help text.
324
325if MACH_SUN6I || MACH_SUN7I
326config I2C3_ENABLE
327 bool "Enable I2C/TWI controller 3"
328 default n
329 ---help---
330 See I2C0_ENABLE help text.
331endif
332
333if MACH_SUN7I
334config I2C4_ENABLE
335 bool "Enable I2C/TWI controller 4"
336 default n
337 ---help---
338 See I2C0_ENABLE help text.
339endif
340
Hans de Goede2fcf0332015-04-25 17:25:14 +0200341config AXP_GPIO
342 boolean "Enable support for gpio-s on axp PMICs"
343 default n
344 ---help---
345 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
346
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200347config VIDEO
Hans de Goede2dae8002014-12-21 16:28:32 +0100348 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200349 default y
350 ---help---
Hans de Goede2dae8002014-12-21 16:28:32 +0100351 Say Y here to add support for using a cfb console on the HDMI, LCD
352 or VGA output found on most sunxi devices. See doc/README.video for
353 info on how to select the video output and mode.
354
Hans de Goede2fbf0912014-12-23 23:04:35 +0100355config VIDEO_HDMI
356 boolean "HDMI output support"
357 depends on VIDEO && !MACH_SUN8I
358 default y
359 ---help---
360 Say Y here to add support for outputting video over HDMI.
361
Hans de Goeded9786d22014-12-25 13:58:06 +0100362config VIDEO_VGA
363 boolean "VGA output support"
364 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
365 default n
366 ---help---
367 Say Y here to add support for outputting video over VGA.
368
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100369config VIDEO_VGA_VIA_LCD
370 boolean "VGA via LCD controller support"
Chen-Yu Tsai2583d5b2015-01-12 18:02:10 +0800371 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100372 default n
373 ---help---
374 Say Y here to add support for external DACs connected to the parallel
375 LCD interface driving a VGA connector, such as found on the
376 Olimex A13 boards.
377
Hans de Goedefb75d972015-01-25 15:33:07 +0100378config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
379 boolean "Force sync active high for VGA via LCD controller support"
380 depends on VIDEO_VGA_VIA_LCD
381 default n
382 ---help---
383 Say Y here if you've a board which uses opendrain drivers for the vga
384 hsync and vsync signals. Opendrain drivers cannot generate steep enough
385 positive edges for a stable video output, so on boards with opendrain
386 drivers the sync signals must always be active high.
387
Chen-Yu Tsai507e27d2015-01-12 18:02:11 +0800388config VIDEO_VGA_EXTERNAL_DAC_EN
389 string "LCD panel power enable pin"
390 depends on VIDEO_VGA_VIA_LCD
391 default ""
392 ---help---
393 Set the enable pin for the external VGA DAC. This takes a string in the
394 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
395
Hans de Goede2dae8002014-12-21 16:28:32 +0100396config VIDEO_LCD_MODE
397 string "LCD panel timing details"
398 depends on VIDEO
399 default ""
400 ---help---
401 LCD panel timing details string, leave empty if there is no LCD panel.
402 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
403 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
404
Hans de Goede65150322015-01-13 13:21:46 +0100405config VIDEO_LCD_DCLK_PHASE
406 int "LCD panel display clock phase"
407 depends on VIDEO
408 default 1
409 ---help---
410 Select LCD panel display clock phase shift, range 0-3.
411
Hans de Goede2dae8002014-12-21 16:28:32 +0100412config VIDEO_LCD_POWER
413 string "LCD panel power enable pin"
414 depends on VIDEO
415 default ""
416 ---help---
417 Set the power enable pin for the LCD panel. This takes a string in the
418 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
419
Hans de Goede242e3d82015-02-16 17:26:41 +0100420config VIDEO_LCD_RESET
421 string "LCD panel reset pin"
422 depends on VIDEO
423 default ""
424 ---help---
425 Set the reset pin for the LCD panel. This takes a string in the format
426 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
427
Hans de Goede2dae8002014-12-21 16:28:32 +0100428config VIDEO_LCD_BL_EN
429 string "LCD panel backlight enable pin"
430 depends on VIDEO
431 default ""
432 ---help---
433 Set the backlight enable pin for the LCD panel. This takes a string in the
434 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
435 port H.
436
437config VIDEO_LCD_BL_PWM
438 string "LCD panel backlight pwm pin"
439 depends on VIDEO
440 default ""
441 ---help---
442 Set the backlight pwm pin for the LCD panel. This takes a string in the
443 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200444
Hans de Goedea7403ae2015-01-22 21:02:42 +0100445config VIDEO_LCD_BL_PWM_ACTIVE_LOW
446 bool "LCD panel backlight pwm is inverted"
447 depends on VIDEO
448 default y
449 ---help---
450 Set this if the backlight pwm output is active low.
451
Hans de Goede55410082015-02-16 17:23:25 +0100452config VIDEO_LCD_PANEL_I2C
453 bool "LCD panel needs to be configured via i2c"
454 depends on VIDEO
Hans de Goede1fc42012015-03-07 12:00:02 +0100455 default n
Hans de Goede55410082015-02-16 17:23:25 +0100456 ---help---
457 Say y here if the LCD panel needs to be configured via i2c. This
458 will add a bitbang i2c controller using gpios to talk to the LCD.
459
460config VIDEO_LCD_PANEL_I2C_SDA
461 string "LCD panel i2c interface SDA pin"
462 depends on VIDEO_LCD_PANEL_I2C
463 default "PG12"
464 ---help---
465 Set the SDA pin for the LCD i2c interface. This takes a string in the
466 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
467
468config VIDEO_LCD_PANEL_I2C_SCL
469 string "LCD panel i2c interface SCL pin"
470 depends on VIDEO_LCD_PANEL_I2C
471 default "PG10"
472 ---help---
473 Set the SCL pin for the LCD i2c interface. This takes a string in the
474 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
475
Hans de Goede213480e2015-01-01 22:04:34 +0100476
477# Note only one of these may be selected at a time! But hidden choices are
478# not supported by Kconfig
479config VIDEO_LCD_IF_PARALLEL
480 bool
481
482config VIDEO_LCD_IF_LVDS
483 bool
484
485
486choice
487 prompt "LCD panel support"
488 depends on VIDEO
489 ---help---
490 Select which type of LCD panel to support.
491
492config VIDEO_LCD_PANEL_PARALLEL
493 bool "Generic parallel interface LCD panel"
494 select VIDEO_LCD_IF_PARALLEL
495
496config VIDEO_LCD_PANEL_LVDS
497 bool "Generic lvds interface LCD panel"
498 select VIDEO_LCD_IF_LVDS
499
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200500config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
501 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
502 select VIDEO_LCD_SSD2828
503 select VIDEO_LCD_IF_PARALLEL
504 ---help---
505 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
506
Hans de Goede27515b22015-01-20 09:23:36 +0100507config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
508 bool "Hitachi tx18d42vm LCD panel"
509 select VIDEO_LCD_HITACHI_TX18D42VM
510 select VIDEO_LCD_IF_LVDS
511 ---help---
512 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
513
Hans de Goedeaad2ac22015-02-16 17:49:47 +0100514config VIDEO_LCD_TL059WV5C0
515 bool "tl059wv5c0 LCD panel"
516 select VIDEO_LCD_PANEL_I2C
517 select VIDEO_LCD_IF_PARALLEL
518 ---help---
519 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
520 Aigo M60/M608/M606 tablets.
521
Hans de Goede213480e2015-01-01 22:04:34 +0100522endchoice
523
524
Hans de Goede1a800f72015-01-11 17:17:00 +0100525config USB_MUSB_SUNXI
526 bool "Enable sunxi OTG / DRC USB controller in host mode"
527 default n
528 ---help---
529 Say y here to enable support for the sunxi OTG / DRC USB controller
530 used on almost all sunxi boards. Note currently u-boot can only have
531 one usb host controller enabled at a time, so enabling this on boards
532 which also use the ehci host controller will result in build errors.
533
Hans de Goede86b49092014-09-18 21:03:34 +0200534config USB_KEYBOARD
535 boolean "Enable USB keyboard support"
536 default y
537 ---help---
538 Say Y here to add support for using a USB keyboard (typically used
Hans de Goede2dae8002014-12-21 16:28:32 +0100539 in combination with a graphical console).
Hans de Goede86b49092014-09-18 21:03:34 +0200540
Hans de Goedec13f60d2015-01-25 12:10:48 +0100541config GMAC_TX_DELAY
542 int "GMAC Transmit Clock Delay Chain"
543 default 0
544 ---help---
545 Set the GMAC Transmit Clock Delay Chain value.
546
Hans de Goedeb6006ba2015-04-15 20:46:48 +0200547config NET
548 default y
549
550config NETDEVICES
551 default y
552
553config DM_ETH
554 default y
555
556config DM_SERIAL
557 default y
558
Masahiro Yamadadd840582014-07-30 14:08:14 +0900559endif