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Prafulla Wadaskar91315892009-06-14 22:33:46 +05301/*
2 * (C) Copyright 2009
3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 *
6 * (C) Copyright 2003
7 * Ingo Assmus <ingo.assmus@keymile.com>
8 *
9 * based on - Driver for MV64360X ethernet ports
10 * Copyright (C) 2002 rabeeh@galileo.co.il
11 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020012 * SPDX-License-Identifier: GPL-2.0+
Prafulla Wadaskar91315892009-06-14 22:33:46 +053013 */
14
15#include <common.h>
16#include <net.h>
17#include <malloc.h>
18#include <miiphy.h>
Lei Wena7efd712011-10-18 20:11:42 +053019#include <asm/io.h>
Prafulla Wadaskar91315892009-06-14 22:33:46 +053020#include <asm/errno.h>
21#include <asm/types.h>
Lei Wena7efd712011-10-18 20:11:42 +053022#include <asm/system.h>
Prafulla Wadaskar91315892009-06-14 22:33:46 +053023#include <asm/byteorder.h>
Anatolij Gustschin36aaa912011-10-29 10:09:22 +000024#include <asm/arch/cpu.h>
Albert Aribaudd44265a2010-07-12 22:24:28 +020025
26#if defined(CONFIG_KIRKWOOD)
Stefan Roese3dc23f72014-10-22 12:13:06 +020027#include <asm/arch/soc.h>
Albert Aribaudd3c9ffd2010-07-12 22:24:29 +020028#elif defined(CONFIG_ORION5X)
29#include <asm/arch/orion5x.h>
Sebastian Hesselbarthfb4879b2012-12-04 09:32:01 +010030#elif defined(CONFIG_DOVE)
31#include <asm/arch/dove.h>
Albert Aribaudd44265a2010-07-12 22:24:28 +020032#endif
33
Albert Aribaud9b6bcdc2010-07-12 22:24:27 +020034#include "mvgbe.h"
Prafulla Wadaskar91315892009-06-14 22:33:46 +053035
Albert Aribaud49fa6ed2010-07-05 20:15:25 +020036DECLARE_GLOBAL_DATA_PTR;
37
Luka Perkov5aa22972013-11-11 07:27:53 +010038#ifndef CONFIG_MVGBE_PORTS
39# define CONFIG_MVGBE_PORTS {0, 0}
40#endif
41
Albert Aribaudd44265a2010-07-12 22:24:28 +020042#define MV_PHY_ADR_REQUEST 0xee
43#define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
Simon Kagstrombb1ca3b2009-08-20 10:12:28 +020044
Sebastian Hesselbarthcd3ca3f2012-12-04 09:32:00 +010045#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Prafulla Wadaskar91315892009-06-14 22:33:46 +053046/*
47 * smi_reg_read - miiphy_read callback function.
48 *
49 * Returns 16bit phy register value, or 0xffff on error
50 */
Mike Frysinger5700bb62010-07-27 18:35:08 -040051static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
Prafulla Wadaskar91315892009-06-14 22:33:46 +053052{
53 struct eth_device *dev = eth_get_dev_by_name(devname);
Albert Aribaudd44265a2010-07-12 22:24:28 +020054 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
55 struct mvgbe_registers *regs = dmvgbe->regs;
Prafulla Wadaskar91315892009-06-14 22:33:46 +053056 u32 smi_reg;
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +020057 u32 timeout;
Prafulla Wadaskar91315892009-06-14 22:33:46 +053058
59 /* Phyadr read request */
Albert Aribaudd44265a2010-07-12 22:24:28 +020060 if (phy_adr == MV_PHY_ADR_REQUEST &&
61 reg_ofs == MV_PHY_ADR_REQUEST) {
Prafulla Wadaskar91315892009-06-14 22:33:46 +053062 /* */
Albert Aribaudd44265a2010-07-12 22:24:28 +020063 *data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK);
Prafulla Wadaskar91315892009-06-14 22:33:46 +053064 return 0;
65 }
66 /* check parameters */
67 if (phy_adr > PHYADR_MASK) {
68 printf("Err..(%s) Invalid PHY address %d\n",
69 __FUNCTION__, phy_adr);
70 return -EFAULT;
71 }
72 if (reg_ofs > PHYREG_MASK) {
73 printf("Err..(%s) Invalid register offset %d\n",
74 __FUNCTION__, reg_ofs);
75 return -EFAULT;
76 }
77
Albert Aribaudd44265a2010-07-12 22:24:28 +020078 timeout = MVGBE_PHY_SMI_TIMEOUT;
Prafulla Wadaskar91315892009-06-14 22:33:46 +053079 /* wait till the SMI is not busy */
80 do {
81 /* read smi register */
Albert Aribaudd44265a2010-07-12 22:24:28 +020082 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
Prafulla Wadaskar91315892009-06-14 22:33:46 +053083 if (timeout-- == 0) {
84 printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
85 return -EFAULT;
86 }
Albert Aribaudd44265a2010-07-12 22:24:28 +020087 } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
Prafulla Wadaskar91315892009-06-14 22:33:46 +053088
89 /* fill the phy address and regiser offset and read opcode */
Albert Aribaudd44265a2010-07-12 22:24:28 +020090 smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
91 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS)
92 | MVGBE_PHY_SMI_OPCODE_READ;
Prafulla Wadaskar91315892009-06-14 22:33:46 +053093
94 /* write the smi register */
Albert Aribaudd44265a2010-07-12 22:24:28 +020095 MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
Prafulla Wadaskar91315892009-06-14 22:33:46 +053096
97 /*wait till read value is ready */
Albert Aribaudd44265a2010-07-12 22:24:28 +020098 timeout = MVGBE_PHY_SMI_TIMEOUT;
Prafulla Wadaskar91315892009-06-14 22:33:46 +053099
100 do {
101 /* read smi register */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200102 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530103 if (timeout-- == 0) {
104 printf("Err..(%s) SMI read ready timeout\n",
105 __FUNCTION__);
106 return -EFAULT;
107 }
Albert Aribaudd44265a2010-07-12 22:24:28 +0200108 } while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530109
110 /* Wait for the data to update in the SMI register */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200111 for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++)
112 ;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530113
Albert Aribaudd44265a2010-07-12 22:24:28 +0200114 *data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530115
116 debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
117 reg_ofs, *data);
118
119 return 0;
120}
121
122/*
123 * smi_reg_write - imiiphy_write callback function.
124 *
125 * Returns 0 if write succeed, -EINVAL on bad parameters
126 * -ETIME on timeout
127 */
Mike Frysinger5700bb62010-07-27 18:35:08 -0400128static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530129{
130 struct eth_device *dev = eth_get_dev_by_name(devname);
Albert Aribaudd44265a2010-07-12 22:24:28 +0200131 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
132 struct mvgbe_registers *regs = dmvgbe->regs;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530133 u32 smi_reg;
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200134 u32 timeout;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530135
136 /* Phyadr write request*/
Albert Aribaudd44265a2010-07-12 22:24:28 +0200137 if (phy_adr == MV_PHY_ADR_REQUEST &&
138 reg_ofs == MV_PHY_ADR_REQUEST) {
139 MVGBE_REG_WR(regs->phyadr, data);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530140 return 0;
141 }
142
143 /* check parameters */
144 if (phy_adr > PHYADR_MASK) {
145 printf("Err..(%s) Invalid phy address\n", __FUNCTION__);
146 return -EINVAL;
147 }
148 if (reg_ofs > PHYREG_MASK) {
149 printf("Err..(%s) Invalid register offset\n", __FUNCTION__);
150 return -EINVAL;
151 }
152
153 /* wait till the SMI is not busy */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200154 timeout = MVGBE_PHY_SMI_TIMEOUT;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530155 do {
156 /* read smi register */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200157 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530158 if (timeout-- == 0) {
159 printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
160 return -ETIME;
161 }
Albert Aribaudd44265a2010-07-12 22:24:28 +0200162 } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530163
164 /* fill the phy addr and reg offset and write opcode and data */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200165 smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS);
166 smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
167 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS);
168 smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530169
170 /* write the smi register */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200171 MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530172
173 return 0;
174}
Stefan Biglercc796972012-03-26 00:02:13 +0000175#endif
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530176
Sebastian Hesselbarthcd3ca3f2012-12-04 09:32:00 +0100177#if defined(CONFIG_PHYLIB)
178int mvgbe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
179 int reg_addr)
180{
181 u16 data;
182 int ret;
183 ret = smi_reg_read(bus->name, phy_addr, reg_addr, &data);
184 if (ret)
185 return ret;
186 return data;
187}
188
189int mvgbe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
190 int reg_addr, u16 data)
191{
192 return smi_reg_write(bus->name, phy_addr, reg_addr, data);
193}
194#endif
195
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530196/* Stop and checks all queues */
197static void stop_queue(u32 * qreg)
198{
199 u32 reg_data;
200
201 reg_data = readl(qreg);
202
203 if (reg_data & 0xFF) {
204 /* Issue stop command for active channels only */
205 writel((reg_data << 8), qreg);
206
207 /* Wait for all queue activity to terminate. */
208 do {
209 /*
210 * Check port cause register that all queues
211 * are stopped
212 */
213 reg_data = readl(qreg);
214 }
215 while (reg_data & 0xFF);
216 }
217}
218
219/*
220 * set_access_control - Config address decode parameters for Ethernet unit
221 *
222 * This function configures the address decode parameters for the Gigabit
223 * Ethernet Controller according the given parameters struct.
224 *
225 * @regs Register struct pointer.
226 * @param Address decode parameter struct.
227 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200228static void set_access_control(struct mvgbe_registers *regs,
229 struct mvgbe_winparam *param)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530230{
231 u32 access_prot_reg;
232
233 /* Set access control register */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200234 access_prot_reg = MVGBE_REG_RD(regs->epap);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530235 /* clear window permission */
236 access_prot_reg &= (~(3 << (param->win * 2)));
237 access_prot_reg |= (param->access_ctrl << (param->win * 2));
Albert Aribaudd44265a2010-07-12 22:24:28 +0200238 MVGBE_REG_WR(regs->epap, access_prot_reg);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530239
240 /* Set window Size reg (SR) */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200241 MVGBE_REG_WR(regs->barsz[param->win].size,
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530242 (((param->size / 0x10000) - 1) << 16));
243
244 /* Set window Base address reg (BA) */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200245 MVGBE_REG_WR(regs->barsz[param->win].bar,
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530246 (param->target | param->attrib | param->base_addr));
247 /* High address remap reg (HARR) */
248 if (param->win < 4)
Albert Aribaudd44265a2010-07-12 22:24:28 +0200249 MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530250
251 /* Base address enable reg (BARER) */
252 if (param->enable == 1)
Albert Aribaudd44265a2010-07-12 22:24:28 +0200253 MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530254 else
Albert Aribaudd44265a2010-07-12 22:24:28 +0200255 MVGBE_REG_BITS_SET(regs->bare, (1 << param->win));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530256}
257
Albert Aribaudd44265a2010-07-12 22:24:28 +0200258static void set_dram_access(struct mvgbe_registers *regs)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530259{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200260 struct mvgbe_winparam win_param;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530261 int i;
262
263 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
264 /* Set access parameters for DRAM bank i */
265 win_param.win = i; /* Use Ethernet window i */
266 /* Window target - DDR */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200267 win_param.target = MVGBE_TARGET_DRAM;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530268 /* Enable full access */
269 win_param.access_ctrl = EWIN_ACCESS_FULL;
270 win_param.high_addr = 0;
Albert Aribaud49fa6ed2010-07-05 20:15:25 +0200271 /* Get bank base and size */
272 win_param.base_addr = gd->bd->bi_dram[i].start;
273 win_param.size = gd->bd->bi_dram[i].size;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530274 if (win_param.size == 0)
275 win_param.enable = 0;
276 else
277 win_param.enable = 1; /* Enable the access */
278
279 /* Enable DRAM bank */
280 switch (i) {
281 case 0:
282 win_param.attrib = EBAR_DRAM_CS0;
283 break;
284 case 1:
285 win_param.attrib = EBAR_DRAM_CS1;
286 break;
287 case 2:
288 win_param.attrib = EBAR_DRAM_CS2;
289 break;
290 case 3:
291 win_param.attrib = EBAR_DRAM_CS3;
292 break;
293 default:
Albert Aribaud49fa6ed2010-07-05 20:15:25 +0200294 /* invalid bank, disable access */
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530295 win_param.enable = 0;
296 win_param.attrib = 0;
297 break;
298 }
299 /* Set the access control for address window(EPAPR) RD/WR */
300 set_access_control(regs, &win_param);
301 }
302}
303
304/*
305 * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
306 *
307 * Go through all the DA filter tables (Unicast, Special Multicast & Other
308 * Multicast) and set each entry to 0.
309 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200310static void port_init_mac_tables(struct mvgbe_registers *regs)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530311{
312 int table_index;
313
314 /* Clear DA filter unicast table (Ex_dFUT) */
315 for (table_index = 0; table_index < 4; ++table_index)
Albert Aribaudd44265a2010-07-12 22:24:28 +0200316 MVGBE_REG_WR(regs->dfut[table_index], 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530317
318 for (table_index = 0; table_index < 64; ++table_index) {
319 /* Clear DA filter special multicast table (Ex_dFSMT) */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200320 MVGBE_REG_WR(regs->dfsmt[table_index], 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530321 /* Clear DA filter other multicast table (Ex_dFOMT) */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200322 MVGBE_REG_WR(regs->dfomt[table_index], 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530323 }
324}
325
326/*
327 * port_uc_addr - This function Set the port unicast address table
328 *
329 * This function locates the proper entry in the Unicast table for the
330 * specified MAC nibble and sets its properties according to function
331 * parameters.
332 * This function add/removes MAC addresses from the port unicast address
333 * table.
334 *
335 * @uc_nibble Unicast MAC Address last nibble.
336 * @option 0 = Add, 1 = remove address.
337 *
338 * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
339 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200340static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble,
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530341 int option)
342{
343 u32 unicast_reg;
344 u32 tbl_offset;
345 u32 reg_offset;
346
347 /* Locate the Unicast table entry */
348 uc_nibble = (0xf & uc_nibble);
349 /* Register offset from unicast table base */
350 tbl_offset = (uc_nibble / 4);
351 /* Entry offset within the above register */
352 reg_offset = uc_nibble % 4;
353
354 switch (option) {
355 case REJECT_MAC_ADDR:
356 /*
357 * Clear accepts frame bit at specified unicast
358 * DA table entry
359 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200360 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530361 unicast_reg &= (0xFF << (8 * reg_offset));
Albert Aribaudd44265a2010-07-12 22:24:28 +0200362 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530363 break;
364 case ACCEPT_MAC_ADDR:
365 /* Set accepts frame bit at unicast DA filter table entry */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200366 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530367 unicast_reg &= (0xFF << (8 * reg_offset));
368 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
Albert Aribaudd44265a2010-07-12 22:24:28 +0200369 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530370 break;
371 default:
372 return 0;
373 }
374 return 1;
375}
376
377/*
378 * port_uc_addr_set - This function Set the port Unicast address.
379 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200380static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530381{
382 u32 mac_h;
383 u32 mac_l;
384
385 mac_l = (p_addr[4] << 8) | (p_addr[5]);
386 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
387 (p_addr[3] << 0);
388
Albert Aribaudd44265a2010-07-12 22:24:28 +0200389 MVGBE_REG_WR(regs->macal, mac_l);
390 MVGBE_REG_WR(regs->macah, mac_h);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530391
392 /* Accept frames of this address */
393 port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
394}
395
396/*
Albert Aribaudd44265a2010-07-12 22:24:28 +0200397 * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530398 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200399static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530400{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200401 struct mvgbe_rxdesc *p_rx_desc;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530402 int i;
403
404 /* initialize the Rx descriptors ring */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200405 p_rx_desc = dmvgbe->p_rxdesc;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530406 for (i = 0; i < RINGSZ; i++) {
407 p_rx_desc->cmd_sts =
Albert Aribaudd44265a2010-07-12 22:24:28 +0200408 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530409 p_rx_desc->buf_size = PKTSIZE_ALIGN;
410 p_rx_desc->byte_cnt = 0;
Albert Aribaudd44265a2010-07-12 22:24:28 +0200411 p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530412 if (i == (RINGSZ - 1))
Albert Aribaudd44265a2010-07-12 22:24:28 +0200413 p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530414 else {
Albert Aribaudd44265a2010-07-12 22:24:28 +0200415 p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *)
416 ((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530417 p_rx_desc = p_rx_desc->nxtdesc_p;
418 }
419 }
Albert Aribaudd44265a2010-07-12 22:24:28 +0200420 dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530421}
422
Albert Aribaudd44265a2010-07-12 22:24:28 +0200423static int mvgbe_init(struct eth_device *dev)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530424{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200425 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
426 struct mvgbe_registers *regs = dmvgbe->regs;
Sascha Silbe0611c602013-08-11 17:08:23 +0200427#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
428 !defined(CONFIG_PHYLIB) && \
429 defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
Simon Kagstromcad713b2009-08-20 10:13:06 +0200430 int i;
Prafulla Wadaskaraba82372009-09-09 15:59:19 +0530431#endif
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530432 /* setup RX rings */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200433 mvgbe_init_rx_desc_ring(dmvgbe);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530434
435 /* Clear the ethernet port interrupts */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200436 MVGBE_REG_WR(regs->ic, 0);
437 MVGBE_REG_WR(regs->ice, 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530438 /* Unmask RX buffer and TX end interrupt */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200439 MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530440 /* Unmask phy and link status changes interrupts */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200441 MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530442
443 set_dram_access(regs);
444 port_init_mac_tables(regs);
Albert Aribaudd44265a2010-07-12 22:24:28 +0200445 port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530446
447 /* Assign port configuration and command. */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200448 MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
449 MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
450 MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530451
452 /* Assign port SDMA configuration */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200453 MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
454 MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
455 MVGBE_REG_WR(regs->tqx[0].tqxtbc,
456 (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530457 /* Turn off the port/RXUQ bandwidth limitation */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200458 MVGBE_REG_WR(regs->pmtu, 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530459
460 /* Set maximum receive buffer to 9700 bytes */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200461 MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE
462 | (MVGBE_REG_RD(regs->psc0) & MRU_MASK));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530463
Prafulla Wadaskarf0588fd2010-04-06 21:33:08 +0530464 /* Enable port initially */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200465 MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN);
Prafulla Wadaskarf0588fd2010-04-06 21:33:08 +0530466
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530467 /*
468 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
469 * disable the leaky bucket mechanism .
470 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200471 MVGBE_REG_WR(regs->pmtu, 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530472
473 /* Assignment of Rx CRDB of given RXUQ */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200474 MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr);
Albert Aribaudc19a20d2010-07-10 15:41:29 +0200475 /* ensure previous write is done before enabling Rx DMA */
476 isb();
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530477 /* Enable port Rx. */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200478 MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530479
Sebastian Hesselbarthcd3ca3f2012-12-04 09:32:00 +0100480#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
481 !defined(CONFIG_PHYLIB) && \
482 defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
Simon Kagstromcad713b2009-08-20 10:13:06 +0200483 /* Wait up to 5s for the link status */
484 for (i = 0; i < 5; i++) {
485 u16 phyadr;
486
Albert Aribaudd44265a2010-07-12 22:24:28 +0200487 miiphy_read(dev->name, MV_PHY_ADR_REQUEST,
488 MV_PHY_ADR_REQUEST, &phyadr);
Simon Kagstromcad713b2009-08-20 10:13:06 +0200489 /* Return if we get link up */
490 if (miiphy_link(dev->name, phyadr))
491 return 0;
492 udelay(1000000);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530493 }
Simon Kagstromcad713b2009-08-20 10:13:06 +0200494
495 printf("No link on %s\n", dev->name);
496 return -1;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530497#endif
498 return 0;
499}
500
Albert Aribaudd44265a2010-07-12 22:24:28 +0200501static int mvgbe_halt(struct eth_device *dev)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530502{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200503 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
504 struct mvgbe_registers *regs = dmvgbe->regs;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530505
506 /* Disable all gigE address decoder */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200507 MVGBE_REG_WR(regs->bare, 0x3f);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530508
509 stop_queue(&regs->tqc);
510 stop_queue(&regs->rqc);
511
Prafulla Wadaskarf0588fd2010-04-06 21:33:08 +0530512 /* Disable port */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200513 MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530514 /* Set port is not reset */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200515 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530516#ifdef CONFIG_SYS_MII_MODE
517 /* Set MMI interface up */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200518 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530519#endif
520 /* Disable & mask ethernet port interrupts */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200521 MVGBE_REG_WR(regs->ic, 0);
522 MVGBE_REG_WR(regs->ice, 0);
523 MVGBE_REG_WR(regs->pim, 0);
524 MVGBE_REG_WR(regs->peim, 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530525
526 return 0;
527}
528
Albert Aribaudd44265a2010-07-12 22:24:28 +0200529static int mvgbe_write_hwaddr(struct eth_device *dev)
Prafulla Wadaskarb5ce63e2010-04-06 22:21:33 +0530530{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200531 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
532 struct mvgbe_registers *regs = dmvgbe->regs;
Prafulla Wadaskarb5ce63e2010-04-06 22:21:33 +0530533
534 /* Programs net device MAC address after initialization */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200535 port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
Prafulla Wadaskarb5ce63e2010-04-06 22:21:33 +0530536 return 0;
537}
538
Joe Hershberger10cbe3b2012-05-22 18:36:19 +0000539static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530540{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200541 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
542 struct mvgbe_registers *regs = dmvgbe->regs;
543 struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
Simon Kagstrom477fa632009-08-20 10:14:11 +0200544 void *p = (void *)dataptr;
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200545 u32 cmd_sts;
Anatolij Gustschine6e556c2011-11-19 08:59:36 +0000546 u32 txuq0_reg_addr;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530547
Simon Kagstrom477fa632009-08-20 10:14:11 +0200548 /* Copy buffer if it's misaligned */
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530549 if ((u32) dataptr & 0x07) {
Simon Kagstrom477fa632009-08-20 10:14:11 +0200550 if (datasize > PKTSIZE_ALIGN) {
551 printf("Non-aligned data too large (%d)\n",
552 datasize);
553 return -1;
554 }
555
Albert Aribaudd44265a2010-07-12 22:24:28 +0200556 memcpy(dmvgbe->p_aligned_txbuf, p, datasize);
557 p = dmvgbe->p_aligned_txbuf;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530558 }
Simon Kagstrom477fa632009-08-20 10:14:11 +0200559
Albert Aribaudd44265a2010-07-12 22:24:28 +0200560 p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC;
561 p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC;
562 p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA;
563 p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT;
Simon Kagstrom477fa632009-08-20 10:14:11 +0200564 p_txdesc->buf_ptr = (u8 *) p;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530565 p_txdesc->byte_cnt = datasize;
566
Albert Aribaudc19a20d2010-07-10 15:41:29 +0200567 /* Set this tc desc as zeroth TXUQ */
Anatolij Gustschine6e556c2011-11-19 08:59:36 +0000568 txuq0_reg_addr = (u32)&regs->tcqdp[TXUQ];
569 writel((u32) p_txdesc, txuq0_reg_addr);
Albert Aribaudc19a20d2010-07-10 15:41:29 +0200570
571 /* ensure tx desc writes above are performed before we start Tx DMA */
572 isb();
573
574 /* Apply send command using zeroth TXUQ */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200575 MVGBE_REG_WR(regs->tqc, (1 << TXUQ));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530576
577 /*
578 * wait for packet xmit completion
579 */
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200580 cmd_sts = readl(&p_txdesc->cmd_sts);
Albert Aribaudd44265a2010-07-12 22:24:28 +0200581 while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530582 /* return fail if error is detected */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200583 if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) ==
584 (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) &&
585 cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530586 printf("Err..(%s) in xmit packet\n", __FUNCTION__);
587 return -1;
588 }
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200589 cmd_sts = readl(&p_txdesc->cmd_sts);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530590 };
591 return 0;
592}
593
Albert Aribaudd44265a2010-07-12 22:24:28 +0200594static int mvgbe_recv(struct eth_device *dev)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530595{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200596 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
597 struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200598 u32 cmd_sts;
599 u32 timeout = 0;
Anatolij Gustschine6e556c2011-11-19 08:59:36 +0000600 u32 rxdesc_curr_addr;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530601
602 /* wait untill rx packet available or timeout */
603 do {
Albert Aribaudd44265a2010-07-12 22:24:28 +0200604 if (timeout < MVGBE_PHY_SMI_TIMEOUT)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530605 timeout++;
606 else {
607 debug("%s time out...\n", __FUNCTION__);
608 return -1;
609 }
Albert Aribaudd44265a2010-07-12 22:24:28 +0200610 } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530611
612 if (p_rxdesc_curr->byte_cnt != 0) {
613 debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
614 __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt,
615 (u32) p_rxdesc_curr->buf_ptr,
616 (u32) p_rxdesc_curr->cmd_sts);
617 }
618
619 /*
620 * In case received a packet without first/last bits on
621 * OR the error summary bit is on,
622 * the packets needs to be dropeed.
623 */
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200624 cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
625
626 if ((cmd_sts &
Albert Aribaudd44265a2010-07-12 22:24:28 +0200627 (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC))
628 != (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530629
630 printf("Err..(%s) Dropping packet spread on"
631 " multiple descriptors\n", __FUNCTION__);
632
Albert Aribaudd44265a2010-07-12 22:24:28 +0200633 } else if (cmd_sts & MVGBE_ERROR_SUMMARY) {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530634
635 printf("Err..(%s) Dropping packet with errors\n",
636 __FUNCTION__);
637
638 } else {
639 /* !!! call higher layer processing */
640 debug("%s: Sending Received packet to"
641 " upper layer (NetReceive)\n", __FUNCTION__);
642
643 /* let the upper layer handle the packet */
644 NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
645 (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
646 }
647 /*
648 * free these descriptors and point next in the ring
649 */
650 p_rxdesc_curr->cmd_sts =
Albert Aribaudd44265a2010-07-12 22:24:28 +0200651 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530652 p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
653 p_rxdesc_curr->byte_cnt = 0;
654
Anatolij Gustschine6e556c2011-11-19 08:59:36 +0000655 rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr;
656 writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr);
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200657
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530658 return 0;
659}
660
Sebastian Hesselbarthcd3ca3f2012-12-04 09:32:00 +0100661#if defined(CONFIG_PHYLIB)
662int mvgbe_phylib_init(struct eth_device *dev, int phyid)
663{
664 struct mii_dev *bus;
665 struct phy_device *phydev;
666 int ret;
667
668 bus = mdio_alloc();
669 if (!bus) {
670 printf("mdio_alloc failed\n");
671 return -ENOMEM;
672 }
673 bus->read = mvgbe_phy_read;
674 bus->write = mvgbe_phy_write;
675 sprintf(bus->name, dev->name);
676
677 ret = mdio_register(bus);
678 if (ret) {
679 printf("mdio_register failed\n");
680 free(bus);
681 return -ENOMEM;
682 }
683
684 /* Set phy address of the port */
685 mvgbe_phy_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid);
686
687 phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII);
688 if (!phydev) {
689 printf("phy_connect failed\n");
690 return -ENODEV;
691 }
692
693 phy_config(phydev);
694 phy_startup(phydev);
695
696 return 0;
697}
698#endif
699
Albert Aribaudd44265a2010-07-12 22:24:28 +0200700int mvgbe_initialize(bd_t *bis)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530701{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200702 struct mvgbe_device *dmvgbe;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530703 struct eth_device *dev;
704 int devnum;
Albert Aribaudd44265a2010-07-12 22:24:28 +0200705 u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530706
Albert Aribaudd44265a2010-07-12 22:24:28 +0200707 for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530708 /*skip if port is configured not to use */
709 if (used_ports[devnum] == 0)
710 continue;
711
Albert Aribaudd44265a2010-07-12 22:24:28 +0200712 dmvgbe = malloc(sizeof(struct mvgbe_device));
713
714 if (!dmvgbe)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530715 goto error1;
716
Albert Aribaudd44265a2010-07-12 22:24:28 +0200717 memset(dmvgbe, 0, sizeof(struct mvgbe_device));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530718
Albert Aribaudd44265a2010-07-12 22:24:28 +0200719 dmvgbe->p_rxdesc =
720 (struct mvgbe_rxdesc *)memalign(PKTALIGN,
721 MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1);
722
723 if (!dmvgbe->p_rxdesc)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530724 goto error2;
725
Albert Aribaudd44265a2010-07-12 22:24:28 +0200726 dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN,
727 RINGSZ*PKTSIZE_ALIGN + 1);
728
729 if (!dmvgbe->p_rxbuf)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530730 goto error3;
731
Albert Aribaudd44265a2010-07-12 22:24:28 +0200732 dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
733
734 if (!dmvgbe->p_aligned_txbuf)
Simon Kagstrom477fa632009-08-20 10:14:11 +0200735 goto error4;
736
Albert Aribaudd44265a2010-07-12 22:24:28 +0200737 dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign(
738 PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
739
740 if (!dmvgbe->p_txdesc) {
741 free(dmvgbe->p_aligned_txbuf);
742error4:
743 free(dmvgbe->p_rxbuf);
744error3:
745 free(dmvgbe->p_rxdesc);
746error2:
747 free(dmvgbe);
748error1:
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530749 printf("Err.. %s Failed to allocate memory\n",
750 __FUNCTION__);
751 return -1;
752 }
753
Albert Aribaudd44265a2010-07-12 22:24:28 +0200754 dev = &dmvgbe->dev;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530755
Mike Frysingerf6add132011-11-10 14:11:04 +0000756 /* must be less than sizeof(dev->name) */
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530757 sprintf(dev->name, "egiga%d", devnum);
758
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530759 switch (devnum) {
760 case 0:
Albert Aribaudd44265a2010-07-12 22:24:28 +0200761 dmvgbe->regs = (void *)MVGBE0_BASE;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530762 break;
Albert Aribaudd44265a2010-07-12 22:24:28 +0200763#if defined(MVGBE1_BASE)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530764 case 1:
Albert Aribaudd44265a2010-07-12 22:24:28 +0200765 dmvgbe->regs = (void *)MVGBE1_BASE;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530766 break;
Albert Aribaudd44265a2010-07-12 22:24:28 +0200767#endif
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530768 default: /* this should never happen */
769 printf("Err..(%s) Invalid device number %d\n",
770 __FUNCTION__, devnum);
771 return -1;
772 }
773
Albert Aribaudd44265a2010-07-12 22:24:28 +0200774 dev->init = (void *)mvgbe_init;
775 dev->halt = (void *)mvgbe_halt;
776 dev->send = (void *)mvgbe_send;
777 dev->recv = (void *)mvgbe_recv;
778 dev->write_hwaddr = (void *)mvgbe_write_hwaddr;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530779
780 eth_register(dev);
781
Sebastian Hesselbarthcd3ca3f2012-12-04 09:32:00 +0100782#if defined(CONFIG_PHYLIB)
783 mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum);
784#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530785 miiphy_register(dev->name, smi_reg_read, smi_reg_write);
786 /* Set phy address of the port */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200787 miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
788 MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530789#endif
790 }
791 return 0;
Prafulla Wadaskar0b785dd2009-07-01 20:34:51 +0200792}