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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
Wolfgang Denkd87080b2006-03-31 18:32:53 +02002 * (C) Copyright 2000-2006
wdenk4a9cbbe2002-08-27 09:48:53 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
wdenk8564acf2003-07-14 22:13:32 +000025 * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x
wdenk4a9cbbe2002-08-27 09:48:53 +000026 *
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
29 *
wdenk4532cb62003-04-27 22:52:51 +000030 * modified by
wdenk4a9cbbe2002-08-27 09:48:53 +000031 * Wolfgang Denk <wd@denx.de>
32 *
33 * modified for 8260 by
34 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
35 *
36 * added 8260 masks by
37 * Marius Groeger <mag@sysgo.de>
wdenk8564acf2003-07-14 22:13:32 +000038 *
wdenk04a85b32004-04-15 18:22:41 +000039 * added HiP7 (824x/827x/8280) processors support by
wdenk8564acf2003-07-14 22:13:32 +000040 * Yuli Barcohen <yuli@arabellasw.com>
wdenk4a9cbbe2002-08-27 09:48:53 +000041 */
42
43#include <common.h>
44#include <watchdog.h>
45#include <command.h>
46#include <mpc8260.h>
Ben Warren3456a142008-10-22 23:20:29 -070047#include <netdev.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000048#include <asm/processor.h>
49#include <asm/cpm_8260.h>
50
Sergej Stepanovc9e7b9b2007-10-17 11:13:51 +020051#if defined(CONFIG_OF_LIBFDT)
52#include <libfdt.h>
53#include <libfdt_env.h>
Kumar Galae93becf2007-11-03 19:46:28 -050054#include <fdt_support.h>
Sergej Stepanovc9e7b9b2007-10-17 11:13:51 +020055#endif
56
Wolfgang Denkd87080b2006-03-31 18:32:53 +020057DECLARE_GLOBAL_DATA_PTR;
58
Heiko Schocherfa230442006-12-21 17:17:02 +010059#if defined(CONFIG_GET_CPU_STR_F)
60extern int get_cpu_str_f (char *buf);
61#endif
62
wdenk4a9cbbe2002-08-27 09:48:53 +000063int checkcpu (void)
64{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk4a9cbbe2002-08-27 09:48:53 +000066 ulong clock = gd->cpu_clk;
67 uint pvr = get_pvr ();
68 uint immr, rev, m, k;
69 char buf[32];
70
71 puts ("CPU: ");
72
wdenk8564acf2003-07-14 22:13:32 +000073 switch (pvr) {
74 case PVR_8260:
75 case PVR_8260_HIP3:
76 k = 3;
77 break;
78 case PVR_8260_HIP4:
79 k = 4;
80 break;
wdenk5779d8d2003-12-06 23:55:10 +000081 case PVR_8260_HIP7R1:
wdenke1599e82004-10-10 23:27:33 +000082 case PVR_8260_HIP7RA:
wdenk8564acf2003-07-14 22:13:32 +000083 case PVR_8260_HIP7:
84 k = 7;
85 break;
86 default:
wdenk4a9cbbe2002-08-27 09:48:53 +000087 return -1; /* whoops! not an MPC8260 */
wdenk8564acf2003-07-14 22:13:32 +000088 }
wdenk4a9cbbe2002-08-27 09:48:53 +000089 rev = pvr & 0xff;
90
91 immr = immap->im_memctl.memc_immr;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092 if ((immr & IMMR_ISB_MSK) != CONFIG_SYS_IMMR)
wdenk4a9cbbe2002-08-27 09:48:53 +000093 return -1; /* whoops! someone moved the IMMR */
94
Heiko Schocherfa230442006-12-21 17:17:02 +010095#if defined(CONFIG_GET_CPU_STR_F)
96 get_cpu_str_f (buf);
97 printf ("%s (HiP%d Rev %02x, Mask ", buf, k, rev);
98#else
wdenk8564acf2003-07-14 22:13:32 +000099 printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
Heiko Schocherfa230442006-12-21 17:17:02 +0100100#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000101
102 /*
103 * the bottom 16 bits of the immr are the Part Number and Mask Number
104 * (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the
105 * RISC Microcode Revision Number (13-10).
106 * For the 8260, Motorola doesn't include the Microcode Revision
107 * in the mask.
108 */
109 m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK);
110 k = *((ushort *) & immap->im_dprambase[PROFF_REVNUM]);
111
112 switch (m) {
113 case 0x0000:
wdenk4b9206e2004-03-23 22:14:11 +0000114 puts ("0.2 2J24M");
wdenk4a9cbbe2002-08-27 09:48:53 +0000115 break;
116 case 0x0010:
wdenk4b9206e2004-03-23 22:14:11 +0000117 puts ("A.0 K22A");
wdenk4a9cbbe2002-08-27 09:48:53 +0000118 break;
119 case 0x0011:
wdenk4b9206e2004-03-23 22:14:11 +0000120 puts ("A.1 1K22A-XC");
wdenk4a9cbbe2002-08-27 09:48:53 +0000121 break;
122 case 0x0001:
wdenk4b9206e2004-03-23 22:14:11 +0000123 puts ("B.1 1K23A");
wdenk4a9cbbe2002-08-27 09:48:53 +0000124 break;
125 case 0x0021:
wdenk4b9206e2004-03-23 22:14:11 +0000126 puts ("B.2 2K23A-XC");
wdenk4a9cbbe2002-08-27 09:48:53 +0000127 break;
128 case 0x0023:
wdenk4b9206e2004-03-23 22:14:11 +0000129 puts ("B.3 3K23A");
wdenk4a9cbbe2002-08-27 09:48:53 +0000130 break;
131 case 0x0024:
wdenk4b9206e2004-03-23 22:14:11 +0000132 puts ("C.2 6K23A");
wdenk4a9cbbe2002-08-27 09:48:53 +0000133 break;
134 case 0x0060:
wdenk4b9206e2004-03-23 22:14:11 +0000135 puts ("A.0(A) 2K25A");
wdenk4a9cbbe2002-08-27 09:48:53 +0000136 break;
wdenk4532cb62003-04-27 22:52:51 +0000137 case 0x0062:
wdenk4b9206e2004-03-23 22:14:11 +0000138 puts ("B.1 4K25A");
wdenk4532cb62003-04-27 22:52:51 +0000139 break;
wdenk54387ac2003-10-08 22:45:44 +0000140 case 0x0064:
wdenk4b9206e2004-03-23 22:14:11 +0000141 puts ("C.0 5K25A");
wdenk54387ac2003-10-08 22:45:44 +0000142 break;
wdenk8564acf2003-07-14 22:13:32 +0000143 case 0x0A00:
wdenk4b9206e2004-03-23 22:14:11 +0000144 puts ("0.0 0K49M");
wdenk8564acf2003-07-14 22:13:32 +0000145 break;
146 case 0x0A01:
wdenk4b9206e2004-03-23 22:14:11 +0000147 puts ("0.1 1K49M");
wdenk8564acf2003-07-14 22:13:32 +0000148 break;
wdenke1599e82004-10-10 23:27:33 +0000149 case 0x0A10:
150 puts ("1.0 1K49M");
151 break;
wdenk04a85b32004-04-15 18:22:41 +0000152 case 0x0C00:
wdenke1599e82004-10-10 23:27:33 +0000153 puts ("0.0 0K50M");
154 break;
155 case 0x0C10:
Wolfgang Denkd980a162005-08-06 02:03:03 +0200156 puts ("1.0 1K50M");
wdenke1599e82004-10-10 23:27:33 +0000157 break;
wdenk04a85b32004-04-15 18:22:41 +0000158 case 0x0D00:
wdenke1599e82004-10-10 23:27:33 +0000159 puts ("0.0 0K50M");
160 break;
161 case 0x0D10:
Wolfgang Denkd980a162005-08-06 02:03:03 +0200162 puts ("1.0 1K50M");
wdenk04a85b32004-04-15 18:22:41 +0000163 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000164 default:
165 printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
166 break;
167 }
168
169 printf (") at %s MHz\n", strmhz (buf, clock));
170
171 return 0;
172}
173
174/* ------------------------------------------------------------------------- */
175/* configures a UPM by writing into the UPM RAM array */
176/* uses bank 11 and a dummy physical address (=BRx_BA_MSK) */
177/* NOTE: the physical address chosen must not overlap into any other area */
178/* mapped by the memory controller because bank 11 has the lowest priority */
179
180void upmconfig (uint upm, uint * table, uint size)
181{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk4a9cbbe2002-08-27 09:48:53 +0000183 volatile memctl8260_t *memctl = &immap->im_memctl;
184 volatile uchar *dummy = (uchar *) BRx_BA_MSK; /* set all BA bits */
185 uint i;
186
187 /* first set up bank 11 to reference the correct UPM at a dummy address */
188
189 memctl->memc_or11 = ORxU_AM_MSK; /* set all AM bits */
190
191 switch (upm) {
192
193 case UPMA:
194 memctl->memc_br11 =
195 ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMA |
196 BRx_V;
197 memctl->memc_mamr = MxMR_OP_WARR;
198 break;
199
200 case UPMB:
201 memctl->memc_br11 =
202 ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMB |
203 BRx_V;
204 memctl->memc_mbmr = MxMR_OP_WARR;
205 break;
206
207 case UPMC:
208 memctl->memc_br11 =
209 ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMC |
210 BRx_V;
211 memctl->memc_mcmr = MxMR_OP_WARR;
212 break;
213
214 default:
215 panic ("upmconfig passed invalid UPM number (%u)\n", upm);
216 break;
217
218 }
219
220 /*
221 * at this point, the dummy address is set up to access the selected UPM,
222 * the MAD pointer is zero, and the MxMR OP is set for writing to RAM
223 *
224 * now we simply load the mdr with each word and poke the dummy address.
225 * the MAD is incremented on each access.
226 */
227
228 for (i = 0; i < size; i++) {
229 memctl->memc_mdr = table[i];
230 *dummy = 0;
231 }
232
233 /* now kill bank 11 */
234 memctl->memc_br11 = 0;
235}
236
237/* ------------------------------------------------------------------------- */
238
wdenkba91e262005-05-30 23:55:42 +0000239#if !defined(CONFIG_HAVE_OWN_RESET)
wdenk4a9cbbe2002-08-27 09:48:53 +0000240int
wdenk8bde7f72003-06-27 21:31:46 +0000241do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +0000242{
243 ulong msr, addr;
244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk4a9cbbe2002-08-27 09:48:53 +0000246
247 immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */
248
249 /* Interrupts and MMU off */
250 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
251
252 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
253 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
254
255 /*
256 * Trying to execute the next instruction at a non-existing address
257 * should cause a machine check, resulting in reset
258 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#ifdef CONFIG_SYS_RESET_ADDRESS
260 addr = CONFIG_SYS_RESET_ADDRESS;
wdenk4a9cbbe2002-08-27 09:48:53 +0000261#else
262 /*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
wdenk4a9cbbe2002-08-27 09:48:53 +0000264 * - sizeof (ulong) is usually a valid address. Better pick an address
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265 * known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
wdenk4a9cbbe2002-08-27 09:48:53 +0000266 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267 addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
wdenk4a9cbbe2002-08-27 09:48:53 +0000268#endif
269 ((void (*)(void)) addr) ();
270 return 1;
271
272}
wdenkba91e262005-05-30 23:55:42 +0000273#endif /* CONFIG_HAVE_OWN_RESET */
wdenk4a9cbbe2002-08-27 09:48:53 +0000274
275/* ------------------------------------------------------------------------- */
276
277/*
278 * Get timebase clock frequency (like cpu_clk in Hz)
279 *
280 */
281unsigned long get_tbclk (void)
282{
wdenk4a9cbbe2002-08-27 09:48:53 +0000283 ulong tbclk;
284
285 tbclk = (gd->bus_clk + 3L) / 4L;
286
287 return (tbclk);
288}
289
290/* ------------------------------------------------------------------------- */
291
292#if defined(CONFIG_WATCHDOG)
293void watchdog_reset (void)
294{
295 int re_enable = disable_interrupts ();
296
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297 reset_8260_watchdog ((immap_t *) CONFIG_SYS_IMMR);
wdenk4a9cbbe2002-08-27 09:48:53 +0000298 if (re_enable)
299 enable_interrupts ();
300}
301#endif /* CONFIG_WATCHDOG */
302
303/* ------------------------------------------------------------------------- */
Marian Balakowicz75d3e8f2008-02-21 17:20:18 +0100304#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
Sergej Stepanovc9e7b9b2007-10-17 11:13:51 +0200305void ft_cpu_setup (void *blob, bd_t *bd)
306{
307 char * cpu_path = "/cpus/" OF_CPU;
308
Esben Haabendalee4ae382008-06-18 11:03:57 +0200309#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
310 defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
Kumar Galaba37aa02008-08-19 15:41:18 -0500311 fdt_fixup_ethernet(blob);
Esben Haabendalee4ae382008-06-18 11:03:57 +0200312#endif
313
Kumar Galae93becf2007-11-03 19:46:28 -0500314 do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
315 do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
316 do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
Sergej Stepanovc9e7b9b2007-10-17 11:13:51 +0200317}
318#endif /* CONFIG_OF_LIBFDT */
Ben Warren3456a142008-10-22 23:20:29 -0700319
320/*
321 * Initializes on-chip ethernet controllers.
322 * to override, implement board_eth_init()
323 */
324int cpu_eth_init(bd_t *bis)
325{
326#if defined(CONFIG_ETHER_ON_FCC)
327 fec_initialize(bis);
328#endif
329 return 0;
330}