blob: efb8ed6f4e8d60f674b13ee263a03f077ff7a2b5 [file] [log] [blame]
wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
Wolfgang Denkd87080b2006-03-31 18:32:53 +02002 * (C) Copyright 2000-2006
wdenk4a9cbbe2002-08-27 09:48:53 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
wdenk8564acf2003-07-14 22:13:32 +000025 * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x
wdenk4a9cbbe2002-08-27 09:48:53 +000026 *
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
29 *
wdenk4532cb62003-04-27 22:52:51 +000030 * modified by
wdenk4a9cbbe2002-08-27 09:48:53 +000031 * Wolfgang Denk <wd@denx.de>
32 *
33 * modified for 8260 by
34 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
35 *
36 * added 8260 masks by
37 * Marius Groeger <mag@sysgo.de>
wdenk8564acf2003-07-14 22:13:32 +000038 *
wdenk04a85b32004-04-15 18:22:41 +000039 * added HiP7 (824x/827x/8280) processors support by
wdenk8564acf2003-07-14 22:13:32 +000040 * Yuli Barcohen <yuli@arabellasw.com>
wdenk4a9cbbe2002-08-27 09:48:53 +000041 */
42
43#include <common.h>
44#include <watchdog.h>
45#include <command.h>
46#include <mpc8260.h>
47#include <asm/processor.h>
48#include <asm/cpm_8260.h>
49
Sergej Stepanovc9e7b9b2007-10-17 11:13:51 +020050#if defined(CONFIG_OF_LIBFDT)
51#include <libfdt.h>
52#include <libfdt_env.h>
Kumar Galae93becf2007-11-03 19:46:28 -050053#include <fdt_support.h>
Sergej Stepanovc9e7b9b2007-10-17 11:13:51 +020054#endif
55
Wolfgang Denkd87080b2006-03-31 18:32:53 +020056DECLARE_GLOBAL_DATA_PTR;
57
Heiko Schocherfa230442006-12-21 17:17:02 +010058#if defined(CONFIG_GET_CPU_STR_F)
59extern int get_cpu_str_f (char *buf);
60#endif
61
wdenk4a9cbbe2002-08-27 09:48:53 +000062int checkcpu (void)
63{
wdenk4a9cbbe2002-08-27 09:48:53 +000064 volatile immap_t *immap = (immap_t *) CFG_IMMR;
65 ulong clock = gd->cpu_clk;
66 uint pvr = get_pvr ();
67 uint immr, rev, m, k;
68 char buf[32];
69
70 puts ("CPU: ");
71
wdenk8564acf2003-07-14 22:13:32 +000072 switch (pvr) {
73 case PVR_8260:
74 case PVR_8260_HIP3:
75 k = 3;
76 break;
77 case PVR_8260_HIP4:
78 k = 4;
79 break;
wdenk5779d8d2003-12-06 23:55:10 +000080 case PVR_8260_HIP7R1:
wdenke1599e82004-10-10 23:27:33 +000081 case PVR_8260_HIP7RA:
wdenk8564acf2003-07-14 22:13:32 +000082 case PVR_8260_HIP7:
83 k = 7;
84 break;
85 default:
wdenk4a9cbbe2002-08-27 09:48:53 +000086 return -1; /* whoops! not an MPC8260 */
wdenk8564acf2003-07-14 22:13:32 +000087 }
wdenk4a9cbbe2002-08-27 09:48:53 +000088 rev = pvr & 0xff;
89
90 immr = immap->im_memctl.memc_immr;
91 if ((immr & IMMR_ISB_MSK) != CFG_IMMR)
92 return -1; /* whoops! someone moved the IMMR */
93
Heiko Schocherfa230442006-12-21 17:17:02 +010094#if defined(CONFIG_GET_CPU_STR_F)
95 get_cpu_str_f (buf);
96 printf ("%s (HiP%d Rev %02x, Mask ", buf, k, rev);
97#else
wdenk8564acf2003-07-14 22:13:32 +000098 printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
Heiko Schocherfa230442006-12-21 17:17:02 +010099#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000100
101 /*
102 * the bottom 16 bits of the immr are the Part Number and Mask Number
103 * (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the
104 * RISC Microcode Revision Number (13-10).
105 * For the 8260, Motorola doesn't include the Microcode Revision
106 * in the mask.
107 */
108 m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK);
109 k = *((ushort *) & immap->im_dprambase[PROFF_REVNUM]);
110
111 switch (m) {
112 case 0x0000:
wdenk4b9206e2004-03-23 22:14:11 +0000113 puts ("0.2 2J24M");
wdenk4a9cbbe2002-08-27 09:48:53 +0000114 break;
115 case 0x0010:
wdenk4b9206e2004-03-23 22:14:11 +0000116 puts ("A.0 K22A");
wdenk4a9cbbe2002-08-27 09:48:53 +0000117 break;
118 case 0x0011:
wdenk4b9206e2004-03-23 22:14:11 +0000119 puts ("A.1 1K22A-XC");
wdenk4a9cbbe2002-08-27 09:48:53 +0000120 break;
121 case 0x0001:
wdenk4b9206e2004-03-23 22:14:11 +0000122 puts ("B.1 1K23A");
wdenk4a9cbbe2002-08-27 09:48:53 +0000123 break;
124 case 0x0021:
wdenk4b9206e2004-03-23 22:14:11 +0000125 puts ("B.2 2K23A-XC");
wdenk4a9cbbe2002-08-27 09:48:53 +0000126 break;
127 case 0x0023:
wdenk4b9206e2004-03-23 22:14:11 +0000128 puts ("B.3 3K23A");
wdenk4a9cbbe2002-08-27 09:48:53 +0000129 break;
130 case 0x0024:
wdenk4b9206e2004-03-23 22:14:11 +0000131 puts ("C.2 6K23A");
wdenk4a9cbbe2002-08-27 09:48:53 +0000132 break;
133 case 0x0060:
wdenk4b9206e2004-03-23 22:14:11 +0000134 puts ("A.0(A) 2K25A");
wdenk4a9cbbe2002-08-27 09:48:53 +0000135 break;
wdenk4532cb62003-04-27 22:52:51 +0000136 case 0x0062:
wdenk4b9206e2004-03-23 22:14:11 +0000137 puts ("B.1 4K25A");
wdenk4532cb62003-04-27 22:52:51 +0000138 break;
wdenk54387ac2003-10-08 22:45:44 +0000139 case 0x0064:
wdenk4b9206e2004-03-23 22:14:11 +0000140 puts ("C.0 5K25A");
wdenk54387ac2003-10-08 22:45:44 +0000141 break;
wdenk8564acf2003-07-14 22:13:32 +0000142 case 0x0A00:
wdenk4b9206e2004-03-23 22:14:11 +0000143 puts ("0.0 0K49M");
wdenk8564acf2003-07-14 22:13:32 +0000144 break;
145 case 0x0A01:
wdenk4b9206e2004-03-23 22:14:11 +0000146 puts ("0.1 1K49M");
wdenk8564acf2003-07-14 22:13:32 +0000147 break;
wdenke1599e82004-10-10 23:27:33 +0000148 case 0x0A10:
149 puts ("1.0 1K49M");
150 break;
wdenk04a85b32004-04-15 18:22:41 +0000151 case 0x0C00:
wdenke1599e82004-10-10 23:27:33 +0000152 puts ("0.0 0K50M");
153 break;
154 case 0x0C10:
Wolfgang Denkd980a162005-08-06 02:03:03 +0200155 puts ("1.0 1K50M");
wdenke1599e82004-10-10 23:27:33 +0000156 break;
wdenk04a85b32004-04-15 18:22:41 +0000157 case 0x0D00:
wdenke1599e82004-10-10 23:27:33 +0000158 puts ("0.0 0K50M");
159 break;
160 case 0x0D10:
Wolfgang Denkd980a162005-08-06 02:03:03 +0200161 puts ("1.0 1K50M");
wdenk04a85b32004-04-15 18:22:41 +0000162 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000163 default:
164 printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
165 break;
166 }
167
168 printf (") at %s MHz\n", strmhz (buf, clock));
169
170 return 0;
171}
172
173/* ------------------------------------------------------------------------- */
174/* configures a UPM by writing into the UPM RAM array */
175/* uses bank 11 and a dummy physical address (=BRx_BA_MSK) */
176/* NOTE: the physical address chosen must not overlap into any other area */
177/* mapped by the memory controller because bank 11 has the lowest priority */
178
179void upmconfig (uint upm, uint * table, uint size)
180{
181 volatile immap_t *immap = (immap_t *) CFG_IMMR;
182 volatile memctl8260_t *memctl = &immap->im_memctl;
183 volatile uchar *dummy = (uchar *) BRx_BA_MSK; /* set all BA bits */
184 uint i;
185
186 /* first set up bank 11 to reference the correct UPM at a dummy address */
187
188 memctl->memc_or11 = ORxU_AM_MSK; /* set all AM bits */
189
190 switch (upm) {
191
192 case UPMA:
193 memctl->memc_br11 =
194 ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMA |
195 BRx_V;
196 memctl->memc_mamr = MxMR_OP_WARR;
197 break;
198
199 case UPMB:
200 memctl->memc_br11 =
201 ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMB |
202 BRx_V;
203 memctl->memc_mbmr = MxMR_OP_WARR;
204 break;
205
206 case UPMC:
207 memctl->memc_br11 =
208 ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMC |
209 BRx_V;
210 memctl->memc_mcmr = MxMR_OP_WARR;
211 break;
212
213 default:
214 panic ("upmconfig passed invalid UPM number (%u)\n", upm);
215 break;
216
217 }
218
219 /*
220 * at this point, the dummy address is set up to access the selected UPM,
221 * the MAD pointer is zero, and the MxMR OP is set for writing to RAM
222 *
223 * now we simply load the mdr with each word and poke the dummy address.
224 * the MAD is incremented on each access.
225 */
226
227 for (i = 0; i < size; i++) {
228 memctl->memc_mdr = table[i];
229 *dummy = 0;
230 }
231
232 /* now kill bank 11 */
233 memctl->memc_br11 = 0;
234}
235
236/* ------------------------------------------------------------------------- */
237
wdenkba91e262005-05-30 23:55:42 +0000238#if !defined(CONFIG_HAVE_OWN_RESET)
wdenk4a9cbbe2002-08-27 09:48:53 +0000239int
wdenk8bde7f72003-06-27 21:31:46 +0000240do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +0000241{
242 ulong msr, addr;
243
244 volatile immap_t *immap = (immap_t *) CFG_IMMR;
245
246 immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */
247
248 /* Interrupts and MMU off */
249 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
250
251 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
252 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
253
254 /*
255 * Trying to execute the next instruction at a non-existing address
256 * should cause a machine check, resulting in reset
257 */
258#ifdef CFG_RESET_ADDRESS
259 addr = CFG_RESET_ADDRESS;
260#else
261 /*
262 * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
263 * - sizeof (ulong) is usually a valid address. Better pick an address
264 * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
265 */
266 addr = CFG_MONITOR_BASE - sizeof (ulong);
267#endif
268 ((void (*)(void)) addr) ();
269 return 1;
270
271}
wdenkba91e262005-05-30 23:55:42 +0000272#endif /* CONFIG_HAVE_OWN_RESET */
wdenk4a9cbbe2002-08-27 09:48:53 +0000273
274/* ------------------------------------------------------------------------- */
275
276/*
277 * Get timebase clock frequency (like cpu_clk in Hz)
278 *
279 */
280unsigned long get_tbclk (void)
281{
wdenk4a9cbbe2002-08-27 09:48:53 +0000282 ulong tbclk;
283
284 tbclk = (gd->bus_clk + 3L) / 4L;
285
286 return (tbclk);
287}
288
289/* ------------------------------------------------------------------------- */
290
291#if defined(CONFIG_WATCHDOG)
292void watchdog_reset (void)
293{
294 int re_enable = disable_interrupts ();
295
296 reset_8260_watchdog ((immap_t *) CFG_IMMR);
297 if (re_enable)
298 enable_interrupts ();
299}
300#endif /* CONFIG_WATCHDOG */
301
302/* ------------------------------------------------------------------------- */
Marian Balakowicz75d3e8f2008-02-21 17:20:18 +0100303#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
Sergej Stepanovc9e7b9b2007-10-17 11:13:51 +0200304void ft_cpu_setup (void *blob, bd_t *bd)
305{
306 char * cpu_path = "/cpus/" OF_CPU;
307
Esben Haabendalee4ae382008-06-18 11:03:57 +0200308#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
309 defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
Kumar Galaba37aa02008-08-19 15:41:18 -0500310 fdt_fixup_ethernet(blob);
Esben Haabendalee4ae382008-06-18 11:03:57 +0200311#endif
312
Kumar Galae93becf2007-11-03 19:46:28 -0500313 do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
314 do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
315 do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
Sergej Stepanovc9e7b9b2007-10-17 11:13:51 +0200316}
317#endif /* CONFIG_OF_LIBFDT */