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wdenkc6097192002-11-03 00:24:07 +00001/*
stroese6f4474e2003-03-20 15:31:19 +00002 * (C) Copyright 2001-2003
wdenkc6097192002-11-03 00:24:07 +00003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
wdenkc6097192002-11-03 00:24:07 +000023#include <common.h>
Matthias Fuchs600fe462009-01-02 12:18:12 +010024#include <libfdt.h>
25#include <fdt_support.h>
wdenkc6097192002-11-03 00:24:07 +000026#include <asm/processor.h>
Matthias Fuchs6f35c532007-06-24 17:41:21 +020027#include <asm/io.h>
wdenkc6097192002-11-03 00:24:07 +000028#include <command.h>
wdenkc6097192002-11-03 00:24:07 +000029#include <malloc.h>
stroese87663b12004-12-16 18:27:05 +000030#include <net.h>
Matthias Fuchs6f35c532007-06-24 17:41:21 +020031#include <pci.h>
wdenkc6097192002-11-03 00:24:07 +000032
Wolfgang Denkd87080b2006-03-31 18:32:53 +020033DECLARE_GLOBAL_DATA_PTR;
34
Matthias Fuchsf6a1f492009-01-02 12:17:36 +010035extern void __ft_board_setup(void *blob, bd_t *bd);
36
37#undef FPGA_DEBUG
wdenkc6097192002-11-03 00:24:07 +000038
39/* fpga configuration data - generated by bin2cc */
40const unsigned char fpgadata[] =
41{
Matthias Fuchsf6a1f492009-01-02 12:17:36 +010042#if defined(CONFIG_CPCI405_VER2)
43# if defined(CONFIG_CPCI405AB)
stroesed4629c82003-05-23 11:30:39 +000044# include "fpgadata_cpci405ab.c"
45# else
46# include "fpgadata_cpci4052.c"
47# endif
wdenkc6097192002-11-03 00:24:07 +000048#else
49# include "fpgadata_cpci405.c"
50#endif
51};
52
53/*
54 * include common fpga code (for esd boards)
55 */
56#include "../common/fpga.c"
stroese87663b12004-12-16 18:27:05 +000057#include "../common/auto_update.h"
58
Matthias Fuchsf6a1f492009-01-02 12:17:36 +010059#if defined(CONFIG_CPCI405AB)
stroese87663b12004-12-16 18:27:05 +000060au_image_t au_image[] = {
61 {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
62 {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
63 {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
64 {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
65 {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
66};
67#else
Matthias Fuchsf6a1f492009-01-02 12:17:36 +010068#if defined(CONFIG_CPCI405_VER2)
stroese87663b12004-12-16 18:27:05 +000069au_image_t au_image[] = {
70 {"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
71 {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
72 {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
73 {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
74 {"cpci4052/postinst.img", 0, 0, AU_SCRIPT},
75};
76#else
77au_image_t au_image[] = {
78 {"cpci405/preinst.img", 0, -1, AU_SCRIPT},
79 {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR},
80 {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR},
81 {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE},
82 {"cpci405/postinst.img", 0, 0, AU_SCRIPT},
83};
84#endif
85#endif
86
87int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
88
wdenkc6097192002-11-03 00:24:07 +000089/* Prototypes */
stroese6f4474e2003-03-20 15:31:19 +000090int cpci405_version(void);
stroese87663b12004-12-16 18:27:05 +000091void lxt971_no_sleep(void);
wdenkc6097192002-11-03 00:24:07 +000092
Matthias Fuchsf6a1f492009-01-02 12:17:36 +010093int board_early_init_f(void)
wdenkc6097192002-11-03 00:24:07 +000094{
95#ifndef CONFIG_CPCI405_VER2
96 int index, len, i;
97 int status;
98#endif
99
100#ifdef FPGA_DEBUG
wdenkc6097192002-11-03 00:24:07 +0000101 /* set up serial port with default baudrate */
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100102 (void)get_clocks();
wdenkc6097192002-11-03 00:24:07 +0000103 gd->baudrate = CONFIG_BAUDRATE;
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100104 serial_init();
wdenkc6097192002-11-03 00:24:07 +0000105 console_init_f();
106#endif
107
108 /*
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100109 * First pull fpga-prg pin low,
110 * to disable fpga logic (on version 2 board)
wdenkc6097192002-11-03 00:24:07 +0000111 */
Matthias Fuchs049216f2009-02-20 10:19:18 +0100112 out_be32((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
113 out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
114 out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
115 out_be32((void *)GPIO0_OR, 0); /* pull prg low */
wdenkc6097192002-11-03 00:24:07 +0000116
117 /*
118 * Boot onboard FPGA
119 */
120#ifndef CONFIG_CPCI405_VER2
stroese6f4474e2003-03-20 15:31:19 +0000121 if (cpci405_version() == 1) {
wdenkc6097192002-11-03 00:24:07 +0000122 status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
123 if (status != 0) {
124 /* booting FPGA failed */
125#ifndef FPGA_DEBUG
wdenkc6097192002-11-03 00:24:07 +0000126 /* set up serial port with default baudrate */
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100127 (void)get_clocks();
wdenkc6097192002-11-03 00:24:07 +0000128 gd->baudrate = CONFIG_BAUDRATE;
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100129 serial_init();
wdenkc6097192002-11-03 00:24:07 +0000130 console_init_f();
131#endif
132 printf("\nFPGA: Booting failed ");
133 switch (status) {
134 case ERROR_FPGA_PRG_INIT_LOW:
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100135 printf("(Timeout: INIT not low after "
136 "asserting PROGRAM*)\n ");
wdenkc6097192002-11-03 00:24:07 +0000137 break;
138 case ERROR_FPGA_PRG_INIT_HIGH:
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100139 printf("(Timeout: INIT not high after "
140 "deasserting PROGRAM*)\n ");
wdenkc6097192002-11-03 00:24:07 +0000141 break;
142 case ERROR_FPGA_PRG_DONE:
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100143 printf("(Timeout: DONE not high after "
144 "programming FPGA)\n ");
wdenkc6097192002-11-03 00:24:07 +0000145 break;
146 }
147
148 /* display infos on fpgaimage */
149 index = 15;
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100150 for (i = 0; i < 4; i++) {
wdenkc6097192002-11-03 00:24:07 +0000151 len = fpgadata[index];
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100152 printf("FPGA: %s\n", &(fpgadata[index + 1]));
153 index += len + 3;
wdenkc6097192002-11-03 00:24:07 +0000154 }
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100155 putc('\n');
wdenkc6097192002-11-03 00:24:07 +0000156 /* delayed reboot */
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100157 for (i = 20; i > 0; i--) {
wdenkc6097192002-11-03 00:24:07 +0000158 printf("Rebooting in %2d seconds \r",i);
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100159 for (index = 0; index < 1000; index++)
wdenkc6097192002-11-03 00:24:07 +0000160 udelay(1000);
161 }
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100162 putc('\n');
wdenkc6097192002-11-03 00:24:07 +0000163 do_reset(NULL, 0, 0, NULL);
164 }
165 }
166#endif /* !CONFIG_CPCI405_VER2 */
167
168 /*
169 * IRQ 0-15 405GP internally generated; active high; level sensitive
170 * IRQ 16 405GP internally generated; active low; level sensitive
171 * IRQ 17-24 RESERVED
172 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100173 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
wdenkc6097192002-11-03 00:24:07 +0000174 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
175 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
176 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
177 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
178 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
179 */
Stefan Roese952e7762009-09-24 09:55:50 +0200180 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
181 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
182 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100183#if defined(CONFIG_CPCI405_6U)
stroese6f4474e2003-03-20 15:31:19 +0000184 if (cpci405_version() == 3) {
Stefan Roese952e7762009-09-24 09:55:50 +0200185 mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */
stroese6f4474e2003-03-20 15:31:19 +0000186 } else {
Stefan Roese952e7762009-09-24 09:55:50 +0200187 mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
stroese6f4474e2003-03-20 15:31:19 +0000188 }
Matthias Fuchs6f35c532007-06-24 17:41:21 +0200189#else
Stefan Roese952e7762009-09-24 09:55:50 +0200190 mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
Matthias Fuchs6f35c532007-06-24 17:41:21 +0200191#endif
Stefan Roese952e7762009-09-24 09:55:50 +0200192 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
193 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100194 * INT0 highest priority */
Stefan Roese952e7762009-09-24 09:55:50 +0200195 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
wdenkc6097192002-11-03 00:24:07 +0000196
197 return 0;
198}
199
wdenkc6097192002-11-03 00:24:07 +0000200int ctermm2(void)
201{
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100202#if defined(CONFIG_CPCI405_VER2)
Wolfgang Denk4ef218f2007-07-10 00:01:28 +0200203 return 0; /* no, board is cpci405 */
wdenkc6097192002-11-03 00:24:07 +0000204#else
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100205 if ((in_8((void*)0xf0000400) == 0x00) &&
206 (in_8((void*)0xf0000401) == 0x01))
Wolfgang Denk4ef218f2007-07-10 00:01:28 +0200207 return 0; /* no, board is cpci405 */
wdenkc6097192002-11-03 00:24:07 +0000208 else
Wolfgang Denk4ef218f2007-07-10 00:01:28 +0200209 return -1; /* yes, board is cterm-m2 */
wdenkc6097192002-11-03 00:24:07 +0000210#endif
211}
212
wdenkc6097192002-11-03 00:24:07 +0000213int cpci405_host(void)
214{
Stefan Roesed1c3b272009-09-09 16:25:29 +0200215 if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
Wolfgang Denk4ef218f2007-07-10 00:01:28 +0200216 return -1; /* yes, board is cpci405 host */
wdenkc6097192002-11-03 00:24:07 +0000217 else
Wolfgang Denk4ef218f2007-07-10 00:01:28 +0200218 return 0; /* no, board is cpci405 adapter */
wdenkc6097192002-11-03 00:24:07 +0000219}
220
stroese6f4474e2003-03-20 15:31:19 +0000221int cpci405_version(void)
wdenkc6097192002-11-03 00:24:07 +0000222{
Stefan Roesed1c3b272009-09-09 16:25:29 +0200223 unsigned long CPC0_CR0Reg;
wdenkc6097192002-11-03 00:24:07 +0000224 unsigned long value;
225
226 /*
stroese6f4474e2003-03-20 15:31:19 +0000227 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
wdenkc6097192002-11-03 00:24:07 +0000228 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200229 CPC0_CR0Reg = mfdcr(CPC0_CR0);
230 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
Matthias Fuchs6f35c532007-06-24 17:41:21 +0200231 out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
232 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100233 udelay(1000); /* wait some time before reading input */
234 value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
wdenkc6097192002-11-03 00:24:07 +0000235
236 /*
stroese6f4474e2003-03-20 15:31:19 +0000237 * Restore GPIO settings
wdenkc6097192002-11-03 00:24:07 +0000238 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200239 mtdcr(CPC0_CR0, CPC0_CR0Reg);
wdenkc6097192002-11-03 00:24:07 +0000240
stroese6f4474e2003-03-20 15:31:19 +0000241 switch (value) {
242 case 0x00180000:
243 /* CS2==1 && CS3==1 -> version 1 */
244 return 1;
245 case 0x00080000:
246 /* CS2==0 && CS3==1 -> version 2 */
247 return 2;
248 case 0x00100000:
Matthias Fuchs6f35c532007-06-24 17:41:21 +0200249 /* CS2==1 && CS3==0 -> version 3 or 6U board */
stroese6f4474e2003-03-20 15:31:19 +0000250 return 3;
251 case 0x00000000:
252 /* CS2==0 && CS3==0 -> version 4 */
253 return 4;
254 default:
255 /* should not be reached! */
256 return 2;
257 }
wdenkc6097192002-11-03 00:24:07 +0000258}
259
wdenkc6097192002-11-03 00:24:07 +0000260int misc_init_r (void)
261{
Stefan Roesed1c3b272009-09-09 16:25:29 +0200262 unsigned long CPC0_CR0Reg;
wdenkc6097192002-11-03 00:24:07 +0000263
stroese87663b12004-12-16 18:27:05 +0000264 /* adjust flash start and offset */
265 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
266 gd->bd->bi_flashoffset = 0;
267
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100268#if defined(CONFIG_CPCI405_VER2)
stroese87663b12004-12-16 18:27:05 +0000269 {
wdenkc6097192002-11-03 00:24:07 +0000270 unsigned char *dst;
271 ulong len = sizeof(fpgadata);
272 int status;
273 int index;
274 int i;
wdenkc6097192002-11-03 00:24:07 +0000275
276 /*
277 * On CPCI-405 version 2 the environment is saved in eeprom!
278 * FPGA can be gzip compressed (malloc) and booted this late.
279 */
stroese6f4474e2003-03-20 15:31:19 +0000280 if (cpci405_version() >= 2) {
wdenkc6097192002-11-03 00:24:07 +0000281 /*
282 * Setup GPIO pins (CS6+CS7 as GPIO)
283 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200284 CPC0_CR0Reg = mfdcr(CPC0_CR0);
285 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
wdenkc6097192002-11-03 00:24:07 +0000286
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100288 if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
289 (uchar *)fpgadata, &len) != 0) {
290 printf("GUNZIP ERROR - must RESET board to recover\n");
291 do_reset(NULL, 0, 0, NULL);
wdenkc6097192002-11-03 00:24:07 +0000292 }
293
294 status = fpga_boot(dst, len);
295 if (status != 0) {
296 printf("\nFPGA: Booting failed ");
297 switch (status) {
298 case ERROR_FPGA_PRG_INIT_LOW:
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100299 printf("(Timeout: INIT not low after "
300 "asserting PROGRAM*)\n ");
wdenkc6097192002-11-03 00:24:07 +0000301 break;
302 case ERROR_FPGA_PRG_INIT_HIGH:
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100303 printf("(Timeout: INIT not high after "
304 "deasserting PROGRAM*)\n ");
wdenkc6097192002-11-03 00:24:07 +0000305 break;
306 case ERROR_FPGA_PRG_DONE:
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100307 printf("(Timeout: DONE not high after "
308 "programming FPGA)\n ");
wdenkc6097192002-11-03 00:24:07 +0000309 break;
310 }
311
312 /* display infos on fpgaimage */
313 index = 15;
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100314 for (i = 0; i < 4; i++) {
wdenkc6097192002-11-03 00:24:07 +0000315 len = dst[index];
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100316 printf("FPGA: %s\n", &(dst[index + 1]));
317 index += len + 3;
wdenkc6097192002-11-03 00:24:07 +0000318 }
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100319 putc('\n');
wdenkc6097192002-11-03 00:24:07 +0000320 /* delayed reboot */
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100321 for (i = 20; i > 0; i--) {
322 printf("Rebooting in %2d seconds \r", i);
323 for (index = 0; index < 1000; index++)
wdenkc6097192002-11-03 00:24:07 +0000324 udelay(1000);
325 }
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100326 putc('\n');
wdenkc6097192002-11-03 00:24:07 +0000327 do_reset(NULL, 0, 0, NULL);
328 }
329
330 /* restore gpio/cs settings */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200331 mtdcr(CPC0_CR0, CPC0_CR0Reg);
wdenkc6097192002-11-03 00:24:07 +0000332
333 puts("FPGA: ");
334
335 /* display infos on fpgaimage */
336 index = 15;
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100337 for (i = 0; i < 4; i++) {
wdenkc6097192002-11-03 00:24:07 +0000338 len = dst[index];
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100339 printf("%s ", &(dst[index + 1]));
340 index += len + 3;
wdenkc6097192002-11-03 00:24:07 +0000341 }
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100342 putc('\n');
wdenkc6097192002-11-03 00:24:07 +0000343
344 free(dst);
stroese6f4474e2003-03-20 15:31:19 +0000345
346 /*
347 * Reset FPGA via FPGA_DATA pin
348 */
349 SET_FPGA(FPGA_PRG | FPGA_CLK);
350 udelay(1000); /* wait 1ms */
351 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
352 udelay(1000); /* wait 1ms */
353
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100354#if defined(CONFIG_CPCI405_6U)
355#error HIER GETH ES WEITER MIT IO ACCESSORS
stroese6f4474e2003-03-20 15:31:19 +0000356 if (cpci405_version() == 3) {
stroese6f4474e2003-03-20 15:31:19 +0000357 /*
358 * Enable outputs in fpga on version 3 board
359 */
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100360 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
361 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
362 CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
stroese6f4474e2003-03-20 15:31:19 +0000363
364 /*
365 * Set outputs to 0
366 */
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100367 out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
stroese6f4474e2003-03-20 15:31:19 +0000368
369 /*
370 * Reset external DUART
371 */
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100372 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
373 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
374 CONFIG_SYS_FPGA_MODE_DUART_RESET);
stroese6f4474e2003-03-20 15:31:19 +0000375 udelay(100);
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100376 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
377 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
378 ~CONFIG_SYS_FPGA_MODE_DUART_RESET);
stroese6f4474e2003-03-20 15:31:19 +0000379 }
Matthias Fuchs6f35c532007-06-24 17:41:21 +0200380#endif
wdenkc6097192002-11-03 00:24:07 +0000381 }
382 else {
stroese6f4474e2003-03-20 15:31:19 +0000383 puts("\n*** U-Boot Version does not match Board Version!\n");
384 puts("*** CPCI-405 Version 1.x detected!\n");
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100385 puts("*** Please use correct U-Boot version "
386 "(CPCI405 instead of CPCI4052)!\n\n");
wdenkc6097192002-11-03 00:24:07 +0000387 }
stroese87663b12004-12-16 18:27:05 +0000388 }
wdenkc6097192002-11-03 00:24:07 +0000389#else /* CONFIG_CPCI405_VER2 */
stroese6f4474e2003-03-20 15:31:19 +0000390 if (cpci405_version() >= 2) {
391 puts("\n*** U-Boot Version does not match Board Version!\n");
392 puts("*** CPCI-405 Board Version 2.x detected!\n");
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100393 puts("*** Please use correct U-Boot version "
394 "(CPCI4052 instead of CPCI405)!\n\n");
wdenkc6097192002-11-03 00:24:07 +0000395 }
wdenkc6097192002-11-03 00:24:07 +0000396#endif /* CONFIG_CPCI405_VER2 */
397
398 /*
stroeseafcc4a72003-04-04 16:52:57 +0000399 * Select cts (and not dsr) on uart1
400 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200401 CPC0_CR0Reg = mfdcr(CPC0_CR0);
402 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
stroeseafcc4a72003-04-04 16:52:57 +0000403
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100404 return 0;
wdenkc6097192002-11-03 00:24:07 +0000405}
406
wdenkc6097192002-11-03 00:24:07 +0000407/*
408 * Check Board Identity:
409 */
410
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100411int checkboard(void)
wdenkc6097192002-11-03 00:24:07 +0000412{
413#ifndef CONFIG_CPCI405_VER2
414 int index;
415 int len;
416#endif
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200417 char str[64];
Wolfgang Denkcdb74972010-07-24 21:55:43 +0200418 int i = getenv_f("serial#", str, sizeof(str));
stroese6f4474e2003-03-20 15:31:19 +0000419 unsigned short ver;
wdenkc6097192002-11-03 00:24:07 +0000420
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100421 puts("Board: ");
wdenkc6097192002-11-03 00:24:07 +0000422
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100423 if (i == -1)
424 puts("### No HW ID - assuming CPCI405");
425 else
wdenkc6097192002-11-03 00:24:07 +0000426 puts(str);
wdenkc6097192002-11-03 00:24:07 +0000427
stroese6f4474e2003-03-20 15:31:19 +0000428 ver = cpci405_version();
429 printf(" (Ver %d.x, ", ver);
wdenkc6097192002-11-03 00:24:07 +0000430
wdenkc6097192002-11-03 00:24:07 +0000431 if (ctermm2()) {
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200432 char str[4];
stroese1b554402003-09-12 08:44:46 +0000433
434 /*
435 * Read board-id and save in env-variable
436 */
437 sprintf(str, "%d", *(unsigned char *)0xf0000400);
438 setenv("boardid", str);
439 printf("CTERM-M2 - Id=%s)", str);
wdenkc6097192002-11-03 00:24:07 +0000440 } else {
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100441 if (cpci405_host())
442 puts("PCI Host Version)");
443 else
444 puts("PCI Adapter Version)");
wdenkc6097192002-11-03 00:24:07 +0000445 }
446
447#ifndef CONFIG_CPCI405_VER2
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100448 puts("\nFPGA: ");
wdenkc6097192002-11-03 00:24:07 +0000449
450 /* display infos on fpgaimage */
451 index = 15;
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100452 for (i = 0; i < 4; i++) {
wdenkc6097192002-11-03 00:24:07 +0000453 len = fpgadata[index];
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100454 printf("%s ", &(fpgadata[index + 1]));
455 index += len + 3;
wdenkc6097192002-11-03 00:24:07 +0000456 }
457#endif
458
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100459 putc('\n');
wdenkc6097192002-11-03 00:24:07 +0000460 return 0;
461}
462
Matthias Fuchs6f35c532007-06-24 17:41:21 +0200463void reset_phy(void)
wdenkc6097192002-11-03 00:24:07 +0000464{
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100465#if defined(CONFIG_LXT971_NO_SLEEP)
wdenkc6097192002-11-03 00:24:07 +0000466
Matthias Fuchs6f35c532007-06-24 17:41:21 +0200467 /*
468 * Disable sleep mode in LXT971
469 */
470 lxt971_no_sleep();
471#endif
wdenkc6097192002-11-03 00:24:07 +0000472}
473
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100474#if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
wdenkc6097192002-11-03 00:24:07 +0000475void ide_set_reset(int on)
476{
wdenkc6097192002-11-03 00:24:07 +0000477 /*
478 * Assert or deassert CompactFlash Reset Pin
479 */
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100480 if (on) { /* assert RESET */
481 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
482 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
483 ~CONFIG_SYS_FPGA_MODE_CF_RESET);
484 } else { /* release RESET */
485 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
486 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
487 CONFIG_SYS_FPGA_MODE_CF_RESET);
wdenkc6097192002-11-03 00:24:07 +0000488 }
489}
490
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100491#endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
wdenkc6097192002-11-03 00:24:07 +0000492
Stefan Roese466fff12007-06-25 15:57:39 +0200493#if defined(CONFIG_PCI)
Matthias Fuchs6f35c532007-06-24 17:41:21 +0200494void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
495{
496 unsigned char int_line = 0xff;
497
498 /*
499 * Write pci interrupt line register (cpci405 specific)
500 */
501 switch (PCI_DEV(dev) & 0x03) {
502 case 0:
503 int_line = 27 + 2;
504 break;
505 case 1:
506 int_line = 27 + 3;
507 break;
508 case 2:
509 int_line = 27 + 0;
510 break;
511 case 3:
512 int_line = 27 + 1;
513 break;
514 }
515
516 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
517}
518
519int pci_pre_init(struct pci_controller *hose)
520{
521 hose->fixup_irq = cpci405_pci_fixup_irq;
522 return 1;
523}
Stefan Roese466fff12007-06-25 15:57:39 +0200524#endif /* defined(CONFIG_PCI) */
Matthias Fuchs6f35c532007-06-24 17:41:21 +0200525
Matthias Fuchs600fe462009-01-02 12:18:12 +0100526#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
527void ft_board_setup(void *blob, bd_t *bd)
528{
529 int rc;
530
531 __ft_board_setup(blob, bd);
532
533 /*
534 * Disable PCI in adapter mode.
535 */
536 if (!cpci405_host()) {
537 rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
538 "disabled", sizeof("disabled"), 1);
539 if (rc) {
540 printf("Unable to update property status in PCI node, "
541 "err=%s\n",
542 fdt_strerror(rc));
543 }
544 }
545}
546#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
547
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100548#if defined(CONFIG_CPCI405AB)
549#define ONE_WIRE_CLEAR out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
550 CONFIG_SYS_FPGA_MODE), \
551 in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
552 CONFIG_SYS_FPGA_MODE)) | \
553 CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
Matthias Fuchs6f35c532007-06-24 17:41:21 +0200554
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100555#define ONE_WIRE_SET out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
556 CONFIG_SYS_FPGA_MODE), \
557 in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
558 CONFIG_SYS_FPGA_MODE)) & \
559 ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
stroese1b554402003-09-12 08:44:46 +0000560
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100561#define ONE_WIRE_GET (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
562 CONFIG_SYS_FPGA_STATUS)) & \
563 CONFIG_SYS_FPGA_MODE_1WIRE)
stroese1b554402003-09-12 08:44:46 +0000564
565/*
566 * Generate a 1-wire reset, return 1 if no presence detect was found,
567 * return 0 otherwise.
568 * (NOTE: Does not handle alarm presence from DS2404/DS1994)
569 */
570int OWTouchReset(void)
stroesed4629c82003-05-23 11:30:39 +0000571{
stroese1b554402003-09-12 08:44:46 +0000572 int result;
stroesed4629c82003-05-23 11:30:39 +0000573
stroese1b554402003-09-12 08:44:46 +0000574 ONE_WIRE_CLEAR;
575 udelay(480);
576 ONE_WIRE_SET;
577 udelay(70);
stroesed4629c82003-05-23 11:30:39 +0000578
stroese1b554402003-09-12 08:44:46 +0000579 result = ONE_WIRE_GET;
580
581 udelay(410);
582 return result;
stroesed4629c82003-05-23 11:30:39 +0000583}
584
stroese1b554402003-09-12 08:44:46 +0000585/*
586 * Send 1 a 1-wire write bit.
587 * Provide 10us recovery time.
588 */
589void OWWriteBit(int bit)
stroesed4629c82003-05-23 11:30:39 +0000590{
stroese1b554402003-09-12 08:44:46 +0000591 if (bit) {
592 /*
593 * write '1' bit
594 */
595 ONE_WIRE_CLEAR;
596 udelay(6);
597 ONE_WIRE_SET;
598 udelay(64);
599 } else {
600 /*
601 * write '0' bit
602 */
603 ONE_WIRE_CLEAR;
604 udelay(60);
605 ONE_WIRE_SET;
606 udelay(10);
stroesed4629c82003-05-23 11:30:39 +0000607 }
stroesed4629c82003-05-23 11:30:39 +0000608}
609
stroese1b554402003-09-12 08:44:46 +0000610/*
611 * Read a bit from the 1-wire bus and return it.
612 * Provide 10us recovery time.
613 */
614int OWReadBit(void)
615{
616 int result;
617
618 ONE_WIRE_CLEAR;
619 udelay(6);
620 ONE_WIRE_SET;
621 udelay(9);
622
623 result = ONE_WIRE_GET;
624
625 udelay(55);
626 return result;
627}
628
stroese1b554402003-09-12 08:44:46 +0000629void OWWriteByte(int data)
630{
631 int loop;
632
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100633 for (loop = 0; loop < 8; loop++) {
stroese1b554402003-09-12 08:44:46 +0000634 OWWriteBit(data & 0x01);
635 data >>= 1;
636 }
637}
638
stroese1b554402003-09-12 08:44:46 +0000639int OWReadByte(void)
640{
641 int loop, result = 0;
642
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100643 for (loop = 0; loop < 8; loop++) {
stroese1b554402003-09-12 08:44:46 +0000644 result >>= 1;
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100645 if (OWReadBit())
stroese1b554402003-09-12 08:44:46 +0000646 result |= 0x80;
stroese1b554402003-09-12 08:44:46 +0000647 }
648
649 return result;
650}
651
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200652int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
stroese1b554402003-09-12 08:44:46 +0000653{
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100654 unsigned short val;
stroese1b554402003-09-12 08:44:46 +0000655 int result;
656 int i;
657 unsigned char ow_id[6];
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200658 char str[32];
stroese1b554402003-09-12 08:44:46 +0000659 unsigned char ow_crc;
660
661 /*
662 * Clear 1-wire bit (open drain with pull-up)
663 */
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100664 val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
665 CONFIG_SYS_FPGA_MODE));
666 val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */
667 out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
668 CONFIG_SYS_FPGA_MODE), val);
stroese1b554402003-09-12 08:44:46 +0000669
670 result = OWTouchReset();
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100671 if (result != 0)
stroese1b554402003-09-12 08:44:46 +0000672 puts("No 1-wire device detected!\n");
stroese1b554402003-09-12 08:44:46 +0000673
674 OWWriteByte(0x33); /* send read rom command */
675 OWReadByte(); /* skip family code ( == 0x01) */
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100676 for (i = 0; i < 6; i++)
stroese1b554402003-09-12 08:44:46 +0000677 ow_id[i] = OWReadByte();
stroese1b554402003-09-12 08:44:46 +0000678 ow_crc = OWReadByte(); /* read crc */
679
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100680 sprintf(str, "%08X%04X",
681 *(unsigned int *)&ow_id[0],
682 *(unsigned short *)&ow_id[4]);
stroese1b554402003-09-12 08:44:46 +0000683 printf("Setting environment variable 'ow_id' to %s\n", str);
684 setenv("ow_id", str);
685
686 return 0;
687}
688U_BOOT_CMD(
689 onewire, 1, 1, do_onewire,
Peter Tyser2fb26042009-01-27 18:03:12 -0600690 "Read 1-write ID",
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200691 ""
692);
stroese1b554402003-09-12 08:44:46 +0000693
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100694#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
695#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
stroese87663b12004-12-16 18:27:05 +0000696
697/*
698 * Write backplane ip-address...
699 */
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200700int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
stroese87663b12004-12-16 18:27:05 +0000701{
stroese87663b12004-12-16 18:27:05 +0000702 bd_t *bd = gd->bd;
703 char *buf;
704 ulong crc;
705 char str[32];
706 char *ptr;
707 IPaddr_t ipaddr;
708
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200709 buf = malloc(CONFIG_ENV_SIZE_2);
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100710 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0,
711 (uchar *)buf, CONFIG_ENV_SIZE_2))
stroese87663b12004-12-16 18:27:05 +0000712 puts("\nError reading backplane EEPROM!\n");
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100713 else {
714 crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
stroese87663b12004-12-16 18:27:05 +0000715 if (crc != *(ulong *)buf) {
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100716 printf("ERROR: crc mismatch %08lx %08lx\n",
717 crc, *(ulong *)buf);
stroese87663b12004-12-16 18:27:05 +0000718 return -1;
719 }
720
721 /*
722 * Find bp_ip
723 */
724 ptr = strstr(buf+4, "bp_ip=");
725 if (ptr == NULL) {
726 printf("ERROR: bp_ip not found!\n");
727 return -1;
728 }
729 ptr += 6;
730 ipaddr = string_to_ip(ptr);
731
732 /*
733 * Update whole ip-addr
734 */
735 bd->bi_ip_addr = ipaddr;
736 sprintf(str, "%ld.%ld.%ld.%ld",
737 (bd->bi_ip_addr & 0xff000000) >> 24,
738 (bd->bi_ip_addr & 0x00ff0000) >> 16,
739 (bd->bi_ip_addr & 0x0000ff00) >> 8,
740 (bd->bi_ip_addr & 0x000000ff));
741 setenv("ipaddr", str);
742 printf("Updated ip_addr from bp_eeprom to %s!\n", str);
743 }
744
745 free(buf);
746
747 return 0;
748}
749U_BOOT_CMD(
750 getbpip, 1, 1, do_get_bpip,
Peter Tyser2fb26042009-01-27 18:03:12 -0600751 "Update IP-Address with Backplane IP-Address",
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200752 ""
753);
stroese87663b12004-12-16 18:27:05 +0000754
755/*
756 * Set and print backplane ip...
757 */
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200758int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
stroese87663b12004-12-16 18:27:05 +0000759{
760 char *buf;
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200761 char str[32];
stroese87663b12004-12-16 18:27:05 +0000762 ulong crc;
763
764 if (argc < 2) {
765 puts("ERROR!\n");
766 return -1;
767 }
768
769 printf("Setting bp_ip to %s\n", argv[1]);
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200770 buf = malloc(CONFIG_ENV_SIZE_2);
771 memset(buf, 0, CONFIG_ENV_SIZE_2);
stroese87663b12004-12-16 18:27:05 +0000772 sprintf(str, "bp_ip=%s", argv[1]);
773 strcpy(buf+4, str);
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100774 crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
stroese87663b12004-12-16 18:27:05 +0000775 *(ulong *)buf = crc;
776
Matthias Fuchsf6a1f492009-01-02 12:17:36 +0100777 if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2,
778 0, (uchar *)buf, CONFIG_ENV_SIZE_2))
stroese87663b12004-12-16 18:27:05 +0000779 puts("\nError writing backplane EEPROM!\n");
stroese87663b12004-12-16 18:27:05 +0000780
781 free(buf);
782
783 return 0;
784}
785U_BOOT_CMD(
786 setbpip, 2, 1, do_set_bpip,
Peter Tyser2fb26042009-01-27 18:03:12 -0600787 "Write Backplane IP-Address",
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200788 ""
789);
stroese87663b12004-12-16 18:27:05 +0000790
stroese1b554402003-09-12 08:44:46 +0000791#endif /* CONFIG_CPCI405AB */