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wdenk5da627a2003-10-09 20:09:04 +00001/* Only eth0 supported for now
2 *
3 * (C) Copyright 2003
4 * Thomas.Lange@corelatus.se
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenk5da627a2003-10-09 20:09:04 +00007 */
8#include <config.h>
9
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020010#if defined(CONFIG_SYS_DISCOVER_PHY)
Wolfgang Denk265817c2005-09-25 00:53:22 +020011#error "PHY not supported yet"
wdenk5da627a2003-10-09 20:09:04 +000012/* We just assume that we are running 100FD for now */
13/* We all use switches, right? ;-) */
14#endif
15
wdenka2663ea2003-12-07 18:32:37 +000016/* I assume ethernet behaves like au1000 */
17
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090018#ifdef CONFIG_SOC_AU1000
wdenk5da627a2003-10-09 20:09:04 +000019/* Base address differ between cpu:s */
20#define ETH0_BASE AU1000_ETH0_BASE
21#define MAC0_ENABLE AU1000_MAC0_ENABLE
22#else
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090023#ifdef CONFIG_SOC_AU1100
wdenka2663ea2003-12-07 18:32:37 +000024#define ETH0_BASE AU1100_ETH0_BASE
25#define MAC0_ENABLE AU1100_MAC0_ENABLE
26#else
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090027#ifdef CONFIG_SOC_AU1500
wdenka2663ea2003-12-07 18:32:37 +000028#define ETH0_BASE AU1500_ETH0_BASE
29#define MAC0_ENABLE AU1500_MAC0_ENABLE
30#else
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090031#ifdef CONFIG_SOC_AU1550
wdenkff36fd82005-01-09 22:28:56 +000032#define ETH0_BASE AU1550_ETH0_BASE
33#define MAC0_ENABLE AU1550_MAC0_ENABLE
34#else
wdenka2663ea2003-12-07 18:32:37 +000035#error "No valid cpu set"
36#endif
37#endif
wdenk5da627a2003-10-09 20:09:04 +000038#endif
wdenkff36fd82005-01-09 22:28:56 +000039#endif
wdenk5da627a2003-10-09 20:09:04 +000040
41#include <common.h>
42#include <malloc.h>
43#include <net.h>
44#include <command.h>
45#include <asm/io.h>
46#include <asm/au1x00.h>
47
Jon Loeliger44312832007-07-09 19:06:00 -050048#if defined(CONFIG_CMD_MII)
Marian Balakowicz63ff0042005-10-28 22:30:33 +020049#include <miiphy.h>
50#endif
51
wdenk5da627a2003-10-09 20:09:04 +000052/* Ethernet Transmit and Receive Buffers */
53#define DBUF_LENGTH 1520
54#define PKT_MAXBUF_SIZE 1518
55
56static char txbuf[DBUF_LENGTH];
57
58static int next_tx;
59static int next_rx;
60
61/* 4 rx and 4 tx fifos */
62#define NO_OF_FIFOS 4
63
64typedef struct{
65 u32 status;
66 u32 addr;
67 u32 len; /* Only used for tx */
68 u32 not_used;
69} mac_fifo_t;
70
71mac_fifo_t mac_fifo[NO_OF_FIFOS];
72
73#define MAX_WAIT 1000
74
Shinya Kuribayashif0132042007-10-27 15:00:25 +090075#if defined(CONFIG_CMD_MII)
Mike Frysinger5700bb62010-07-27 18:35:08 -040076int au1x00_miiphy_read(const char *devname, unsigned char addr,
Shinya Kuribayashif0132042007-10-27 15:00:25 +090077 unsigned char reg, unsigned short * value)
78{
79 volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
80 volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
81 u32 mii_control;
82 unsigned int timedout = 20;
83
84 while (*mii_control_reg & MAC_MII_BUSY) {
85 udelay(1000);
86 if (--timedout == 0) {
87 printf("au1x00_eth: miiphy_read busy timeout!!\n");
88 return -1;
89 }
90 }
91
92 mii_control = MAC_SET_MII_SELECT_REG(reg) |
93 MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
94
95 *mii_control_reg = mii_control;
96
97 timedout = 20;
98 while (*mii_control_reg & MAC_MII_BUSY) {
99 udelay(1000);
100 if (--timedout == 0) {
101 printf("au1x00_eth: miiphy_read busy timeout!!\n");
102 return -1;
103 }
104 }
105 *value = *mii_data_reg;
106 return 0;
107}
108
Mike Frysinger5700bb62010-07-27 18:35:08 -0400109int au1x00_miiphy_write(const char *devname, unsigned char addr,
Shinya Kuribayashif0132042007-10-27 15:00:25 +0900110 unsigned char reg, unsigned short value)
111{
112 volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
113 volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
114 u32 mii_control;
115 unsigned int timedout = 20;
116
117 while (*mii_control_reg & MAC_MII_BUSY) {
118 udelay(1000);
119 if (--timedout == 0) {
120 printf("au1x00_eth: miiphy_write busy timeout!!\n");
Shinya Kuribayashi4fbd0742007-10-27 15:22:33 +0900121 return -1;
Shinya Kuribayashif0132042007-10-27 15:00:25 +0900122 }
123 }
124
125 mii_control = MAC_SET_MII_SELECT_REG(reg) |
126 MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
127
128 *mii_data_reg = value;
129 *mii_control_reg = mii_control;
130 return 0;
131}
132#endif
133
Joe Hershberger10cbe3b2012-05-22 18:36:19 +0000134static int au1x00_send(struct eth_device *dev, void *packet, int length)
135{
wdenk5da627a2003-10-09 20:09:04 +0000136 volatile mac_fifo_t *fifo_tx =
137 (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
138 int i;
139 int res;
140
141 /* tx fifo should always be idle */
142 fifo_tx[next_tx].len = length;
143 fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
144 au_sync();
145
146 udelay(1);
147 i=0;
148 while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
149 if(i>MAX_WAIT){
150 printf("TX timeout\n");
151 break;
152 }
153 udelay(1);
154 i++;
155 }
156
157 /* Clear done bit */
158 fifo_tx[next_tx].addr = 0;
159 fifo_tx[next_tx].len = 0;
160 au_sync();
161
162 res = fifo_tx[next_tx].status;
163
164 next_tx++;
165 if(next_tx>=NO_OF_FIFOS){
166 next_tx=0;
167 }
168 return(res);
169}
170
171static int au1x00_recv(struct eth_device* dev){
172 volatile mac_fifo_t *fifo_rx =
173 (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
174
175 int length;
176 u32 status;
177
178 for(;;){
179 if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
180 /* Nothing has been received */
181 return(-1);
182 }
183
184 status = fifo_rx[next_rx].status;
185
186 length = status&0x3FFF;
187
188 if(status&RX_ERROR){
189 printf("Rx error 0x%x\n", status);
190 }
191 else{
192 /* Pass the packet up to the protocol layers. */
193 NetReceive(NetRxPackets[next_rx], length - 4);
194 }
195
196 fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE;
197
198 next_rx++;
199 if(next_rx>=NO_OF_FIFOS){
200 next_rx=0;
201 }
202 } /* for */
203
204 return(0); /* Does anyone use this? */
205}
206
207static int au1x00_init(struct eth_device* dev, bd_t * bd){
208
209 volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
210 volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
211 volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
212 volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
213 volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
214 volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
215 volatile mac_fifo_t *fifo_tx =
216 (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
217 volatile mac_fifo_t *fifo_rx =
218 (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
219 int i;
220
Wolfgang Denk4bc12f12005-09-24 22:05:40 +0200221 next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
222 next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);
wdenk5da627a2003-10-09 20:09:04 +0000223
224 /* We have to enable clocks before releasing reset */
225 *macen = MAC_EN_CLOCK_ENABLE;
226 udelay(10);
227
228 /* Enable MAC0 */
229 /* We have to release reset before accessing registers */
230 *macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
231 MAC_EN_RESET1|MAC_EN_RESET2;
232 udelay(10);
233
234 for(i=0;i<NO_OF_FIFOS;i++){
235 fifo_tx[i].len = 0;
236 fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
237 fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))|RX_DMA_ENABLE;
238 }
239
240 /* Put mac addr in little endian */
wdenk5da627a2003-10-09 20:09:04 +0000241#define ea eth_get_dev()->enetaddr
Wolfgang Denk265817c2005-09-25 00:53:22 +0200242 *mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
243 *mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
244 (ea[1] << 8) | (ea[0] ) ;
wdenk5da627a2003-10-09 20:09:04 +0000245#undef ea
wdenk5da627a2003-10-09 20:09:04 +0000246 *mac_mcast_low = 0;
247 *mac_mcast_high = 0;
248
wdenk63f34912004-01-02 15:01:32 +0000249 /* Make sure the MAC buffer is in the correct endian mode */
250#ifdef __LITTLE_ENDIAN
251 *mac_ctrl = MAC_FULL_DUPLEX;
252 udelay(1);
253 *mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
254#else
wdenk5da627a2003-10-09 20:09:04 +0000255 *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
256 udelay(1);
257 *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
wdenk63f34912004-01-02 15:01:32 +0000258#endif
wdenk5da627a2003-10-09 20:09:04 +0000259
260 return(1);
261}
262
263static void au1x00_halt(struct eth_device* dev){
Thomas Lange87423d72009-04-24 16:22:16 +0200264 volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
265
266 /* Put MAC0 in reset */
267 *macen = 0;
wdenk5da627a2003-10-09 20:09:04 +0000268}
269
270int au1x00_enet_initialize(bd_t *bis){
271 struct eth_device* dev;
272
Wolfgang Denk95515302006-03-13 01:00:22 +0100273 if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
274 puts ("malloc failed\n");
Shinya Kuribayashi5dfb3ee2008-10-19 12:08:50 +0900275 return -1;
Wolfgang Denk95515302006-03-13 01:00:22 +0100276 }
277
wdenk5da627a2003-10-09 20:09:04 +0000278 memset(dev, 0, sizeof *dev);
279
Wolfgang Denk95515302006-03-13 01:00:22 +0100280 sprintf(dev->name, "Au1X00 ethernet");
wdenk5da627a2003-10-09 20:09:04 +0000281 dev->iobase = 0;
282 dev->priv = 0;
283 dev->init = au1x00_init;
284 dev->halt = au1x00_halt;
285 dev->send = au1x00_send;
286 dev->recv = au1x00_recv;
287
288 eth_register(dev);
289
Jon Loeliger44312832007-07-09 19:06:00 -0500290#if defined(CONFIG_CMD_MII)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200291 miiphy_register(dev->name,
292 au1x00_miiphy_read, au1x00_miiphy_write);
293#endif
294
wdenk5da627a2003-10-09 20:09:04 +0000295 return 1;
296}
Daniel Schwierzeckd9a4a622015-01-29 14:47:01 +0100297
298int cpu_eth_init(bd_t *bis)
299{
300 au1x00_enet_initialize(bis);
301 return 0;
302}