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wdenk5da627a2003-10-09 20:09:04 +00001/* Only eth0 supported for now
2 *
3 * (C) Copyright 2003
4 * Thomas.Lange@corelatus.se
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Wolfgang Denk265817c2005-09-25 00:53:22 +020016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk5da627a2003-10-09 20:09:04 +000017 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24#include <config.h>
25
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020026#if defined(CONFIG_SYS_DISCOVER_PHY)
Wolfgang Denk265817c2005-09-25 00:53:22 +020027#error "PHY not supported yet"
wdenk5da627a2003-10-09 20:09:04 +000028/* We just assume that we are running 100FD for now */
29/* We all use switches, right? ;-) */
30#endif
31
wdenka2663ea2003-12-07 18:32:37 +000032/* I assume ethernet behaves like au1000 */
33
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090034#ifdef CONFIG_SOC_AU1000
wdenk5da627a2003-10-09 20:09:04 +000035/* Base address differ between cpu:s */
36#define ETH0_BASE AU1000_ETH0_BASE
37#define MAC0_ENABLE AU1000_MAC0_ENABLE
38#else
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090039#ifdef CONFIG_SOC_AU1100
wdenka2663ea2003-12-07 18:32:37 +000040#define ETH0_BASE AU1100_ETH0_BASE
41#define MAC0_ENABLE AU1100_MAC0_ENABLE
42#else
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090043#ifdef CONFIG_SOC_AU1500
wdenka2663ea2003-12-07 18:32:37 +000044#define ETH0_BASE AU1500_ETH0_BASE
45#define MAC0_ENABLE AU1500_MAC0_ENABLE
46#else
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090047#ifdef CONFIG_SOC_AU1550
wdenkff36fd82005-01-09 22:28:56 +000048#define ETH0_BASE AU1550_ETH0_BASE
49#define MAC0_ENABLE AU1550_MAC0_ENABLE
50#else
wdenka2663ea2003-12-07 18:32:37 +000051#error "No valid cpu set"
52#endif
53#endif
wdenk5da627a2003-10-09 20:09:04 +000054#endif
wdenkff36fd82005-01-09 22:28:56 +000055#endif
wdenk5da627a2003-10-09 20:09:04 +000056
57#include <common.h>
58#include <malloc.h>
59#include <net.h>
60#include <command.h>
61#include <asm/io.h>
62#include <asm/au1x00.h>
63
Jon Loeliger44312832007-07-09 19:06:00 -050064#if defined(CONFIG_CMD_MII)
Marian Balakowicz63ff0042005-10-28 22:30:33 +020065#include <miiphy.h>
66#endif
67
wdenk5da627a2003-10-09 20:09:04 +000068/* Ethernet Transmit and Receive Buffers */
69#define DBUF_LENGTH 1520
70#define PKT_MAXBUF_SIZE 1518
71
72static char txbuf[DBUF_LENGTH];
73
74static int next_tx;
75static int next_rx;
76
77/* 4 rx and 4 tx fifos */
78#define NO_OF_FIFOS 4
79
80typedef struct{
81 u32 status;
82 u32 addr;
83 u32 len; /* Only used for tx */
84 u32 not_used;
85} mac_fifo_t;
86
87mac_fifo_t mac_fifo[NO_OF_FIFOS];
88
89#define MAX_WAIT 1000
90
Shinya Kuribayashif0132042007-10-27 15:00:25 +090091#if defined(CONFIG_CMD_MII)
Mike Frysinger5700bb62010-07-27 18:35:08 -040092int au1x00_miiphy_read(const char *devname, unsigned char addr,
Shinya Kuribayashif0132042007-10-27 15:00:25 +090093 unsigned char reg, unsigned short * value)
94{
95 volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
96 volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
97 u32 mii_control;
98 unsigned int timedout = 20;
99
100 while (*mii_control_reg & MAC_MII_BUSY) {
101 udelay(1000);
102 if (--timedout == 0) {
103 printf("au1x00_eth: miiphy_read busy timeout!!\n");
104 return -1;
105 }
106 }
107
108 mii_control = MAC_SET_MII_SELECT_REG(reg) |
109 MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
110
111 *mii_control_reg = mii_control;
112
113 timedout = 20;
114 while (*mii_control_reg & MAC_MII_BUSY) {
115 udelay(1000);
116 if (--timedout == 0) {
117 printf("au1x00_eth: miiphy_read busy timeout!!\n");
118 return -1;
119 }
120 }
121 *value = *mii_data_reg;
122 return 0;
123}
124
Mike Frysinger5700bb62010-07-27 18:35:08 -0400125int au1x00_miiphy_write(const char *devname, unsigned char addr,
Shinya Kuribayashif0132042007-10-27 15:00:25 +0900126 unsigned char reg, unsigned short value)
127{
128 volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
129 volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
130 u32 mii_control;
131 unsigned int timedout = 20;
132
133 while (*mii_control_reg & MAC_MII_BUSY) {
134 udelay(1000);
135 if (--timedout == 0) {
136 printf("au1x00_eth: miiphy_write busy timeout!!\n");
Shinya Kuribayashi4fbd0742007-10-27 15:22:33 +0900137 return -1;
Shinya Kuribayashif0132042007-10-27 15:00:25 +0900138 }
139 }
140
141 mii_control = MAC_SET_MII_SELECT_REG(reg) |
142 MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
143
144 *mii_data_reg = value;
145 *mii_control_reg = mii_control;
146 return 0;
147}
148#endif
149
wdenk5da627a2003-10-09 20:09:04 +0000150static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
151 volatile mac_fifo_t *fifo_tx =
152 (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
153 int i;
154 int res;
155
156 /* tx fifo should always be idle */
157 fifo_tx[next_tx].len = length;
158 fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
159 au_sync();
160
161 udelay(1);
162 i=0;
163 while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
164 if(i>MAX_WAIT){
165 printf("TX timeout\n");
166 break;
167 }
168 udelay(1);
169 i++;
170 }
171
172 /* Clear done bit */
173 fifo_tx[next_tx].addr = 0;
174 fifo_tx[next_tx].len = 0;
175 au_sync();
176
177 res = fifo_tx[next_tx].status;
178
179 next_tx++;
180 if(next_tx>=NO_OF_FIFOS){
181 next_tx=0;
182 }
183 return(res);
184}
185
186static int au1x00_recv(struct eth_device* dev){
187 volatile mac_fifo_t *fifo_rx =
188 (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
189
190 int length;
191 u32 status;
192
193 for(;;){
194 if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
195 /* Nothing has been received */
196 return(-1);
197 }
198
199 status = fifo_rx[next_rx].status;
200
201 length = status&0x3FFF;
202
203 if(status&RX_ERROR){
204 printf("Rx error 0x%x\n", status);
205 }
206 else{
207 /* Pass the packet up to the protocol layers. */
208 NetReceive(NetRxPackets[next_rx], length - 4);
209 }
210
211 fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE;
212
213 next_rx++;
214 if(next_rx>=NO_OF_FIFOS){
215 next_rx=0;
216 }
217 } /* for */
218
219 return(0); /* Does anyone use this? */
220}
221
222static int au1x00_init(struct eth_device* dev, bd_t * bd){
223
224 volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
225 volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
226 volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
227 volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
228 volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
229 volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
230 volatile mac_fifo_t *fifo_tx =
231 (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
232 volatile mac_fifo_t *fifo_rx =
233 (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
234 int i;
235
Wolfgang Denk4bc12f12005-09-24 22:05:40 +0200236 next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
237 next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);
wdenk5da627a2003-10-09 20:09:04 +0000238
239 /* We have to enable clocks before releasing reset */
240 *macen = MAC_EN_CLOCK_ENABLE;
241 udelay(10);
242
243 /* Enable MAC0 */
244 /* We have to release reset before accessing registers */
245 *macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
246 MAC_EN_RESET1|MAC_EN_RESET2;
247 udelay(10);
248
249 for(i=0;i<NO_OF_FIFOS;i++){
250 fifo_tx[i].len = 0;
251 fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
252 fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))|RX_DMA_ENABLE;
253 }
254
255 /* Put mac addr in little endian */
wdenk5da627a2003-10-09 20:09:04 +0000256#define ea eth_get_dev()->enetaddr
Wolfgang Denk265817c2005-09-25 00:53:22 +0200257 *mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
258 *mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
259 (ea[1] << 8) | (ea[0] ) ;
wdenk5da627a2003-10-09 20:09:04 +0000260#undef ea
wdenk5da627a2003-10-09 20:09:04 +0000261 *mac_mcast_low = 0;
262 *mac_mcast_high = 0;
263
wdenk63f34912004-01-02 15:01:32 +0000264 /* Make sure the MAC buffer is in the correct endian mode */
265#ifdef __LITTLE_ENDIAN
266 *mac_ctrl = MAC_FULL_DUPLEX;
267 udelay(1);
268 *mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
269#else
wdenk5da627a2003-10-09 20:09:04 +0000270 *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
271 udelay(1);
272 *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
wdenk63f34912004-01-02 15:01:32 +0000273#endif
wdenk5da627a2003-10-09 20:09:04 +0000274
275 return(1);
276}
277
278static void au1x00_halt(struct eth_device* dev){
Thomas Lange87423d72009-04-24 16:22:16 +0200279 volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
280
281 /* Put MAC0 in reset */
282 *macen = 0;
wdenk5da627a2003-10-09 20:09:04 +0000283}
284
285int au1x00_enet_initialize(bd_t *bis){
286 struct eth_device* dev;
287
Wolfgang Denk95515302006-03-13 01:00:22 +0100288 if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
289 puts ("malloc failed\n");
Shinya Kuribayashi5dfb3ee2008-10-19 12:08:50 +0900290 return -1;
Wolfgang Denk95515302006-03-13 01:00:22 +0100291 }
292
wdenk5da627a2003-10-09 20:09:04 +0000293 memset(dev, 0, sizeof *dev);
294
Wolfgang Denk95515302006-03-13 01:00:22 +0100295 sprintf(dev->name, "Au1X00 ethernet");
wdenk5da627a2003-10-09 20:09:04 +0000296 dev->iobase = 0;
297 dev->priv = 0;
298 dev->init = au1x00_init;
299 dev->halt = au1x00_halt;
300 dev->send = au1x00_send;
301 dev->recv = au1x00_recv;
302
303 eth_register(dev);
304
Jon Loeliger44312832007-07-09 19:06:00 -0500305#if defined(CONFIG_CMD_MII)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200306 miiphy_register(dev->name,
307 au1x00_miiphy_read, au1x00_miiphy_write);
308#endif
309
wdenk5da627a2003-10-09 20:09:04 +0000310 return 1;
311}