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Graeme Russc620c012008-12-07 10:28:57 +11001/*
2 * (C) Copyright 2008
3 * Graeme Russ, graeme.russ@gmail.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/io.h>
Graeme Russ3c7db1b2011-08-04 22:05:09 +100026#include <asm/arch/sc520.h>
Graeme Russ8fd80562010-04-24 00:05:55 +100027#include <net.h>
28#include <netdev.h>
Graeme Russc620c012008-12-07 10:28:57 +110029
30#ifdef CONFIG_HW_WATCHDOG
31#include <watchdog.h>
32#endif
33
34#include "hardware.h"
35
36DECLARE_GLOBAL_DATA_PTR;
37
Graeme Russe9bf8872011-04-04 15:18:59 +100038unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
39
Graeme Russ880c59e2010-04-24 00:05:58 +100040static void enet_timer_isr(void);
41static void enet_toggle_run_led(void);
Graeme Russc083e4b2011-02-12 15:11:47 +110042static void enet_setup_pars(void);
Graeme Russ880c59e2010-04-24 00:05:58 +100043
Graeme Russc620c012008-12-07 10:28:57 +110044/*
45 * Miscellaneous platform dependent initializations
46 */
Graeme Russ1c409bc2009-11-24 20:04:21 +110047int board_early_init_f(void)
Graeme Russc620c012008-12-07 10:28:57 +110048{
Graeme Russ420c7c02011-02-12 15:11:45 +110049 u16 pio_out_cfg = 0x0000;
Graeme Russc620c012008-12-07 10:28:57 +110050
Graeme Russ420c7c02011-02-12 15:11:45 +110051 /* Configure General Purpose Bus timing */
52 writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt);
53 writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw);
54 writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff);
55 writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw);
56 writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff);
57 writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw);
58 writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff);
Graeme Russc620c012008-12-07 10:28:57 +110059
Graeme Russ420c7c02011-02-12 15:11:45 +110060 /* Configure Programmable Input/Output Pins */
61 writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0);
62 writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16);
63 writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16);
64 writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0);
65 writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs);
66 writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel);
67
68 /*
69 * Turn off top board
70 * Set StrataFlash chips to 16-bit width
71 * Set StrataFlash chips to normal (non reset/power down) mode
72 */
73 pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR;
74 pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH;
75 pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE;
76 pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE;
77 writew(pio_out_cfg, &sc520_mmcr->pioset15_0);
78
79 /* Turn off auxiliary power output */
80 writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0);
81
82 /* Clear FPGA program mode */
83 writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
84
Graeme Russc083e4b2011-02-12 15:11:47 +110085 enet_setup_pars();
Graeme Russc620c012008-12-07 10:28:57 +110086
87 /* Disable Watchdog */
Graeme Russ64a0a492010-04-24 00:05:37 +100088 writew(0x3333, &sc520_mmcr->wdtmrctl);
89 writew(0xcccc, &sc520_mmcr->wdtmrctl);
90 writew(0x0000, &sc520_mmcr->wdtmrctl);
Graeme Russc620c012008-12-07 10:28:57 +110091
92 /* Chip Select Configuration */
Graeme Russ420c7c02011-02-12 15:11:45 +110093 writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl);
94 writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl);
95 writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);
Graeme Russc620c012008-12-07 10:28:57 +110096
Graeme Russ420c7c02011-02-12 15:11:45 +110097 writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl);
98 writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl);
99 writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl);
Graeme Russ870847f2011-02-12 15:11:38 +1100100
Graeme Russ420c7c02011-02-12 15:11:45 +1100101 writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl);
102 writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb);
Graeme Russc620c012008-12-07 10:28:57 +1100103
Graeme Russ870847f2011-02-12 15:11:38 +1100104 /* enable posted-writes */
Graeme Russ420c7c02011-02-12 15:11:45 +1100105 writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl);
Graeme Russ870847f2011-02-12 15:11:38 +1100106
Graeme Russ1c409bc2009-11-24 20:04:21 +1100107 return 0;
108}
109
Graeme Russc083e4b2011-02-12 15:11:47 +1100110static void enet_setup_pars(void)
111{
112 /*
113 * PARs 11 and 12 are 2MB SRAM @ 0x19000000
114 *
115 * These are setup now because older version of U-Boot have them
116 * mapped to a different PAR which gets clobbered which prevents
117 * using SRAM for warm-booting a new image
118 */
119 writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]);
120 writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]);
121
122 /* PARs 0 and 1 are Compact Flash slots (4kB each) */
123 writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]);
124 writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]);
125
126 /* PAR 2 is used for Cache-As-RAM */
127
128 /*
129 * PARs 5 through 8 are additional NS16550 UARTS
130 * 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8
131 */
132 writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]);
133 writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]);
134 writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]);
135 writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]);
136
137 /* PARs 9 and 10 are 32MB StrataFlash @ 0x10000000 */
138 writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[9]);
139 writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[10]);
140
141 /* PAR 13 is 4kB DPRAM @ 0x18100000 (implemented in FPGA) */
142 writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]);
143
144 /*
145 * PAR 14 is Low Level I/O (LEDs, Hex Switches etc)
146 * Already configured in board_init16 (eNET_start16.S)
147 *
148 * PAR 15 is Boot ROM
149 * Already configured in board_init16 (eNET_start16.S)
150 */
151}
152
153
Graeme Russ1c409bc2009-11-24 20:04:21 +1100154int board_early_init_r(void)
155{
156 /* CPU Speed to 100MHz */
157 gd->cpu_clk = 100000000;
158
Graeme Russc620c012008-12-07 10:28:57 +1100159 /* Crystal is 33.000MHz */
160 gd->bus_clk = 33000000;
161
162 return 0;
163}
164
Graeme Russc620c012008-12-07 10:28:57 +1100165void show_boot_progress(int val)
166{
167 uchar led_mask;
168
169 led_mask = 0x00;
170
171 if (val < 0)
172 led_mask |= LED_ERR_BITMASK;
173
174 led_mask |= (uchar)(val & 0x001f);
175 outb(led_mask, LED_LATCH_ADDRESS);
176}
177
178
179int last_stage_init(void)
180{
181 int minor;
182 int major;
183
184 major = minor = 0;
185
Graeme Russ880c59e2010-04-24 00:05:58 +1000186 outb(0x00, LED_LATCH_ADDRESS);
187
Graeme Russcfbe8612011-02-12 15:11:48 +1100188 register_timer_isr(enet_timer_isr);
Graeme Russ880c59e2010-04-24 00:05:58 +1000189
Graeme Russc620c012008-12-07 10:28:57 +1100190 printf("Serck Controls eNET\n");
191
192 return 0;
193}
194
Graeme Russcfbe8612011-02-12 15:11:48 +1100195ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
Graeme Russc620c012008-12-07 10:28:57 +1100196{
197 if (banknum == 0) { /* non-CFI boot flash */
198 info->portwidth = FLASH_CFI_8BIT;
199 info->chipwidth = FLASH_CFI_BY8;
200 info->interface = FLASH_CFI_X8;
201 return 1;
Graeme Russcfbe8612011-02-12 15:11:48 +1100202 } else {
Graeme Russc620c012008-12-07 10:28:57 +1100203 return 0;
Graeme Russcfbe8612011-02-12 15:11:48 +1100204 }
Graeme Russc620c012008-12-07 10:28:57 +1100205}
Graeme Russ8fd80562010-04-24 00:05:55 +1000206
207int board_eth_init(bd_t *bis)
208{
209 return pci_eth_init(bis);
210}
Graeme Russ4a4c31a2010-04-24 00:05:56 +1000211
212void setup_pcat_compatibility()
213{
214 /* disable global interrupt mode */
215 writeb(0x40, &sc520_mmcr->picicr);
216
217 /* set all irqs to edge */
218 writeb(0x00, &sc520_mmcr->pic_mode[0]);
219 writeb(0x00, &sc520_mmcr->pic_mode[1]);
220 writeb(0x00, &sc520_mmcr->pic_mode[2]);
221
222 /*
223 * active low polarity on PIC interrupt pins,
224 * active high polarity on all other irq pins
225 */
Graeme Russ63a90bf2011-11-08 02:33:16 +0000226 writew(0x0000, &sc520_mmcr->intpinpol);
Graeme Russ4a4c31a2010-04-24 00:05:56 +1000227
Graeme Russd881ea52011-02-12 15:11:41 +1100228 /*
229 * PIT 0 -> IRQ0
230 * RTC -> IRQ8
231 * FP error -> IRQ13
232 * UART1 -> IRQ4
233 * UART2 -> IRQ3
234 */
Graeme Russ4a4c31a2010-04-24 00:05:56 +1000235 writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
236 writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
237 writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
Graeme Russd881ea52011-02-12 15:11:41 +1100238 writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]);
239 writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]);
Graeme Russ4a4c31a2010-04-24 00:05:56 +1000240
241 /* Disable all other interrupt sources */
242 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
243 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]);
244 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
245 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
246 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
Graeme Russ4a4c31a2010-04-24 00:05:56 +1000247 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
248 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
249 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
250 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap);
251}
Graeme Russ880c59e2010-04-24 00:05:58 +1000252
253void enet_timer_isr(void)
254{
Graeme Russ63a90bf2011-11-08 02:33:16 +0000255 static long enet_ticks;
Graeme Russ880c59e2010-04-24 00:05:58 +1000256
257 enet_ticks++;
258
259 /* Toggle Watchdog every 100ms */
260 if ((enet_ticks % 100) == 0)
261 hw_watchdog_reset();
262
263 /* Toggle Run LED every 500ms */
264 if ((enet_ticks % 500) == 0)
265 enet_toggle_run_led();
266}
267
268void hw_watchdog_reset(void)
269{
270 /* Watchdog Reset must be atomic */
271 long flag = disable_interrupts();
272
273 if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT)
274 sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT;
275 else
276 sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT;
277
278 if (flag)
279 enable_interrupts();
280}
281
282void enet_toggle_run_led(void)
283{
Graeme Russ63a90bf2011-11-08 02:33:16 +0000284 unsigned char leds_state = inb(LED_LATCH_ADDRESS);
Graeme Russ880c59e2010-04-24 00:05:58 +1000285 if (leds_state & LED_RUN_BITMASK)
Graeme Russ63a90bf2011-11-08 02:33:16 +0000286 outb(leds_state & ~LED_RUN_BITMASK, LED_LATCH_ADDRESS);
Graeme Russ880c59e2010-04-24 00:05:58 +1000287 else
288 outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);
289}